A PD control circuit for spaceborne SAR payload

Abstract

The present application provides a PD control circuit for a satellite-borne SAR payload, including a PD driving unit, a PD logic unit, a TYPEC interface unit, and a SOC unit, wherein the PD logic unit includes a connected logic circuit and a driving circuit; the PD driving unit is respectively connected to the logic circuit, the driving circuit, and the TYPEC interface unit, the output end of the driving circuit is connected to the internal load of the payload, and the PD driving unit controls the logic circuit and the driving circuit through the output driving signal to provide power supply to the load; the TYPEC interface unit is connected to the SOC unit, and the image is burned from the PC end to the SOC unit through a data line to complete the image burning of the system. The present application can provide a certain power supply capacity for the load, and in the absence of a network, it can be directly burned from the computer end to the SOC chip through a data line to realize the update and burning of the image, and ensure the normal operation of the internal load of the payload.

Description

Technical Field

[0001] The present application belongs to the technical field of detection payloads, and in particular, relates to a satellite-borne SAR payload PD control circuit. Background Art

[0002] As detection payloads become more and more integrated, the requirements for system power supply are also getting higher and higher. Most traditional antenna payload designs only have one power supply interface, which is relatively simple. When conducting environmental tests or tests in the field, it is often necessary to carry power supply equipment. In addition, traditional R&D designs do not use SOCs for system operations. The circuit system of this invention uses SOCs with Linux system operations. When burning the system image, this SOC often needs to be downloaded and burned through the network. In a complex environment, when conducting field tests, when the image file needs to be updated and burned into the SOC, the system image cannot be burned without a network. Summary of the invention

[0003] In view of this, the present application aims to propose a satellite-borne SAR payload PD control circuit to solve the problem of burning the system image through the PD control circuit in the absence of a network.

[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0005] The present application provides a satellite-borne SAR payload PD control circuit, comprising a PD driving unit, a PD logic unit, a TYPEC interface unit and a SOC unit, wherein the PD logic unit comprises a connected logic circuit and a driving circuit;

[0006] The PD driving unit is connected to the logic circuit, the driving circuit and the TYPEC interface unit respectively, the output end of the driving circuit is connected to the internal load of the load, and the PD driving unit controls the operation of the logic circuit and the driving circuit through the output driving signal to provide power supply to the load;

[0007] The TYPEC interface unit is connected to the SOC unit, and image burning is performed from the PC end to the SOC unit through a data line to complete the image burning of the system.

[0008] Further, the logic circuit is composed of a tri-state buffer, a logic AND gate, an inverter and a logic XOR gate;

[0009] The PD driving unit comprises a PD driving chip, two IO pins of the PD driving chip are respectively connected to the input pins of the first gate device and the second gate device of the tri-state buffer, one of the IO pins is further connected to the enable pin of the third gate device of the tri-state buffer through a first logic AND gate, and the output pin of the third gate device is connected to the enable pins of the first gate device and the second gate device;

[0010] The first power input pin of the PD driving unit is respectively connected to the third gate device and the two inverters, wherein the output pin of one of the inverters is respectively connected to the first logic AND gate and the first gate device through a first pull-up resistor, and the output pin of the other inverter is respectively connected to the first logic AND gate and the second gate device through a second pull-up resistor;

[0011] The output pins of the first gate device and the second gate device are connected to the input pin of the logic XOR gate, the output pin of the logic XOR gate is connected to one of the input pins of the second logic AND gate, the other input pin of the second logic AND gate is connected to the second power input pin of the PD driving unit, and the output end of the second logic gate is connected to the driving circuit.

[0012] Furthermore, the tri-state buffer is a 74LVC1G126GW model, the logic AND gate is a NC7SZ08 model, the inverter is a NL27WZ04DFT2G model, and the logic XOR gate is a NL17SG86DFT2G model.

[0013] Further, the driving circuit includes a first driving link and a second driving link connected to each other;

[0014] Among them, the first driving link includes a power chip, an enable pin of the power chip is connected to the drain of the first switch tube, the source of the first switch tube is connected to the power supply end, the gate of the first switch tube is connected to the drain of the second switch tube, the gate of the second switch tube is connected to the IO pin of the PD driver chip, the source of the second switch tube is connected to the drain of the third switch tube, the gate of the third switch tube is connected to the IO pin of the PD driver chip, the output pin of the power chip is connected to the fourth switch tube through multiple parallel resistors, and the gate of the fourth switch tube is connected to the IO pin of the PD driver chip.

[0015] Further, the second drive link includes a fifth switch tube, the gate of the fifth switch tube is connected to the gate of the second switch tube, the drain of the fifth switch tube is connected to the drains of the sixth switch tube, the seventh switch tube and the gate of the eighth switch tube, the gate of the sixth switch tube is connected to the gate of the third switch tube, the drain of the eighth switch tube is connected to the drain of the tenth switch tube, and the gate of the tenth switch tube is connected to the output pin of the second logic AND gate;

[0016] The source of the seventh switch tube is connected to the drain of the ninth switch tube, the source of the ninth switch tube is connected to the source of the eleventh switch tube, the drain of the eleventh switch tube is connected to the output pin of the power chip, and the gate of the eleventh switch tube is connected to the drain of the eighth switch tube;

[0017] The drain of the ninth switch tube is connected to the load and the TYPEC interface unit as an output end.

[0018] Furthermore, the power chip is model AP22615AWU-7.

[0019] Further, the first switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube and the eleventh switch tube are NMOS tubes;

[0020] The second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube and the tenth switch tube are PMOS tubes.

[0021] Compared with the prior art, the spaceborne SAR payload PD control circuit described in this application has the following beneficial effects:

[0022] The satellite-borne SAR payload PD control circuit described in the present application can, on the one hand, quickly release the charge of internal devices and the static electricity accumulation of logic circuits and loads after the load is powered off; on the other hand, it can provide a certain power supply capacity for the load, and in the absence of a network, it can be directly burned from the computer to the SOC chip through a data cable, thereby realizing the update and burning of the image, while ensuring the normal operation of the internal load of the payload. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0024] Figure 1 This is an overall block diagram of a satellite-borne SAR payload PD control circuit according to an embodiment of the present application;

[0025] Figure 2This is a schematic diagram of a PD control circuit for a satellite-borne SAR payload according to an embodiment of the present application;

[0026] Figure 3 This is a circuit diagram of the first part of the logic circuit described in the embodiment of the present application;

[0027] Figure 4 A circuit diagram of the second part of the logic circuit described in the embodiment of the present application;

[0028] Figure 5 This is a circuit diagram of the first part of the driving circuit described in the embodiment of the present application;

[0029] Figure 6 A circuit diagram of the second part of the driving circuit described in an embodiment of the present application;

[0030] Figure 7 This is a circuit diagram of the PD driver chip described in the embodiment of the present application;

[0031] Figure 8 This is a TYPEC interface circuit diagram described in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0033] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] See also Figure 1 and Figure 2 As shown, the present application provides a satellite-borne SAR payload PD control circuit, including a PD driving unit, a PD logic unit, a TYPEC interface unit and a SOC unit, wherein the PD logic unit includes a connected logic circuit and a driving circuit;

[0035] The PD driving unit is connected to the logic circuit, the driving circuit and the TYPEC interface unit respectively. The output end of the driving circuit is connected to the internal load of the load. The PD driving unit controls the logic circuit and the driving circuit through the output driving signal to provide power supply to the load.

[0036] The TYPEC interface unit is connected to the SOC unit, and the image is burned from the PC to the SOC unit through a data cable to complete the image burning of the system.

[0037] Specifically, in this embodiment, the control circuit controls the PD driver chip to send a driving signal, and transmits the driving signal to each combinational logic device, so as to obtain a highly reliable stable signal, and the obtained stable signal controls the action of the driving circuit. On the one hand, after the load is powered off, the charge of the internal device and the static electricity accumulation of the logic circuit and the load can be quickly released; on the other hand, a certain power supply capacity can be provided for the load, and in the absence of a network, the data cable can be directly burned from the computer end to the SOC chip, thereby realizing the update and burning of the image, and at the same time ensuring the normal operation of the internal load of the load.

[0038] The circuit architecture described in this application is independent and optimizes the circuit structure compared to the traditional design, from the basic control chip application, to the construction of the combined logic circuit, and then to the drive circuit built by the MOS tube. The traditional design relies solely on the main control chip to realize the direct output signal of the logic of synchronous timing or asynchronous timing, and the traditional digital circuit design relies solely on the main control chip to complete the control. Its defect is that the output signal of the main control chip will have the risk of false triggering or competition and risk, which will cause the signal output to be unstable. The signal output by the circuit of this application is more stable, and the power consumption is reduced. Even in the process of burning the image, the internal load of the load is not affected.

[0039] In some embodiments, Figure 3 As shown, the logic circuit is composed of a tri-state buffer, a logic AND gate, an inverter and a logic XOR gate;

[0040] The PD driving unit includes a PD driving chip, and the chip circuit diagram is shown in Figure 7. Two IO pins of the PD driving chip are respectively connected to the input pins of the first gate device U88 and the second gate device U89 of the tri-state buffer, and one of the IO pins is also connected to the enable pin of the third gate device U86 of the tri-state buffer through the first logic AND gate U84, and the output pin of the third gate device U86 is connected to the enable pins of the first gate device U88 and the second gate device U89;

[0041] The 35pin of the PD driving unit is respectively connected to the third gate device U86 and two inverters, wherein the output pin of one inverter U87A is respectively connected to the first logic AND gate U84 and the first gate device U88 through the first pull-up resistor R572, and the output pin of the other inverter U87B is respectively connected to the first logic AND gate U84 and the second gate device U89 through the second pull-up resistor R581;

[0042] like Figure 4 As shown, the output pins of the first gate device U88 and the second gate device U89 are connected to the input pin of the logic XOR gate U90, the output pin of the logic XOR gate U90 is connected to one of the input pins of the second logic AND gate U92, the other input pin of the second logic AND gate U92 is connected to the 36pin of the PD driving unit, and the output end of the second logic gate U92 is connected to the driving circuit.

[0043] Specifically, the control circuit is composed of several major categories, including power chips, resistors, capacitors, PD driver chips, etc. The model of the PD driver chip U162 is CYPD4226, which belongs to the EZ-PD CCG4 series. It is a dual USB-C interface control chip. The chip uses Cypress's proprietary M0S8 technology, built-in 32-bit ARM M0 processor, with 128KB flash memory and 8kB memory.

[0044] In this embodiment, the three-state buffer adopts a three-state single-channel buffer of model 74LVC1G126, and its truth table is as follows:

[0045] OE (Enable) A (input) Y (output) H H H H L L L X Z

[0046] The logic AND gate uses the NC7SZ08 logic device, and its logic principle is Y=A*B.

[0047] The inverter uses the NL27WZ04DFT2G model inverter, and its truth table is as follows;

[0048] A (input) Y (output) L H H L

[0049] The logic XOR gate uses the NL17SG86DFT2G logic device, and its logic principle is: Y=(A+B)'.

[0050] The logic control of the logic circuit is as follows:

[0051] When the DC_IN_GATE_CCG4 signal is low, U87A and U87B both output high, U84 outputs high, and U86 outputs high;

[0052] When the VBUS_C_CTRL_P1 signal is a low pulse level, U88 outputs a low level. When the VBUS_C_CTRL_P2 signal is a low pulse level, U89 outputs a low level. At this time, U90 outputs a high level. When GPIO_PMOS_ON is a high level, U92 outputs a high level.

[0053] In some embodiments, the drive circuit includes a first drive link and a second drive link connected to each other;

[0054] Among them, Figure 5 As shown, the first drive link includes a power chip U91 (this embodiment uses the AP22615AWU-7 model chip, the VIN pin of the U91 chip is powered by a 5V voltage, and the FAULT* pin is left floating. The VOUT pin is the output, the ILIM pin is connected to the current limiting resistor, and the GND pin is grounded), the EN pin of the power chip U91 is connected to the D pole of the first switch tube Q20, the S pole of the first switch tube Q20 is connected to the power supply end, the G pole of the first switch tube Q20 is connected to the D pole of the second switch tube Q57B, the G pole of the second switch tube Q57B is connected to the IO pin of the PD driver chip, the S pole of the second switch tube Q57B is connected to the D pole of the third switch tube Q57A, the G pole of the third switch tube Q57A is connected to the IO pin of the PD driver chip, the VOUT pin of the power chip U91 is connected to the fourth switch tube Q18 through multiple parallel resistors (R584, R585, and R587 are connected in three groups in parallel), the G pole of the fourth switch tube Q18 is connected to one of the IO pins of the PD driver chip, and the S pole of the fourth switch tube Q18 is grounded.

[0055] Among them, Figure 6 As shown, the second driving link includes a fifth switch tube Q47B, a G pole of the fifth switch tube Q47B is connected to a G pole of the second switch tube Q57B, a D pole of the fifth switch tube Q57B is connected to a sixth switch tube Q47A, a D pole of the seventh switch tube Q19 and a G pole of the eighth switch tube Q21, a G pole of the sixth switch tube Q47A is connected to a G pole of the third switch tube Q57A, an S pole of the sixth switch tube Q47A is grounded, a D pole of the eighth switch tube Q21 is connected to a D pole of the tenth switch tube Q67A, and a G pole of the tenth switch tube Q67A is connected to an output pin of the second logic AND gate U92;

[0056] The S pole of the seventh switch tube Q19 is connected to the D pole of the ninth switch tube Q17, the S pole of the ninth switch tube Q17 is connected to the S pole of the eleventh switch tube Q16, the S pole of the eleventh switch tube Q16 is connected to the VOUT pin of the power chip U91, and the G pole of the eleventh switch tube Q16 is connected to the D pole of the eighth switch tube Q21;

[0057] The D pole of the ninth switch tube Q17 is connected to the load and the TYPEC interface unit as an output terminal. The TYPEC interface unit circuit is as follows: Figure 8 shown.

[0058] Specifically, in this embodiment, when U91 is powered by 5V, VBUS_C_CTRL_P2_R is at a high level, and VBUS_P_CTRL_P2 is at a high level, the G poles of Q57A and Q57B are both turned on, and the G pole of Q20 meets the turn-on condition. At this time, pin 4 of U91 is at a high level.

[0059] When U91 outputs 5V voltage and VBUS_DISCHARGE_P2 outputs high level, Q18 is turned on and the MOS tube is turned on for internal discharge of the circuit.

[0060] When VBUS_C_CTRL_P2_R is at a high level and VBUS_P_CTRL_P2 is at a high level, the G poles of Q47A and Q47B are at a high level, and the MOS tube meets the conduction condition.

[0061] Q19 and Q21 are turned on. After Q21 is turned on, the voltage of D meets the turn-on condition of Q16. Q16 is turned on, the Vgs of Q17 meets the turn-on condition, Q17 is also turned on, and USBC2_VBUS outputs 5V to power the load, thereby improving the load capacity.

[0062] Based on the connection relationship of the above components, the specific implementation logic of the control circuit is as follows:

[0063] After the PD driver chip is powered on, CC_PORT1 will detect whether the data cable is inserted into the TYPE C port in the forward or reverse direction. If it is inserted in the forward direction, the host uses CC1 for communication; otherwise, it uses CC2.

[0064] The 12th pin of CYPD4226 sends out the VBUS_C_CTRL_P1 signal, and the 38th pin of the driver chip sends out the VBUS_C_CTRL_P2 signal. The VBUS_C_CTRL_P1 signal and the VBUS_C_CTRL_P2 signal are output through the logic AND gate of U84 as the DC_IN_GATE_OE signal to the OE enable pins of U86, U88, and U89; at the same time, the two groups of signals are respectively passed through the three-state single-channel buffer to obtain a more stable signal.

[0065] U88 and U89 output VBUS_C_CTRL_P1_R and VBUS_C_CTRL_P2_R signals respectively. The VBUS_C_CTRL_P1_R signal and the VBUS_C_CTRL_P2_R signal are input to U90 together. U90 outputs the VBUS_C_CTRL_OR signal to pin 1 of the logic AND gate of U92. At the same time, the 36pin of the CYPD4226 driver outputs GPIO_PMOS_ON (signal high level is valid) to pin 2 of U92, and finally outputs the GPIO_PMOS_ON_CTRL signal (high level is valid).

[0066] The 40pin of the CYPD4226 driver chip outputs the VBUS_DISCHARGE_P2 signal, which is used to turn on the MOS tube of Q18 so that it can discharge quickly after the internal power is cut off without accumulating charge. The 39pin of the CYPD4226 driver chip outputs the VBUS_P_CTRL_P2 signal, which turns on the MOS tube of Q47A (high level is valid).

[0067] The 35pin of the CYPD4226 driver chip outputs the DC_IN_GATE_CCG4 signal, which is given to the 2nd pin of U86 and output from the 4th pin of U86 in order to obtain a stable level signal. At the same time, the DC_IN_GATE_CCG4 signal passes through U87 (inverter), so that when controlling the logic circuit, VBUS_C_CTRL_P1 and VBUS_C_CTRL_P2 provide a certain level signal.

[0068] The logic circuit finally outputs a 5V voltage to power the internal load of the payload. When the payload is connected to the computer through a data cable, the computer configures the corresponding file and can burn the image. At the same time, the internal load of the payload can also work normally.

[0069] In the control circuit, the PD driver chip not only obtains a more stable electrical level through a combinational logic circuit, but also solves the potential risk of false signal triggering, and controls the on or off of the MOS tube to realize circuit control.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

[0071] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A spaceborne SAR payload PD control circuit, characterized in that: It includes a PD driving unit, a PD logic unit, a TYPEC interface unit and a SOC unit, wherein the PD logic unit includes a connected logic circuit and a driving circuit; The PD driving unit is connected to the logic circuit, the driving circuit and the TYPEC interface unit respectively, the output end of the driving circuit is connected to the internal load of the load, and the PD driving unit controls the operation of the logic circuit and the driving circuit through the output driving signal to provide power supply to the load; The TYPEC interface unit is connected to the SOC unit, and image burning is performed from the PC end to the SOC unit through a data line to complete the image burning of the system; The logic circuit is composed of a tri-state buffer, a logic AND gate, an inverter and a logic XOR gate; The PD driving unit comprises a PD driving chip, two IO pins of the PD driving chip are respectively connected to the input pins of the first gate device and the second gate device of the tri-state buffer, one of the IO pins is further connected to the enable pin of the third gate device of the tri-state buffer through a first logic AND gate, and the output pin of the third gate device is connected to the enable pins of the first gate device and the second gate device; The first power input pin of the PD driving unit is respectively connected to the third gate device and the two inverters, wherein the output pin of one of the inverters is respectively connected to the first logic AND gate and the first gate device through a first pull-up resistor, and the output pin of the other inverter is respectively connected to the first logic AND gate and the second gate device through a second pull-up resistor; The output pins of the first gate device and the second gate device are connected to the input pin of the logic XOR gate, the output pin of the logic XOR gate is connected to one of the input pins of the second logic AND gate, the other input pin of the second logic AND gate is connected to the second power input pin of the PD driving unit, and the output end of the second logic gate is connected to the driving circuit.

2. A spaceborne SAR payload PD control circuit according to claim 1, characterized in that: The tri-state buffer is of model 74LVC1G126GW, the logic AND gate is of model NC7SZ08, the inverter is of model NL27WZ04DFT2G, and the logic XOR gate is of model NL17SG86DFT2G.

3. A spaceborne SAR payload PD control circuit according to claim 1, characterized in that: The driving circuit includes a first driving link and a second driving link connected to each other; Among them, the first driving link includes a power chip, an enable pin of the power chip is connected to the drain of the first switch tube, the source of the first switch tube is connected to the power supply end, the gate of the first switch tube is connected to the drain of the second switch tube, the gate of the second switch tube is connected to the IO pin of the PD driver chip, the source of the second switch tube is connected to the drain of the third switch tube, the gate of the third switch tube is connected to the IO pin of the PD driver chip, the output pin of the power chip is connected to the fourth switch tube through multiple parallel resistors, and the gate of the fourth switch tube is connected to the IO pin of the PD driver chip.

4. A spaceborne SAR payload PD control circuit according to claim 3, characterized in that: in, The second drive link includes a fifth switch tube, the gate of the fifth switch tube is connected to the gate of the second switch tube, the drain of the fifth switch tube is connected to the drains of the sixth switch tube, the seventh switch tube and the gate of the eighth switch tube, the gate of the sixth switch tube is connected to the gate of the third switch tube, the drain of the eighth switch tube is connected to the drain of the tenth switch tube, and the gate of the tenth switch tube is connected to the output pin of the second logic AND gate; The source of the seventh switch tube is connected to the drain of the ninth switch tube, the source of the ninth switch tube is connected to the source of the eleventh switch tube, the drain of the eleventh switch tube is connected to the output pin of the power chip, and the gate of the eleventh switch tube is connected to the drain of the eighth switch tube; The drain of the ninth switch tube is connected to the load and the TYPEC interface unit as an output end.

5. A spaceborne SAR payload PD control circuit according to claim 4, characterized in that: The power chip is model AP22615AWU-7.

6. A spaceborne SAR payload PD control circuit according to claim 4, characterized in that: The first switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube and the eleventh switch tube are PMOS tubes; The second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube and the tenth switch tube are NMOS tubes.

Images