Sub-power generation circuits and chips

Abstract

The sub-power supply generation circuit and chip provided by the embodiments of the present disclosure include: a startup current generation module, which generates a startup current; a target current generation module, which determines the on-current of the first branch according to the gate-source voltage of the first transistor, the gate-source voltage of the second transistor and the first resistor, and determines the upper node current mirrored to the second branch according to the on-current and the first mirror relationship between the first branch and the second branch, determines the lower node current mirrored to the second branch according to the on-current and the second mirror relationship between the first branch and the second branch, and determines the target current according to the lower node current and the upper node current, the on-current is positively correlated with the temperature coefficient, and the lower node current is greater than the upper node current; a sub-power supply voltage generation module, which determines the sub-power supply voltage according to the target current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor and the second resistor, and the gate-source voltage of the third transistor and the fourth transistor is negatively correlated with the temperature coefficient.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits and related technical fields, and in particular, to a sub-power generation circuit and chip. Background Art

[0002] Different types of chips have different power supply ranges. For factors such as static power consumption and power supply rejection ratio, some circuits within the chip require a low and relatively constant power supply to meet power supply requirements. Therefore, a circuit that generates a sub-regulator under the power supply voltage is used in many analog circuit designs.

[0003] In the prior art, the circuit for generating a sub-power supply with a low and constant power supply under the power supply voltage is relatively complex. Usually, bipolar devices are used to design the circuit. Bipolar devices have a large area, which makes the overall area of ​​the sub-power supply generation circuit larger. Summary of the Invention

[0004] The embodiments described herein provide a sub-power generation circuit and chip to solve the problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a sub-power supply generation circuit is provided, comprising: a startup current generation module, a target current generation module, and a sub-power supply voltage generation module, wherein the target current generation module comprises at least a first transistor, a second transistor, and a first resistor, wherein the width-to-length ratio of the first transistor is smaller than the width-to-length ratio of the second transistor, and the sub-power supply voltage generation module comprises at least a third transistor, a fourth transistor, and a second resistor;

[0006] Wherein, the starting current generating module is configured to generate a starting current;

[0007] The target current generating module is configured to, after receiving the startup current, determine the on-current of the first branch according to the gate-source voltage of the first transistor, the gate-source voltage of the second transistor, and the first resistor, determine an upper node current mirrored to the second branch according to the on-current and a first mirror relationship between the first branch and the second branch, determine a lower node current mirrored to the second branch according to the on-current and a second mirror relationship between the first branch and the second branch, and determine a target current according to the lower node current and the upper node current, wherein the on-current is positively correlated with the temperature coefficient, and the lower node current is greater than the upper node current;

[0008] The sub-power supply voltage generation module is configured to determine the sub-power supply voltage based on the target current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor and the second resistor, and the gate-source voltage of the third transistor and the fourth transistor are negatively correlated with the temperature coefficient.

[0009] In some embodiments of the present disclosure, the startup current generating module includes an initial current generating unit and a first mirror unit;

[0010] The initial current generating unit is configured to generate an initial current;

[0011] The first mirror unit is configured to mirror the initial current to the third branch to obtain a startup current.

[0012] In some embodiments of the present disclosure, the initial current generating unit includes a fifth transistor and a third resistor, and the initial current generating unit includes a sixth transistor and a seventh transistor, the first end of the third resistor and the control end of the fifth transistor are respectively electrically connected to the common ground node, the second end of the third resistor is electrically connected to the source end of the fifth transistor, the drain end of the fifth transistor is respectively electrically connected to the drain end of the sixth transistor, the control end of the sixth transistor and the control end of the seventh transistor, the source end of the sixth transistor and the source end of the seventh transistor are respectively electrically connected to the power supply voltage node, and the drain end of the seventh transistor outputs the startup current to the target current generating module.

[0013] In some embodiments of the present disclosure, the target current generating module further includes a second mirror unit and a third mirror unit;

[0014] The second mirror unit is configured to determine the upper node current mirrored to the second branch according to the conduction current and a first mirror relationship between the first branch and the second branch;

[0015] The third mirror unit is configured to determine a second mirror relationship between the first branch and the second branch based on the third mirror relationship between the first branch and the fourth branch and the fourth mirror relationship between the fourth branch and the second branch, and determine a lower node current mirrored to the second branch based on the conduction current and the second mirror relationship between the first branch and the second branch.

[0016] In some embodiments of the present disclosure, the second mirror unit includes an eighth transistor, a ninth transistor, and a tenth transistor, and the third mirror unit includes an eleventh transistor and a twelfth transistor. The drain terminal of the first transistor is electrically connected to the control terminal of the first transistor and the control terminal of the second transistor, respectively. The source terminal of the second transistor is electrically connected to the first end of the first resistor. The source terminals of the eighth transistor, the ninth transistor, and the tenth transistor are electrically connected to a power supply voltage node, respectively. The control terminal of the eighth transistor, the drain terminal of the eighth transistor, the control terminal of the ninth transistor, and the control terminal of the tenth transistor are electrically connected to the drain terminal of the second transistor, respectively. The drain terminal of the ninth transistor is electrically connected to the drain terminal of the eleventh transistor, the control terminal of the eleventh transistor, and the control terminal of the twelfth transistor, respectively. The drain terminal of the tenth transistor is electrically connected to the drain terminal of the twelfth transistor, and the source terminal of the first transistor, the second end of the first resistor, the source terminal of the eleventh transistor, and the source terminal of the twelfth transistor are electrically connected to a common ground node, respectively.

[0017] In some embodiments of the present disclosure, the sub-power supply voltage generating module includes a fourth mirror unit and a sub-power supply voltage determining unit;

[0018] The fourth mirror unit is configured to determine a mirror current mirrored to the sixth branch according to the target current and a fifth mirror relationship between the fifth branch and the sixth branch;

[0019] The sub-power supply voltage determination unit is configured to determine the sub-power supply current of the sub-power supply voltage branch based on the mirror current and a sixth mirror relationship between the sixth branch and the sub-power supply voltage branch, and to determine the sub-power supply voltage based on the sub-power supply current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor, and the second resistor.

[0020] In some embodiments of the present disclosure, the fourth mirror unit includes a thirteenth transistor and a fourteenth transistor, and the sub-power supply voltage determination unit includes a fifteenth transistor, the third transistor, the fourth transistor, the second resistor and a twenty-first transistor. The source terminal of the thirteenth transistor and the source terminal of the fourteenth transistor are respectively electrically connected to the power supply voltage node, the control terminal of the thirteenth transistor, the control terminal of the fourteenth transistor and the drain terminal of the fourteenth transistor are respectively electrically connected to the drain terminal of the fifteenth transistor, the drain terminal of the thirteenth transistor receives a target current, the control terminal of the fifteenth transistor is respectively electrically connected to the control terminal of the third transistor, the drain terminal of the third transistor and the source terminal of the fourth transistor, the control terminal of the fourth transistor and the drain terminal of the fourth transistor are electrically connected to the first end of the second resistor, the second end of the second resistor and the drain terminal of the twenty-first transistor are respectively electrically connected to the sub-power supply voltage node, and the source terminal of the twenty-first transistor is electrically connected to the power supply voltage node.

[0021] In some embodiments of the present disclosure, the circuit further includes a circuit protection module, which is configured to withstand high-voltage signals of each branch and protect transistors of each branch.

[0022] The circuit protection module includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a fourth resistor; the drain terminal of the sixteenth transistor is electrically connected to the control terminal of the sixteenth transistor, the control terminal of the seventeenth transistor, the control terminal of the eighteenth transistor and the control terminal of the nineteenth transistor, respectively; the source terminal of the sixteenth transistor is electrically connected to the drain terminal of the first transistor, the drain terminal of the seventeenth transistor is electrically connected to the first terminal of the fourth resistor and the control terminal of the twentieth transistor, respectively; the second terminal of the fourth resistor is electrically connected to the drain terminal of the eighth transistor, and the second terminal of the eighth transistor is electrically connected to the drain terminal of the eighth transistor. The source terminal of the tenth transistor is electrically connected to the drain terminal of the ninth transistor, the drain terminal of the twentieth transistor is electrically connected to the drain terminal of the eleventh transistor, the drain terminal of the eighteenth transistor is electrically connected to the drain terminal of the tenth transistor, the source terminal of the eighteenth transistor is electrically connected to the drain terminal of the twelfth transistor, the drain terminal of the nineteenth transistor is electrically connected to the drain terminal of the fourteenth transistor, the source terminal of the nineteenth transistor is electrically connected to the drain terminal of the fifteenth transistor, the source terminal of the twenty-first transistor is electrically connected to the power supply voltage node, the drain terminal of the twenty-first transistor is electrically connected to the sub-power supply voltage output node, and the control terminal of the twenty-first transistor is electrically connected to the drain terminal of the tenth transistor and the drain terminal of the thirteenth transistor respectively.

[0023] According to a second aspect of the present disclosure, a chip is provided, comprising the sub-power generation circuit described in the first aspect.

[0024] The embodiments of the present disclosure provide a sub-power supply generation circuit and chip, a startup current generation module, which generates a startup current; a target current generation module, which, after receiving the startup current, determines the on-current of the first branch according to the gate-source voltage of the first transistor, the gate-source voltage of the second transistor and the first resistor, and determines the upper node current mirrored to the second branch according to the on-current and the first mirror relationship between the first branch and the second branch, determines the lower node current mirrored to the second branch according to the on-current and the second mirror relationship between the first branch and the second branch, and determines the target current according to the lower node current and the upper node current, the on-current is positively correlated with the temperature coefficient, and the lower node current is greater than the upper node current; a sub-power supply voltage generation module, which determines the sub-power supply voltage according to the target current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor and the second resistor, and the gate-source voltages of the third transistor and the fourth transistor are negatively correlated with the temperature coefficient. A current that is positively correlated with the temperature coefficient is generated in the sub-power supply voltage branch through the target current generation module. Combined with the characteristics of the gate-source voltage of the third transistor and the fourth transistor in the sub-power supply voltage branch (negatively correlated with the temperature coefficient), when the mirror relationship between the branches is configured, the sub-power supply voltage generated at the sub-power supply voltage node is independent of the preparation process, voltage and temperature of the transistor, and the generated sub-power supply voltage varies little with PVT (process, voltage and temperature).

[0025] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0027] Figure 1 This is a schematic structural diagram of a sub-power generation circuit provided by an embodiment of the present disclosure;

[0028] Figure 2 This is a schematic diagram of a specific circuit structure of a sub-power generation circuit provided by an embodiment of the present disclosure;

[0029] Figure 3 This is a schematic diagram of a specific circuit structure of a sub-power generation circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0032] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0033] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0034] In view of the problems existing in the prior art, the present disclosure provides a sub-power generation circuit. Figure 1 is a structural diagram of a sub-power generation circuit provided by an embodiment of the present disclosure, Figure 2 This is a schematic diagram of a specific circuit structure of a sub-power generation circuit provided by an embodiment of the present disclosure, combined with Figure 1 and Figure 2The sub-power supply generation circuit includes a startup current generation module 10, a target current generation module 20, and a sub-power supply voltage generation module 30. The target current generation module 20 includes a first transistor M1, a second transistor M2, and a first resistor R1. The width-to-length ratio of the first transistor M1 is smaller than the width-to-length ratio of the second transistor M2. The sub-power supply voltage generation module 30 includes at least a third transistor M3, a fourth transistor M4, and a second resistor R2. The startup current generation module 10 is configured to generate a startup current. The target current generation module 20 is configured to determine, after receiving the startup current, the on-state current of the first branch L1 according to the gate-source voltage of the first transistor M1, the gate-source voltage of the second transistor M2, and the first resistor R1, and determine the upper node current I mirrored to the second branch according to the on-state current and the first mirror relationship between the first branch L1 and the second branch L2. up , according to the conduction current and the second mirror relationship between the first branch L1 and the second branch L2, determine the lower node current I mirrored to the second branch down , and according to the lower node current I down and the upper node current I up Determine the target current I out , the conduction current is positively correlated with the temperature coefficient, and the lower node current is greater than the upper node current; the sub-power supply voltage generation module 30 is configured to generate a voltage according to the target current I out , the gate-source voltage of the third transistor M3, the gate-source voltage of the fourth transistor M4 and the second resistor R2, determine the sub-power supply voltage V sub_reg , the gate-source voltage of the third transistor M3 and the gate-source voltage of the fourth transistor M4 are negatively correlated with the temperature coefficient.

[0035] Specifically, the starting current generating module 10 generates a starting current and mirrors the generated starting current to the target current generating module 20 .

[0036] Specifically, after the target current generating module 20 receives the startup current, the first transistor M1 receives the startup current and is turned on. Since the first transistor M1 and the second transistor M2 have different aspect ratios, and the aspect ratio of the first transistor M1 is smaller than the aspect ratio of the second transistor M2, the gate-source voltage of the first transistor M1 is greater than the gate-source voltage of the second transistor M2. At this time, the current flowing through the first resistor R1, i.e., the on-state current, satisfies: After determining the on-current, the upper node current of the second branch mirrored by the on-current can be determined based on the on-current and the first mirror relationship between the first branch L1 and the second branch L2. The lower node current of the second branch mirrored by the on-current can be determined based on the on-current and the second mirror relationship between the first branch and the second branch. Then, the target current is determined based on the upper node current and the lower node current of the second branch. For example, if the first mirror relationship between the first branch and the second branch is 1:1 and the second mirror relationship between the first branch and the second branch is 1:2, then the upper node current of the second branch mirrored by the on-current satisfies: I up =I in , the conduction current mirrored to the lower node current of the second branch satisfies: I down =2I in , and then according to the flow direction of the upper node current and the lower node current, determine the target current to meet: I out =I down -I up .

[0037] The sub-power supply voltage module 30 receives the target current and mirrors the target current to the third transistor M3 and the fourth transistor M4 of the sub-power supply voltage branch Lsub through a mirror relationship. At this time, the sub-power supply voltage output by the sub-power supply voltage node satisfies: Wherein, K is determined based on the first mirror relationship, the second mirror relationship, and the mirror relationship of mirroring the target current to the sub-power supply voltage branch. Since ΔVgs is positively correlated with the temperature coefficient, and the gate-source voltage of the third transistor M3 and the fourth transistor M4 is negatively correlated with the temperature coefficient, V gs It is negatively correlated with the temperature coefficient, and the generated sub-power supply voltage is similar to the bandgap voltage (Δvbe*A+vbe). Therefore, the sub-power supply voltage has the advantage of changing less with PVT (process, voltage and temperature). In addition, no bipolar devices are used in the sub-power supply generation circuit disclosed in this application, which greatly reduces the circuit area.

[0038] The embodiment of the present disclosure provides a sub-power supply generation circuit, a startup current generation module, which generates a startup current; a target current generation module, which determines the on-current of the first branch according to the gate-source voltage of the first transistor, the gate-source voltage of the second transistor and the first resistor after receiving the startup current, and determines the upper node current mirrored to the second branch according to the on-current and the first mirror relationship between the first branch and the second branch, determines the lower node current mirrored to the second branch according to the on-current and the second mirror relationship between the first branch and the second branch, and determines the target current according to the lower node current and the upper node current, the on-current is positively correlated with the temperature coefficient, and the lower node current is greater than the upper node current; the sub-power supply voltage generation module determines the sub-power supply voltage according to the target current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor and the second resistor, and the gate-source voltage of the third transistor and the fourth transistor is negatively correlated with the temperature coefficient. A current that is positively correlated with the temperature coefficient is generated in the sub-power supply voltage branch through the target current generation module. Combined with the characteristics of the gate-source voltage of the third transistor and the fourth transistor in the sub-power supply voltage branch (negatively correlated with the temperature coefficient), when the mirror relationship between the branches is configured, the sub-power supply voltage generated at the sub-power supply voltage node is independent of the preparation process, voltage and temperature of the transistor, and the generated sub-power supply voltage varies little with PVT (process, voltage and temperature).

[0039] In a specific embodiment, Figure 2 FIG. 1 is a schematic diagram of a specific circuit structure of a startup current generating module provided by an embodiment of the present disclosure, such as Figure 2 As shown, the starting current generating module 10 includes an initial current generating unit 11 and a first mirror unit 12; the initial current generating unit 11 is configured to generate an initial current; the first mirror unit 12 is configured to mirror the initial current to the third branch L3 to obtain a starting current.

[0040] In which, the initial current generating unit 11 includes a fifth transistor M5 and a third resistor R3, the first mirroring unit 12 includes a sixth transistor M6 and a seventh transistor M7, the first end of the third resistor R3 and the control end of the fifth transistor M5 are respectively electrically connected to the common ground node, the second end of the third resistor R3 is electrically connected to the source end of the fifth transistor M5, the drain end of the fifth transistor M5 is respectively electrically connected to the drain end of the sixth transistor M6, the control end of the sixth transistor M6, and the control end of the seventh transistor M7, the source end of the sixth transistor M6 and the source end of the seventh transistor M7 are respectively electrically connected to the power supply voltage node, and the drain end of the seventh transistor M7 outputs the startup current to the target current generating module.

[0041] Specifically, the fifth transistor M5 is a high-voltage depletion-type transistor, the threshold voltage of the fifth transistor M5 is negative, and the source-drain and drain-gate can withstand high voltage, and a startup current is generated through the fifth transistor M5 and the third resistor R3: By setting the fifth transistor M5 as a depletion-type transistor, there is no need to set up an additional startup circuit. The initial current can be generated through the fifth transistor M5 and the third resistor R3, thereby further reducing the area of ​​the circuit.

[0042] It should be noted that the startup current is related to the resistance of the third resistor R3 and the size of the fifth transistor M5.

[0043] After the fifth transistor M5 and the third resistor R3 generate an initial current, the sixth transistor M6 and the seventh transistor M7 form a first mirror unit 12. The sixth transistor M6 mirrors the initial current to the seventh transistor M7 to obtain a startup current. The startup current serves as a startup condition for the target current generating module to generate a target current.

[0044] In a specific embodiment, see Figure 2 The target current generating module 20 further includes a second mirror unit 21 and a third mirror unit 22; the second mirror unit 21 is configured to determine the upper node current I mirrored to the second branch L2 according to the conduction current and the first mirror relationship between the first branch L1 and the second branch L2. up The third mirror unit 22 is configured to determine the second mirror relationship between the first branch L1 and the second branch L2 based on the third mirror relationship between the first branch L1 and the fourth branch L4 and the fourth mirror relationship between the fourth branch L4 and the second branch L2, and determine the lower node current I mirrored to the second branch L2 based on the conduction current and the second mirror relationship between the first branch L1 and the second branch L2. down .

[0045] The second mirror unit 21 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10, the third mirror unit 22 includes an eleventh transistor M11 and a twelfth transistor M12, the drain end of the first transistor M1 is electrically connected to the control end of the first transistor M1 and the control end of the second transistor M2, the source end of the second transistor M2 is electrically connected to the first end of the first resistor R1, the source ends of the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are electrically connected to the power supply voltage node, the control end of the eighth transistor M8, the eighth transistor M9, and the tenth transistor M10 are electrically connected to the power supply voltage node, and the control end of the eighth transistor M8 and the eighth transistor M10 are electrically connected to the power supply voltage node. A drain terminal of the first transistor M1, a control terminal of the ninth transistor M9, and a control terminal of the tenth transistor M10 are electrically connected to the drain terminal of the second transistor M2, respectively. The drain terminal of the ninth transistor M9 is electrically connected to the drain terminal of the eleventh transistor M11, the control terminal of the eleventh transistor M11, and the control terminal of the twelfth transistor M12, respectively. The drain terminal of the tenth transistor M10 is electrically connected to the drain terminal of the twelfth transistor M12. A source terminal of the first transistor M1, a second end of the first resistor R1, a source terminal of the eleventh transistor M11, and a source terminal of the twelfth transistor M12 are electrically connected to the common ground node, respectively.

[0046] Specifically, such as Figure 2 As shown, after the first mirror unit 12 mirrors the initial current to the third branch L3 where the first transistor M1 is located, the first transistor M1 is turned on, and the first transistor M1 and the second transistor M2 have the same gate voltage. By setting the width-to-length ratio of the first transistor M1 and the second transistor M2, the gate-source voltage of the first transistor M1 is greater than the gate-source voltage of the second transistor M2. When the gate-source voltages of the first transistor M1 and the second transistor M2 are different, the on-current flowing through the first resistor R1 satisfies: ΔV gs The voltage is positively correlated with the temperature coefficient, and the on-state current is positively correlated with the temperature coefficient.

[0047] The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 form a second mirror unit 21. The first mirror relationship of the second mirror unit 21 can be set to 1:K1:K1, that is, the first mirror ratio of the first branch L1 to the second branch L2 is K1, and the mirror ratio of the first branch L1 to the fourth branch L4 is K1. At this time, the upper node current of the second branch L2 satisfies: I up =K1*I in , the mirror current of the fourth branch L4 satisfies: I2=K1*I in .

[0048] The eleventh transistor M11 and the twelfth transistor M12 form a third mirror unit 22. The second mirror relationship of the third mirror unit 22 can be set to 1:K2, that is, the mirror ratio of the fourth branch L4 and the second branch L2 is K2. Therefore, according to the fourth mirror relationship between the fourth branch and the second branch L4 L2 and the third mirror relationship between the first branch L1 and the fourth branch L4, it can be determined that the second mirror relationship between the first branch L1 and the second branch L2 is 1:K2, that is, the second mirror ratio of the fourth branch L4 and the second branch L2 is K2. Therefore, the determined lower node current mirrored to the second branch satisfies: I down =K2*I in .

[0049] After determining the lower node current and the upper node current of the second branch, based on the current flow relationship, it can be determined that the target current flowing through the sub-power supply voltage generation module satisfies:

[0050] On the basis of the above embodiment, continue to refer to Figure 2The sub-power supply voltage generation module includes a fourth mirror unit 31 and a sub-power supply voltage determination unit 32; the fourth mirror unit 31 is configured to determine the mirror current mirrored to the sixth branch according to the target current and the fifth mirror relationship between the fifth branch and the sixth branch; the sub-power supply voltage determination unit 32 is configured to determine the sub-power supply current of the sub-power supply voltage branch according to the mirror current and the sixth mirror relationship between the sixth branch and the sub-power supply voltage branch, and determine the sub-power supply voltage according to the sub-power supply current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor and the second resistor.

[0051] The fourth mirroring unit 31 includes a thirteenth transistor M13 and a fourteenth transistor M14. The sub-power supply voltage determining unit 32 includes a fifteenth transistor M15, a third transistor M3, a fourth transistor M4, a second resistor R2, and a twenty-first transistor M21. The source terminal of the thirteenth transistor M13 and the source terminal of the fourteenth transistor M14 are electrically connected to the power supply voltage node, respectively. The control terminal of the thirteenth transistor M13, the control terminal of the fourteenth transistor M14, and the drain terminal of the fourteenth transistor M14 are electrically connected to the drain terminal of the fifteenth transistor M15, respectively. The drain terminal of the thirteenth transistor M13 receives a target current. The control terminal of the fifteenth transistor M15 is electrically connected to the control terminal of the third transistor M3, the drain terminal of the third transistor M3, and the source terminal of the fourth transistor M4, respectively. The control terminal and the drain terminal of the fourth transistor M4 are electrically connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 and the drain terminal of the twenty-first transistor M21 are electrically connected to the sub-power supply voltage node, respectively. The source terminal of the twenty-first transistor M21 is electrically connected to the power supply voltage node.

[0052] Combine Figure 2 The thirteenth transistor M13 and the fourteenth transistor M14 form a fourth mirror unit. The current flowing through the thirteenth transistor M13 is the target current. Through the mirroring effect of the thirteenth transistor M13 and the fourteenth transistor M14, the mirror current of the sixth branch L6 satisfies: I2=K4*I out , K4 is the mirror ratio of the fourth mirror unit, the fifteenth transistor M15 and the third transistor M3 form a mirror circuit, and the mirroring effect of the fifteenth transistor M15 and the third transistor M3 makes the sub-power supply current of the sub-power supply voltage branch meet the following conditions: I3=K5*K4*I out , K4 is the mirror ratio of the fourth mirror unit, K5 is the mirror ratio of the mirror circuit composed of the fifteenth transistor M15 and the third transistor M3, after determining the sub-power supply current of the sub-power supply voltage branch, the sub-power supply voltage of the sub-power supply voltage node satisfies: Among them, K=(K2-K1)*K4*K5, ΔV gs =V gsn1 -V gsn2.

[0053] Based on the above embodiments, Figure 3 As shown, the circuit further includes a circuit protection module 40, which is configured to withstand high voltage signals of each branch and protect transistors of each branch.

[0054] The circuit protection module includes a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, and a fourth resistor R4; the drain terminal of the sixteenth transistor M16 is electrically connected to the control terminal of the sixteenth transistor M16, the control terminal of the seventeenth transistor M17, the control terminal of the eighteenth transistor M18, and the control terminal of the nineteenth transistor M19, respectively; the source terminal of the sixteenth transistor M16 is electrically connected to the drain terminal of the first transistor M1, and the drain terminal of the seventeenth transistor M17 is electrically connected to the first terminal of the fourth resistor R4 and the drain terminal of the twentieth transistor M20, respectively. The control end is electrically connected, the second end of the fourth resistor R4 is electrically connected to the drain end of the eighth transistor M8, the source end of the twentieth transistor M20 is electrically connected to the drain end of the ninth transistor M9, the drain end of the twentieth transistor M20 is electrically connected to the drain end of the eleventh transistor M11, the drain end of the eighteenth transistor M18 is electrically connected to the drain end of the tenth transistor M10, the source end of the eighteenth transistor M18 is electrically connected to the drain end of the twelfth transistor M12, the drain end of the nineteenth transistor M19 is electrically connected to the drain end of the fourteenth transistor M14, and the source end of the nineteenth transistor M19 is electrically connected to the drain end of the fifteenth transistor M15.

[0055] In a specific embodiment, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, and the twenty-first transistor are high-voltage transistors, and the source-drain and gate-drain gaps between the transistors can withstand high voltage.

[0056] Specific, combined Figure 3After the first mirror unit mirrors the startup current to the third branch, the sixteenth transistor M16 is turned on by the startup current. If the voltage of the power supply voltage node is a high voltage (for example, 36V), assuming that the conduction voltage drop of any transistor is 1V, at this time, the voltages of the drain terminal and the control terminal of the sixteenth transistor M16 are both 2V. Since the control terminals of the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are respectively connected to the control terminal of the sixteenth transistor M16, the control terminals of the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all 2V. By setting the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 as high-voltage transistors, their source and drain can withstand high voltage. For example, when the power supply voltage node VDD=36V and the conduction voltage drop of the fourth resistor R4 is 1V, the gate voltage of the twentieth transistor M20 (the drain voltage of the seventeenth transistor M17) is VDD-|V gs8 |-I*R4=34V, the source voltage of the twentieth transistor M20 is VDD-|V gs8 |-IR4+|V gs20 |=35V, by setting the fourth resistor R4 and the twentieth transistor M20, the drain-source voltage of the ninth transistor M9 can be prevented from being too large, thereby protecting the ninth transistor M9. The source voltage of the seventeenth transistor M17 is V gs1 +V gs16 -V gs17 =1V, that is, the drain-source voltage of the seventeenth transistor M17 withstands the high voltage of 33V; the drain voltage of the eighteenth transistor M18 is VDD-|V gs21 |=35V, the source voltage of the eighteenth transistor M18 is V gs1 +V gs16 -V gs18 =1V, that is, the drain-source voltage of the eighteenth transistor M18 withstands the high voltage of 34V; the drain voltage of the nineteenth transistor M19 is VDD-|V gs14 |=35V, the source voltage of the nineteenth transistor M19 is V gs1 +V gs16 -V gs19=1V, that is, the drain-source voltage of the nineteenth transistor M19 withstands a high voltage of 34V. Therefore, the first branch L1 is subjected to the high voltage by the seventeenth transistor M17, which can prevent the second transistor M2 from being broken down due to an excessive voltage difference between the gate-drain and source-drain of the second transistor M2, thereby protecting the second transistor M2. The second branch L2 is subjected to the high voltage by the eighteenth transistor M18, which can prevent the twelfth transistor M12 from being broken down due to an excessive voltage difference between the gate-drain and source-drain of the twelfth transistor M12, thereby protecting the twelfth transistor M12. The sixth branch L6 is subjected to the high voltage by the nineteenth transistor M19, which can prevent the fifteenth transistor M15 from being broken down due to an excessive voltage difference between the gate-drain and source-drain of the fifteenth transistor M15, thereby protecting the fifteenth transistor M15. The fourth branch L4 is subjected to the high voltage by the twentieth transistor M20, which can prevent the ninth transistor M9 from being broken down due to an excessive voltage difference between the gate-drain and source-drain of the ninth transistor M9, thereby protecting the ninth transistor M9.

[0057] In addition, in the above embodiment, the high voltage of the third branch L3 is borne by the source and drain of the seventh transistor M7, the source voltage of the twenty-first transistor M21 is VDD, and the drain voltage is the sub-power supply voltage (which is a low voltage, below 3V). Therefore, the high voltage of the sub-power supply voltage branch is borne by the drain and source of the twenty-first transistor M21.

[0058] It should be noted that, in the above embodiment, when the circuit protection module is not set, it is necessary to set the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15 and the twenty-first transistor M21 as high-voltage transistors.

[0059] When the circuit protection module is set, the twenty-first transistor M21, the fourth transistor M4, the third transistor M3, the fifteenth transistor M15, the nineteenth transistor M19, the fourteenth transistor M14, and the thirteenth transistor M13 in the circuit protection module form a negative feedback loop to implement feedback regulation of the sub-power supply voltage output from the sub-power supply voltage output node, thereby reducing fluctuations in the sub-power supply voltage and ensuring the stability of the output sub-power supply voltage.

[0060] When the output sub-power supply voltage increases, the drain and gate voltages of the fourth transistor M4 increase, the source voltage of the fourth transistor M4 increases, the drain and gate voltages of the third transistor M3 increase, the gate voltage of the fifteenth transistor M15 increases, the drain voltage of the fifteenth transistor M15 decreases, the source voltage of the nineteenth transistor M19 decreases, the drain voltage of the nineteenth transistor M19 decreases, the drain and gate voltages of the fourteenth transistor M14 decrease, the gate voltage of the thirteenth transistor M13 decreases, the drain voltage of the thirteenth transistor M13 increases, the gate voltage of the twenty-first transistor M21 increases, and the drain voltage of the twenty-first transistor M21 decreases. Therefore, the output sub-power supply voltage decreases, thereby achieving negative feedback regulation of the sub-power supply voltage.

[0061] It should be further explained that the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the nineteenth transistor are NMOS transistors, and the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, the fourteenth transistor, the twentieth transistor, and the twenty-first transistor are PMOS transistors.

[0062] On the basis of the above embodiments, the embodiments of the present disclosure further provide a chip, including the circuit described in any one of the above embodiments, and having the beneficial effects described in any one of the above embodiments. The embodiments of the present disclosure do not provide examples one by one for this.

[0063] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0064] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0065] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0066] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A sub-power generation circuit, characterized in that: include: a startup current generating module, a target current generating module, and a sub-power supply voltage generating module, wherein the target current generating module includes at least a first transistor, a second transistor, and a first resistor, wherein the width-to-length ratio of the first transistor is smaller than the width-to-length ratio of the second transistor, and the sub-power supply voltage generating module includes at least a third transistor, a fourth transistor, and a second resistor; Wherein, the starting current generating module is configured to generate a starting current; The target current generating module is configured to, after receiving the startup current, determine the on-current of the first branch according to the gate-source voltage of the first transistor, the gate-source voltage of the second transistor, and the first resistor, determine an upper node current mirrored to the second branch according to the on-current and a first mirror relationship between the first branch and the second branch, determine a lower node current mirrored to the second branch according to the on-current and a second mirror relationship between the first branch and the second branch, and determine a target current according to the lower node current and the upper node current, wherein the on-current is positively correlated with the temperature coefficient, and the lower node current is greater than the upper node current; The sub-power supply voltage generation module is configured to determine the sub-power supply voltage based on the target current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor and the second resistor, and the gate-source voltage of the third transistor and the fourth transistor are negatively correlated with the temperature coefficient.

2. The circuit according to claim 1, wherein: The startup current generating module includes an initial current generating unit and a first mirror unit; The initial current generating unit is configured to generate an initial current; The first mirror unit is configured to mirror the initial current to the third branch to obtain a startup current.

3. The circuit according to claim 2, characterized in that The initial current generating unit includes a fifth transistor and a third resistor, and the initial current generating unit includes a sixth transistor and a seventh transistor. The first end of the third resistor and the control end of the fifth transistor are respectively electrically connected to a common ground node, the second end of the third resistor is electrically connected to the source end of the fifth transistor, the drain end of the fifth transistor is respectively electrically connected to the drain end of the sixth transistor, the control end of the sixth transistor and the control end of the seventh transistor, the source end of the sixth transistor and the source end of the seventh transistor are respectively electrically connected to the power supply voltage node, and the drain end of the seventh transistor outputs a startup current to the target current generating module.

4. The circuit according to claim 1, wherein: The target current generating module further includes a second mirror unit and a third mirror unit; The second mirror unit is configured to determine the upper node current mirrored to the second branch according to the conduction current and a first mirror relationship between the first branch and the second branch; The third mirror unit is configured to determine a second mirror relationship between the first branch and the second branch based on the third mirror relationship between the first branch and the fourth branch and the fourth mirror relationship between the fourth branch and the second branch, and determine a lower node current mirrored to the second branch based on the conduction current and the second mirror relationship between the first branch and the second branch.

5. The circuit according to claim 4, characterized in that The second mirror unit includes an eighth transistor, a ninth transistor, and a tenth transistor. The third mirror unit includes an eleventh transistor and a twelfth transistor. The drain terminal of the first transistor is electrically connected to the control terminal of the first transistor and the control terminal of the second transistor, respectively. The source terminal of the second transistor is electrically connected to the first end of the first resistor. The source terminals of the eighth transistor, the ninth transistor, and the tenth transistor are electrically connected to a power supply voltage node, respectively. The control terminal of the eighth transistor, the drain terminal of the eighth transistor, the control terminal of the ninth transistor, and the control terminal of the tenth transistor are electrically connected to the drain terminal of the second transistor, respectively. The drain terminal of the ninth transistor is electrically connected to the drain terminal of the eleventh transistor, the control terminal of the eleventh transistor, and the control terminal of the twelfth transistor, respectively. The drain terminal of the tenth transistor is electrically connected to the drain terminal of the twelfth transistor. The source terminal of the first transistor, the second end of the first resistor, the source terminal of the eleventh transistor, and the source terminal of the twelfth transistor are electrically connected to a common ground node, respectively.

6. The circuit according to claim 1, wherein: The sub-power supply voltage generating module includes a fourth mirror unit and a sub-power supply voltage determining unit; The fourth mirror unit is configured to determine a mirror current mirrored to the sixth branch according to the target current and a fifth mirror relationship between the fifth branch and the sixth branch; The sub-power supply voltage determination unit is configured to determine the sub-power supply current of the sub-power supply voltage branch based on the mirror current and a sixth mirror relationship between the sixth branch and the sub-power supply voltage branch, and to determine the sub-power supply voltage based on the sub-power supply current, the gate-source voltage of the third transistor, the gate-source voltage of the fourth transistor, and the second resistor.

7. The circuit according to claim 6, characterized in that The fourth mirror unit includes a thirteenth transistor and a fourteenth transistor. The sub-power supply voltage determination unit includes a fifteenth transistor, the third transistor, the fourth transistor, the second resistor, and a twenty-first transistor. The source terminal of the thirteenth transistor and the source terminal of the fourteenth transistor are respectively electrically connected to the power supply voltage node. The control terminal of the thirteenth transistor, the control terminal of the fourteenth transistor, and the drain terminal of the fourteenth transistor are respectively electrically connected to the drain terminal of the fifteenth transistor. The drain terminal of the thirteenth transistor receives a target current. The control terminal of the fifteenth transistor is respectively electrically connected to the control terminal of the third transistor, the drain terminal of the third transistor, and the source terminal of the fourth transistor. The control terminal of the fourth transistor and the drain terminal of the fourth transistor are electrically connected to the first terminal of the second resistor. The second terminal of the second resistor and the drain terminal of the twenty-first transistor are respectively electrically connected to the sub-power supply voltage node. The source terminal of the twenty-first transistor is electrically connected to the power supply voltage node.

8. The circuit according to claim 1, wherein: The circuit further includes a circuit protection module, which is configured to withstand high-voltage signals of each branch and protect transistors of each branch.

9. The circuit according to claim 8, characterized in that The circuit protection module includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a fourth resistor; the drain terminal of the sixteenth transistor is electrically connected to the control terminal of the sixteenth transistor, the control terminal of the seventeenth transistor, the control terminal of the eighteenth transistor and the control terminal of the nineteenth transistor, respectively, the source terminal of the sixteenth transistor is electrically connected to the drain terminal of the first transistor, the drain terminal of the seventeenth transistor is electrically connected to the first end of the fourth resistor and the control terminal of the twentieth transistor, respectively, the second end of the fourth resistor is electrically connected to the drain terminal of the eighth transistor, the source terminal of the twentieth transistor is electrically connected to the drain terminal of the ninth transistor, the drain terminal of the twentieth transistor is electrically connected to the drain terminal of the eleventh transistor, the drain terminal of the eighteenth transistor is electrically connected to the drain terminal of the tenth transistor, the source terminal of the eighteenth transistor is electrically connected to the drain terminal of the twelfth transistor, the drain terminal of the nineteenth transistor is electrically connected to the drain terminal of the fourteenth transistor, and the source terminal of the nineteenth transistor is electrically connected to the drain terminal of the fifteenth transistor.

10. A chip, characterized in that: The invention comprises the sub-power supply generating circuit according to any one of claims 1 to 9.

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