Method for cyclically generating high-rate waveform signal and signal generator

Abstract

The invention relates to a method and a system for cyclically generating a high-speed waveform signal. The method comprises the following steps of: cyclically splicing waveform data by a waveform circulation module; the control module transmits a variable related to the waveform length to the waveform circulation module; the data storage module stores waveform data information; the waveform circulation module comprises an address circulation module which is responsible for data addressing and outputting a data address to a data storage module; the data circulation module receives the waveform data sent by the data storage module, completes circulation splicing of the data and sends the data to the data transmission interface, and the data transmission interface sends the waveform circulation data to the DAC. The waveform data length can be effectively reduced, and the requirement for the storage space is lowered; the method is suitable for any high-speed DAC (Digital-to-Analog Converter) using a JESD204 protocol interface, and can run most FPGA models of Xilinx JESD204 IP; the device can be adapted to an FPGA on-chip storage resource BRAM, and can also be adapted to an off-chip storage resource DDR and other devices; waveform circulation can be achieved according to needs, waveform infinite circulation can be completed, and circulation of specific times can also be completed.

Description

Technical Field

[0001] The present invention relates to the technical field of signal generators, and in particular to a method for cyclically generating a high-rate waveform signal and a signal generator. Background Art

[0002] A signal generator is a device that can provide electrical signals of various frequencies, waveforms, and output levels, such as an arbitrary waveform generator (AWG) or a vector signal generator (VSG). It is used as a test signal source or excitation source when measuring the amplitude characteristics, frequency characteristics, transmission characteristics, and other electrical parameters of various telecommunication systems or equipment, as well as when measuring the characteristics and parameters of components.

[0003] Signal generators include digital to analog converter chips (DAC) and field programmable gate array chips (FPGA). FPGA chips realize signal generation and control. DAC chips are common electronic devices in the RF field. They are used to convert digital signals generated by FPGA chips into analog signals. As key components of signal generators, they are widely used in communications, radar, test and measurement, and other fields. At present, the data interface of most high-speed DAC chips adopts the JESD204 protocol. When a high-speed DAC chip sends a specific waveform, the FPGA chip needs to use the JESD204 protocol to send waveform data to the DAC chip to achieve the purpose of waveform playback.

[0004] In Xilinx FPGA, JESD204 IP transmits a packet of sample frame data to the DAC chip in each clock cycle. Each packet of sample frame data has a variety of bit widths such as 256bit, 512bit or 1024bit according to the actual situation. Taking DAC with 8-bit sampling accuracy as an example, a packet of sample frame needs to transmit 32, 64 or 128 sample points. When the DAC chip waveform loops a certain waveform, the number of waveform sampling points needs to meet two conditions: Condition (1): The number of waveform sampling points needs to be one complete cycle or multiple complete cycles; Condition (2): The number of waveform sampling points must be an integer multiple of the number of sampling points in the sampling frame.

[0005] When the waveform sampling points are small, conditions (1) and (2) are relatively easy to meet; however, when the waveform sampling points are large, especially with the current mainstream method of directly repeating the waveform data periodically, that is, repeating the transmitted waveform periodically according to the number of sampling points of the sampling frame, the final length of the transmitted waveform will reach a very large value. Take the DAC chip with 8-bit sampling accuracy and 512-bit sampling frame as an example. Assuming that the transmitted waveform is a prbs7 signal, a single cycle of the prbs7 signal has 127 sampling points. After the cycle is repeated, the waveform length needs to be multiplied by 64, becoming 8128 sampling points. It can be seen that although the cycle repetition method is simple in concept, it will generate several times of storage redundancy, resulting in insufficient hardware storage space, data overwriting or loss, incomplete wave cycle data transmission, unstable analog signal output of the DAC chip, waveform distortion, etc., which seriously affects the performance indicators of the test and measurement system. Summary of the invention

[0006] The present invention provides a method for cyclically generating a high-rate waveform signal, which is used for a signal generator to cyclically generate a high-rate waveform signal. The signal generator includes an FPGA chip, a data storage module and a DAC chip. The FPGA chip includes a control module, a waveform circulation module and a data transmission interface. The waveform circulation module includes an address circulation module and a data circulation module. The method includes the following steps: The control module sends variables related to the waveform data length to the address circulation module and the data circulation module respectively; The address circulation module sends the data address of the sampling frame length to the data storage module according to the variable related to the waveform data length; The data storage module is pre-stored with waveform data, the waveform data includes a plurality of sampling frame waveform data, wherein the sampling frame waveform data includes residual frame data and N complete frame data, the complete frame data includes A sampling points, the number of sampling points of the residual frame data is M, the data storage module searches for the corresponding sampling frame waveform data according to the received data address and sends the sampling frame waveform data to the data circulation module; The data circulation module determines whether the received sampling frame waveform data is complete frame data or residual frame data according to the first preset rule. If it is complete frame data, the complete frame data is sent to the DAC chip through the data transmission interface, and so on, until N complete frame data in the first sampling frame waveform data are sent out, and the number of cycles i=i+1; If it is residual frame data, update the residual frame data to the original residual frame data, compare the number of sampling points in the residual frame data with the number of sampling points in the complete frame data, if the number of sampling points in the residual frame data is less than the number of sampling points in the complete frame data, then splice the sampling points in the residual frame data with part of the sampling points in the next sampling frame waveform data into complete frame data and send it to the DAC chip through the data transmission interface, and store another part of the sampling points in the next sampling frame data for splicing with the next waveform data, and so on, until the sending of N complete frame data is completed, update the residual frame to the last 2*M sampling points of the Nth sampling frame waveform data spliced ​​with the sampling points of the original residual frame data, and record the number of cycles as i=i+1; This cycle is repeated for P times to complete the sending of waveform data, wherein the length of the last residual frame data is exactly the length of a completed frame data, and P is equal to the least common multiple of M and A.

[0007] In some implementations, if the number of sampling points in the residual frame data is greater than the number of sampling points in the complete frame data, the first A sampling points of the residual frame data are sent out, and the remaining sampling points of the current residual frame data are retained as new residual frame data; If the number of sampling points in the residual frame data is equal to the number of sampling points in the complete frame data, the current residual frame data is sent out.

[0008] In some implementations, the first preset rule includes determining whether the number of sampling points of the received sampling frame waveform data is equal to the number of sampling points transmitted by the data transmission interface in each clock cycle; if they are equal, it is complete frame data; otherwise, it is residual frame data.

[0009] In some embodiments, the control module sends a loop enable instruction to the address loop module; The address cycle module waits for the cycle enable instruction, and if the cycle enable instruction is received, the address cycle module outputs an address valid mark and a residual frame data address to the data storage module; If not, judging whether the loop starts according to the second preset rule, if the loop starts, the address loop module outputs an address valid mark and outputs the first complete frame data address to the data storage module, and continues to wait for the loop enable instruction; If not, determine whether the loop is valid according to the third preset rule; if the loop is valid, calculate the address loop count, calculate the complement length, and calculate the number of loops; if not, the address loop module outputs the address invalid and the address is kept to the data storage module, and continues to wait for the loop enable instruction; Determine whether the residual frame data address needs to be output based on the complement length. If necessary, determine whether a loop is completed based on the address number. If the loop is completed, return to the first address and continue to wait for the loop enable instruction. If the loop is not completed, the output address is incremented, the residual frame data address is not output, and the loop enable instruction continues to be waited for.

[0010] In some implementations, the variables related to the waveform data length include the total waveform data length, the sampling frame waveform data length, the number of frames, and the residual frame data length.

[0011] In some embodiments, the second preset rule includes using the rising edge of the loop enable instruction to delay by one beat as a loop start judgment mark, if the mark is valid, the loop starts, and the loop start mark is set to 1; otherwise, the loop does not start, and the loop start mark remains; The third preset rule includes that when the loop start mark is set to 1 and the data transmission interface receive enable is valid, the loop is valid and the loop valid flag is set to 1; otherwise, the loop is invalid and the loop valid flag is set to 0.

[0012] In some embodiments, the calculating of the address cycle count includes: if the address cycle count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the address cycle count at the next moment = the current address cycle count - (the total length of the waveform data - the length of the sampling frame waveform data); otherwise, the address cycle count at the next moment = the current address cycle count + the length of the sampling frame waveform data; The calculation of the complement length includes: if the address cycle count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the complement length at the next moment = the current address cycle count - (the total length of the waveform data - the length of the sampling frame waveform data); otherwise, the complement length at the next moment = the current complement length; The calculation of the number of loops includes: if the address loop count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the next moment loop count = the current loop count + 1; otherwise, the next moment loop count = the current loop count.

[0013] In some implementations, if it is not necessary to output the address of the residual frame data, it is determined whether the cycle is completed based on whether the address number exceeds the frame number - 1.

[0014] In some implementations, the control module sends a sampling frame waveform data enable; The data circulation module determines whether the received sampling frame waveform data enable is valid, and if the sampling frame waveform data enable is valid, determines whether the received residual frame data enable is valid; If the received residual frame data is enabled and valid, the residual frame data is pre-stored; if it is invalid, the data cycle sequence number, the data cycle length count, the complement length and the number of cycles are calculated; According to the current complement length, enter different data processing branches to determine whether the loop is completed. If the loop is not completed, determine whether the current loop needs to output residual frame data. If necessary, determine whether the current data sequence number is equal to the number of frames. If not, output data valid enable, output the complete frame data length part in the residual frame data, update the residual frame data, and continue the data loop module to determine whether the received sampling frame waveform data enable is valid.

[0015] The present invention also provides a signal generator for cyclically generating a high-rate waveform signal, comprising an FPGA chip, a data storage module and a DAC chip, wherein the FPGA chip comprises a control module, a waveform circulation module and a data transmission interface, the waveform circulation module comprises an address circulation module and a data circulation module, and the signal generator is used to cyclically generate a high-rate waveform signal using the method described in any one of claims 1 to 9.

[0016] Beneficial effects of the present invention: The method for cyclically generating high-rate waveform signals provided by the present invention comprises an address module sending a data address, a data storage module performing addressing and then sending corresponding sampling frame waveform data, and a data circulation module combining information of the address circulation, circulation enabling information sent by a control module, etc. to splice residual frame data, thereby achieving complete sending of waveform data to a DAC chip within a limited number of cycles, effectively reducing the length of waveform circulation data, reducing the requirement for storage space in the data storage module, avoiding incomplete transmission of waveform circulation data due to insufficient storage space, unstable analog signal output of a DAC chip, waveform distortion, etc., and effectively improving the performance of a signal generator and a test and measurement system; the present invention can be adapted to FPGA on-chip storage resources BRAM, and can also be adapted to off-chip storage resources DDR and other devices; waveform circulation can be achieved as required, and both infinite waveform circulation and a specific number of circulations can be completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The specific implementation of the present invention will be further explained below in conjunction with the accompanying drawings.

[0018] Figure 1 A step diagram of a method for cyclically generating a high-rate waveform signal provided in an embodiment of the present application; Figure 2 A principle block diagram of a signal generator provided in one embodiment of the present application; Figure 3 A functional block diagram of a signal generator provided in another embodiment of the present application; Figure 4 A schematic diagram of a process of waveform cyclic splicing provided in an embodiment of the present application; Figure 5 A flowchart of a method for address cycling provided in one embodiment of the present application; Figure 6 A flow chart of a method for data circulation provided in one embodiment of the present application. DETAILED DESCRIPTION

[0019] A signal generator is an electronic instrument that can generate multiple waveforms, with adjustable frequency, amplitude and phase. It is used to provide stable waveform signals during testing and measurement. It includes: a circuit board with an FPGA chip and a DAC chip integrated on the circuit board. The FPGA chip is used to generate and control signals. The DAC chip is used to convert the digital signals generated by the FPGA control into analog signals.

[0020] In a signal generator, within a waveform cycle, a longer sampling frame (i.e., longer sampling time or more sampling points) means more points for sampling the signal, thus being able to capture signal details more finely. In DAC signal processing, an increase in the number of sampling points can improve the fidelity of signal reconstruction, making the reconstructed signal closer to the original signal. However, a longer sampling frame places higher requirements on the system's storage space. Example 1

[0021] When generating high-speed waveform signals, insufficient hardware storage space (such as DDR) often causes data overwriting or loss, resulting in incomplete waveform signal data transmission, which in turn causes the DAC chip 200 to experience unstable analog signal output and waveform distortion.

[0022] Figure 1 A diagram of the steps of a method for cyclically generating a high-rate waveform signal provided in one embodiment of the present application.

[0023] like Figure 1 As shown, this embodiment provides a method for cyclically generating a high-rate waveform signal, which is used by a signal generator to cyclically generate a high-rate waveform signal.

[0024] Figure 2 This is a principle block diagram of a signal generator provided in one embodiment of the present application. Figure 4 A schematic diagram of waveform data.

[0025] like Figure 2 As shown, the signal generator includes an FPGA chip 100, a data storage module 130 and a DAC chip 200, the FPGA chip 100 includes a control module 110, a waveform circulation module 120 and a data transmission interface 140, the waveform circulation module 120 includes an address circulation module 121 and a data circulation module 122, and the waveform circulation module 120 includes an address circulation module 121 and a data circulation module 122. Figure 1As shown, the method for cyclically generating a high-rate waveform signal comprises the following steps: Step S1, the control module 110 sends variables related to the waveform data length to the address circulation module 121 and the data circulation module 122 respectively; Step S2, the address circulation module 121 sends the data address of the sampling frame length to the data storage module 130 according to the variable related to the waveform data length; Step S3, please combine Figure 4 The data storage module 130 is pre-stored with waveform data, the waveform data includes a plurality of sampling frame waveform data, wherein the sampling frame waveform data includes residual frame data and N complete frame data, the complete frame data includes A sampling points, and the number of sampling points of the residual frame data is M. The data storage module 130 searches for the corresponding sampling frame waveform data according to the received data address and sends the sampling frame waveform data to the data circulation module 122; Step S4, the data circulation module 122 determines whether the received sampling frame waveform data is complete frame data or residual frame data according to the first preset rule. If it is complete frame data, the complete frame data is sent to the DAC chip 200 through the data transmission interface 140, and so on, until the N complete frame data in the first sampling frame are sent out, and the number of cycles i=i+1, the initial value of i is 0; Step S5, if it is residual frame data, update the residual frame data to the original residual frame data, compare the number of sampling points in the residual frame data with the number of sampling points in the complete frame data, if the number of sampling points in the residual frame data is less than the number of sampling points in the complete frame data, then splice the sampling points in the residual frame data with part of the sampling points in the next sampling frame waveform data into complete frame data and send it to the DAC chip 200 through the data transmission interface 140, and store another part of the sampling points in the next sampling frame data for splicing with the next waveform data, and so on, until the sending of N complete frame data is completed, and the residual frame is updated to be the last 2*M sampling points of the Nth sampling frame waveform data spliced ​​with the sampling points of the original residual frame data, and the number of cycles is recorded as i=i+1; Step S6, repeating the cycle in this way, completing the sending of waveform data for P cycles, wherein the length of the last residual frame data is exactly the length of a complete frame data, and P is equal to the least common multiple of M and A.

[0026] Specifically, in this embodiment, the first preset rule includes determining whether the number of sampling points of the received sampling frame waveform data is equal to the number of sampling points transmitted in each clock cycle of the data transmission interface 140. If they are equal, it is complete frame data; otherwise, it is residual frame data. The number of sampling points that can be transmitted in each clock cycle of the data transmission interface 140 is determined by the sampling accuracy of the DAC and the bit width of the data transmission interface. Taking the DAC with 8-bit sampling accuracy and the data transmission interface 140 with 512-bit bit width as an example, the number of sampling points that can be transmitted in each clock cycle is 64.

[0027] Figure 3 A principle block diagram of a signal generator provided in yet another embodiment of the present application.

[0028] In the embodiment of the present invention, the data storage module 130 may be a BRAM storage area (eg, Figure 2 As shown), it can also be a storage unit outside the FPGA chip 100 (such as Figure 3 As shown), for example, a DDR chip. The method for cyclically generating a high-rate waveform signal provided by an embodiment of the present invention can save storage space. As needed, it can be independent of the DDR chip and only use the storage area inside the FPGA.

[0029] The above description is based on 8-bit sampling accuracy and 64 sampling points as the main body, but the present invention is also applicable to other sampling accuracy and other sampling frame lengths. In addition, the waveform data length can be specially specified to reduce the difficulty of FPGA implementation without greatly increasing the waveform data length.

[0030] The method for cyclically generating a high-rate waveform signal provided by an embodiment of the present invention comprises an address module sending a data address, a data storage module 130 performing addressing and then sending the corresponding sampling frame waveform data, and a data circulation module 122 splicing the residual frame data in combination with the information of the address circulation and the circulation enable information sent by the control module 110, so as to achieve complete sending of the waveform data to the DAC chip 200 within a limited number of cycles, effectively reducing the waveform circulation data length, reducing the requirements for the storage space in the data storage module 130, avoiding incomplete transmission of wave circulation data due to insufficient storage space, unstable analog signal output of the DAC chip 200, waveform distortion, etc., and effectively improving the performance of the signal generator and the test and measurement system; the present invention can be adapted to the on-chip storage resource BRAM of FPGA, and can also adapt to the off-chip storage resource DDR and other devices; the waveform circulation can be realized as needed, and both infinite waveform circulation and a specific number of circulations can be completed.

[0031] Furthermore, the method further comprises: Step S51, if the number of sampling points in the residual frame data is greater than the number of sampling points in the complete frame data, the first A sampling points of the residual frame data are sent out, and the remaining sampling points of the current residual frame data are retained as new residual frame data; Step S52: If the number of sampling points in the residual frame data is equal to the number of sampling points in the complete frame data, the current residual frame data is sent out.

[0032] During the loop process, sometimes the number of sampling points in the residual frame data is greater than the number of sampling points in the complete frame data. This method can effectively solve this situation, sending the first A sampling points of the residual frame data as a complete frame data, and retaining the remaining sampling points of the current residual frame data as new residual frame data. The same is true for the case when the number is equal. It is flexible and convenient, and can effectively deal with a variety of situations, making the waveform data transmission accurate and stable.

[0033] In this embodiment, variables related to waveform data length include total waveform data length, sampling frame waveform data length, number of frames and residual frame data length, which facilitates the address cycle module 121 to perform address cycles and the data cycle module 122 to splice waveforms.

[0034] In this embodiment, the data transmission interface 140 uses the JESD204 protocol to send waveform data to the DAC chip 200 .

[0035] The present invention is based on the situation that when the logic device uses FPGA, data is transmitted to the high-speed DAC through JESD204 IP, and an implementation method for high-speed waveform signal cyclic generation is proposed. For DAC and FPGA using the JESD204 protocol, the requirements for device storage depth can be effectively reduced, and the waveform cyclic output of complex waveforms can be completed under limited storage depth. Example 2

[0036] Figure 5 A flowchart of a method for cyclically generating a high-rate waveform signal provided in yet another embodiment of the present application.

[0037] like Figure 5 As shown, this embodiment provides a method for cyclically generating a high-rate waveform signal, further comprising: Step S10, the control module 110 sends a loop enable instruction to the address loop module 121; Step S11, the address cycle module 121 waits for a cycle enable instruction. If the cycle enable instruction is received, the address cycle module 121 outputs an address valid flag and a residual frame data address to the data storage module 130; Step S12, if not, determine whether the loop starts according to the second preset rule; if the loop starts, the address loop module 121 outputs an address valid mark and outputs the first complete frame data address to the data storage module 130, and continues to wait for the loop enable instruction; Step S13, if not, determine whether the loop is valid according to the third preset rule, if the loop is valid, calculate the address loop count, calculate the complement length, and calculate the number of loops; if not, the address loop module 121 outputs the address invalid and the address is kept to the data storage module 130, and continues to wait for the loop enable instruction; Step S14, judging whether it is necessary to output the residual frame data address according to the complement length, if necessary, judging whether a cycle is completed according to the address number, if the cycle is completed, returning to the first address and continuing to wait for the cycle enable instruction; Step S15: If the loop is not completed, the output address is incremented automatically, the address of the remaining frame data is not output, and the loop enable instruction is continued to be waited.

[0038] The method for cyclically generating a high-rate waveform signal provided in this embodiment can output a residual frame address so that the data storage module 130 can search for a waveform according to the residual frame data address, and receive the loop enable instruction of the control module 110 through the address loop module 121, thereby realizing precise control over the generation of the waveform signal, ensuring that the generation of the waveform signal can be carried out according to a predetermined cycle, and improving the operating efficiency of the system; by outputting the address of the residual frame data, the data storage module 130 can accurately search for and process the residual frame data, avoiding the loss or repeated processing of the residual frame data, and improving the integrity and accuracy of the waveform data transmission.

[0039] Specifically, in this embodiment, the second preset rule includes delaying the rising edge of the loop enable instruction by one beat as a loop start judgment mark. If the mark is valid, the loop starts and the loop start mark is set to 1; otherwise, the loop does not start and the loop start mark is maintained.

[0040] Specifically, in this embodiment, the third preset rule includes that when the loop start mark is set to 1 and the data transmission interface 140 receiving enable is valid, the loop is valid and the loop valid flag is set to 1; otherwise, the loop is invalid and the loop valid flag is set to 0.

[0041] Specifically, in this embodiment, calculating the address cycle count includes: if the address cycle count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the address cycle count at the next moment = the current address cycle count - (the total length of the waveform data - the length of the sampling frame waveform data); otherwise, the address cycle count at the next moment = the current address cycle count + the length of the sampling frame waveform data; Calculating the complement length includes: if the address cycle count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the complement length at the next moment = the current address cycle count - (the total length of the waveform data - the length of the sampling frame waveform data); otherwise, the complement length at the next moment = the current complement length; Calculating the number of loops includes: if the address loop count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the next moment loop count = the current loop count + 1; otherwise, the next moment loop count = the current loop count.

[0042] In this embodiment, the method further includes: if it is not necessary to output the residual frame data address, determining whether the cycle is completed according to whether the address number exceeds the frame number - 1. Example 3

[0043] Figure 6 A flow chart of a method for data circulation provided in one embodiment of the present application.

[0044] like Figure 5 As shown, the method for cyclically generating a high-rate waveform signal provided in this embodiment further includes: Step S20, the control module 110 sends a sampling frame waveform data enable; Step S21, the data circulation module 122 determines whether the received sampling frame waveform data enable is valid, if the sampling frame waveform data enable is invalid, the sampling frame data is kept, and the residual frame data is kept; Step S22, if the sampling frame waveform data enable is valid, then determine whether the received residual frame data enable is valid, if the received residual frame data enable is valid, then pre-store the residual frame data, if not valid, then calculate the data cycle sequence number, calculate the data cycle length count, calculate the complement length and calculate the number of cycles; Step S23, according to the current complement length, enter different data processing branches to determine whether the loop is completed. If the loop is not completed, determine whether the current loop needs to output residual frame data; if not, output data valid enable, output the complete frame data length part in the residual frame data, update the residual frame data, and continue the data loop module 122 to determine whether the received sampling frame waveform data enable is valid.

[0045] Step S24, if necessary, determine whether the current data sequence number is equal to the frame number, if so, output data valid enable, output residual frame data, and update the residual frame data; Step S25, if not equal, then output data valid enable, output the complete frame data length part in the residual frame data, update the residual frame data, and continue the data circulation module 122 to determine whether the received sampling frame waveform data enable is valid.

[0046] The method for cyclically generating a high-rate waveform signal provided in this embodiment can improve the flexibility and efficiency of data processing by intelligently selecting pre-stored residual frame data or performing other data processing operations through the effectiveness of sampling frame waveform data enable and residual frame data enable; by calculating parameters such as data cycle sequence number, data cycle length count, complement length and number of cycles, precise control of the cycle process is achieved and storage resource utilization is optimized; when the cycle is not completed and residual frame data needs to be output, the method can accurately judge the relationship between the current data sequence number and the number of frames, thereby outputting the complete frame data length portion and updating the residual frame data, avoiding repeated processing or loss of waveform data and improving the integrity and accuracy of waveform data transmission. Example 4

[0047] This embodiment provides a signal generator for cyclically generating a high-rate waveform signal, comprising an FPGA chip 100, a data storage module 130 and a DAC chip 200. The FPGA chip 100 comprises a control module 110, a waveform circulation module 120 and a data transmission interface 140. The waveform circulation module 120 comprises an address circulation module 121 and a data circulation module 122. The signal generator is used to cyclically generate a high-rate waveform signal using the method steps described in any of the above embodiments.

[0048] The method for cyclically generating high-rate waveform signals provided by the present invention comprises an address module sending a data address, a data storage module 130 performing addressing and then sending corresponding sampling frame waveform data, and a data circulation module 122 splicing residual frame data in combination with information of the address circulation, circulation enable information sent by a control module 110, etc., so as to achieve complete sending of waveform data to a DAC chip 200 within a limited number of cycles, effectively reducing the length of waveform circulation data, reducing the requirement for storage space in the data storage module 130, avoiding incomplete transmission of waveform circulation data due to insufficient storage space, unstable analog signal output of the DAC chip 200, waveform distortion, etc., and effectively improving the performance of a signal generator and a test and measurement system; the present invention can be adapted to FPGA on-chip storage resources BRAM, and can also adapt to off-chip storage resources DDR and other devices; the waveform circulation can be realized as needed, and both infinite waveform circulation and a specific number of circulations can be completed.

[0049] Many specific details are described in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for cyclically generating a high-rate waveform signal, characterized in that: A signal generator is used to cyclically generate a high-speed waveform signal, the signal generator includes an FPGA chip, a data storage module and a DAC chip, the FPGA chip includes a control module, a waveform circulation module and a data transmission interface, the waveform circulation module includes an address circulation module and a data circulation module, and the method includes the following steps: The control module sends variables related to the waveform data length to the address circulation module and the data circulation module respectively; The address circulation module sends the data address of the sampling frame length to the data storage module according to the variable related to the waveform data length; The data storage module is pre-stored with waveform data, the waveform data includes a plurality of sampling frame waveform data, wherein the sampling frame waveform data includes residual frame data and N complete frame data, the complete frame data includes A sampling points, the number of sampling points of the residual frame data is M, the data storage module searches for the corresponding sampling frame waveform data according to the received data address and sends the sampling frame waveform data to the data circulation module; The data circulation module determines whether the received sampling frame waveform data is complete frame data or residual frame data according to the first preset rule. If it is complete frame data, the complete frame data is sent to the DAC chip through the data transmission interface, and so on, until N complete frame data in the first sampling frame waveform data are sent out, and the number of cycles i=i+1; If it is residual frame data, update the residual frame data to the original residual frame data, compare the number of sampling points in the residual frame data with the number of sampling points in the complete frame data, if the number of sampling points in the residual frame data is less than the number of sampling points in the complete frame data, then splice the sampling points in the residual frame data with part of the sampling points in the next sampling frame waveform data into complete frame data and send it to the DAC chip through the data transmission interface, and store another part of the sampling points in the next sampling frame waveform data for the next waveform data splicing, and so on, until the sending of N complete frame data is completed, update the residual frame to the last 2*M sampling points of the Nth sampling frame waveform data spliced ​​with the sampling points of the original residual frame data, and record the number of cycles as i=i+1; This cycle is repeated for P times to complete the sending of waveform data, wherein the length of the last residual frame data is exactly the length of a completed frame data, and P is equal to the least common multiple of M and A.

2. A method for cyclically generating a high-rate waveform signal according to claim 1, characterized in that: The method further comprises: If the number of sampling points in the residual frame data is greater than the number of sampling points in the complete frame data, the first A sampling points of the residual frame data are sent out, and the remaining sampling points of the current residual frame data are retained as new residual frame data; If the number of sampling points in the residual frame data is equal to the number of sampling points in the complete frame data, the current residual frame data is sent out.

3. The method for cyclically generating a high-rate waveform signal according to claim 1, characterized in that: The first preset rule includes determining whether the number of sampling points of the received sampling frame waveform data is equal to the number of sampling points transmitted by the data transmission interface in each clock cycle. If they are equal, it is complete frame data; otherwise, it is residual frame data.

4. The method for cyclically generating a high-rate waveform signal according to claim 1, characterized in that: Also includes: The control module sends a loop enable instruction to the address loop module; The address cycle module waits for the cycle enable instruction, and if the cycle enable instruction is received, the address cycle module outputs an address valid mark and a residual frame data address to the data storage module; If not, judging whether the loop starts according to the second preset rule, if the loop starts, the address loop module outputs an address valid mark and outputs the first complete frame data address to the data storage module, and continues to wait for the loop enable instruction; If not, determine whether the loop is valid according to the third preset rule; if the loop is valid, calculate the address loop count, calculate the complement length, and calculate the number of loops; if not, the address loop module outputs the address invalid and the address is kept to the data storage module, and continues to wait for the loop enable instruction; Determine whether the residual frame data address needs to be output based on the complement length. If necessary, determine whether a loop is completed based on the address number. If the loop is completed, return to the first address and continue to wait for the loop enable instruction. If the loop is not completed, the output address is incremented, the residual frame data address is not output, and the loop enable instruction continues to be waited for.

5. The method for cyclically generating a high-rate waveform signal according to claim 4, characterized in that: The variables related to the waveform data length include the total waveform data length, the sampling frame waveform data length, the number of frames and the residual frame data length.

6. The method for cyclically generating a high-rate waveform signal according to claim 4, characterized in that: The second preset rule includes using the rising edge of the loop enable instruction delayed by one beat as a loop start judgment mark, if the mark is valid, the loop starts, and the loop start mark is set to 1; Otherwise, the loop does not start and the loop start mark remains; The third preset rule includes that when the cycle start mark is set to 1 and the data transmission interface receiving enable is valid, the cycle is valid, and the cycle valid flag is set to 1; Otherwise, the loop is invalid and the loop valid flag is set to 0.

7. The method for cyclically generating a high-rate waveform signal according to claim 4, characterized in that: The calculation of the address cycle count includes: if the address cycle count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the address cycle count at the next moment = the current address cycle count - (the total length of the waveform data - the length of the sampling frame waveform data); otherwise, the address cycle count at the next moment = the current address cycle count + the length of the sampling frame waveform data; The calculation of the complement length includes: if the address cycle count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the complement length at the next moment = the current address cycle count - (the total length of the waveform data - the length of the sampling frame waveform data); otherwise, the complement length at the next moment = the current complement length; The calculation of the number of cycles includes: if the address cycle count is greater than or equal to (the total length of the waveform data - the length of the sampling frame waveform data), then the next moment cycle count = the current cycle count + 1; Otherwise, the next loop count = the current loop count.

8. The method for cyclically generating a high-rate waveform signal according to claim 4, characterized in that: If the address of the residual frame data does not need to be output, whether the cycle is completed is determined based on whether the address number exceeds the frame number - 1.

9. The method for cyclically generating a high-rate waveform signal according to claim 1, characterized in that: Also includes: The control module sends sampling frame waveform data enable; The data circulation module determines whether the received sampling frame waveform data enable is valid, and if the sampling frame waveform data enable is valid, determines whether the received residual frame data enable is valid; If the received residual frame data is enabled and valid, the residual frame data is pre-stored; if it is invalid, the data cycle sequence number, the data cycle length count, the complement length and the number of cycles are calculated; According to the current complement length, enter different data processing branches to determine whether the loop is completed. If the loop is not completed, determine whether the current loop needs to output residual frame data. If necessary, determine whether the current data sequence number is equal to the number of frames. If not, output data valid enable, output the complete frame data length part in the residual frame data, update the residual frame data, and continue the data loop module to determine whether the received sampling frame waveform data enable is valid.

10. A signal generator for cyclically generating a high-rate waveform signal, characterized in that: It comprises an FPGA chip, a data storage module and a DAC chip, wherein the FPGA chip comprises a control module, a waveform circulation module and a data transmission interface, the waveform circulation module comprises an address circulation module and a data circulation module, and the signal generator is used to cyclically generate a high-rate waveform signal using the method described in any one of claims 1 to 9.

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