A method, device, equipment and storage medium for fixed-point multiplication and product-accumulation operations

Abstract

The present invention discloses a method, device, equipment and storage medium for fixed-point number multiplication and multiplication-accumulation operations. The method comprises: obtaining at least two groups of arrays to be subjected to fixed-point number multiplication and multiplication-accumulation operations; determining the product results between N first fixed-point numbers and N second fixed-point numbers in at least two groups of arrays based on the multiplication instructions configured in the multiplier, and forming the product results into a third array; determining the accumulation results corresponding to the product results contained in the third array based on the accumulation instructions configured in the adder; wherein the multiplication instructions are single instruction multiple data stream SIMD instructions; and the accumulation instructions are very long instruction words VLIW instructions. In the embodiment of the present invention, the fixed-point number multiplication and multiplication-accumulation operations are performed by combining the multiplication instructions in the multiplier and the accumulation instructions configured in the adder, which can improve the overall calculation speed, eliminate the need for memory cache, and save space.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for fixed-point number multiplication and product-addition operations. Background Art

[0002] When performing fixed-point multiplication and multiplication-addition operations, existing solutions need to be performed serially in two steps, and the results of the serial execution need to be stored in temporary memory first, that is, memory space is needed to store the product results calculated by the multiplication between the two steps. After all executions are completed, the results of the serial execution are obtained from the temporary memory, and then the calculation is performed again, which reduces the overall calculation speed and causes low data calculation efficiency. Summary of the invention

[0003] In view of this, the present invention provides a method, apparatus, device and storage medium for fixed-point multiplication and product-addition operations, which can improve the overall calculation speed, eliminate the need for memory cache, and save space.

[0004] According to one aspect of the present invention, an embodiment of the present invention provides a method for fixed-point number multiplication and product-addition operations, the method comprising:

[0005] Obtain at least two groups of arrays to be subjected to fixed-point multiplication and product-addition operations; wherein the at least two groups of arrays include a first array and a second array; wherein the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers;

[0006] Determine the product results between the N first fixed-point numbers and the N second fixed-point numbers in the at least two arrays based on the multiplication instruction configured in the multiplier, and form the product results into a third array;

[0007] Determine the accumulation result corresponding to the product result included in the third array based on the accumulation instruction configured in the adder;

[0008] Wherein, the multiplication instruction is a single instruction multiple data (SIMD) instruction; and the accumulation instruction is a very long instruction word (VLIW) instruction.

[0009] According to another aspect of the present invention, an embodiment of the present invention further provides a device for fixed-point number multiplication and product-addition operations, the device comprising:

[0010] An array acquisition module, used to acquire at least two groups of arrays to be subjected to fixed-point multiplication and product-addition operations; wherein the at least two groups of arrays include a first array and a second array; wherein the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers;

[0011] A multiplier module, configured to determine the product results between the N first fixed-point numbers and the N second fixed-point numbers in the at least two arrays based on the multiplication instruction configured in the multiplier, and form the product results into a third array;

[0012] an adder module, configured to determine an accumulation result corresponding to the product result contained in the third array based on an accumulation instruction configured in the adder;

[0013] Wherein, the multiplication instruction is a single instruction multiple data (SIMD) instruction; and the accumulation instruction is a very long instruction word (VLIW) instruction.

[0014] According to another aspect of the present invention, an embodiment of the present invention further provides an electronic device, the electronic device comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method of fixed-point multiplication and product-addition operation described in any embodiment of the present invention.

[0018] According to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method of fixed-point multiplication and product-addition operations described in any embodiment of the present invention when executed.

[0019] According to another aspect of the present invention, an embodiment of the present invention further provides a computer program product, characterized in that the computer program product includes a computer program, and when the computer program is executed by a processor, it implements the method of fixed-point multiplication and multiplication and accumulation operations described in any embodiment of the present invention.

[0020] The technical effect of the present invention is that the product results between N first fixed-point numbers and N second fixed-point numbers in at least two groups of arrays are determined by multiplication instructions in a multiplier, and the product results are formed into a third array. Then, the accumulation results corresponding to the product results contained in the third array are determined according to the accumulation instructions configured in the adder, which can improve the overall calculation speed, eliminate the need for memory cache, and save space.

[0021] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A flowchart of a method for fixed-point multiplication and product-addition operation provided by an embodiment of the present invention;

[0024] Figure 2 A flowchart of another method for fixed-point multiplication and product-addition operation provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of the architecture of a method for fixed-point multiplication and product-addition operation provided by an embodiment of the present invention;

[0026] Figure 4 A structural block diagram of a device for fixed-point multiplication and product-addition operations provided by an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] In one embodiment, Figure 1 A flowchart of a method for fixed-point multiplication and multiplication-accumulation operations is provided for one embodiment of the present invention. This embodiment can be applicable to situations when fixed-point multiplication and multiplication-accumulation operations are performed. The method can be executed by a device for fixed-point multiplication and multiplication-accumulation operations. The device for fixed-point multiplication and multiplication-accumulation operations can be implemented in the form of hardware and / or software, and the device for fixed-point multiplication and multiplication-accumulation operations can be configured in an electronic device.

[0031] like Figure 1 As shown, the method for fixed-point multiplication and product-addition operation in this embodiment includes the following specific steps:

[0032] S110, obtaining at least two arrays to be subjected to fixed-point multiplication and product-addition operations.

[0033] Among them, at least two groups of arrays include a first array and a second array; wherein the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers.

[0034] The first fixed-point number is the fixed-point number included in the first array; the second fixed-point number is the fixed-point number included in the second array.

[0035] In the present embodiment, the multiple arrays to be subjected to fixed-point number multiplication and multiplication-accumulation operations include N fixed-point numbers respectively, and the data type of each fixed-point number can be a signed fixed-point number or an unsigned fixed-point number. Among them, a signed fixed-point number is a data bit specifically taken as a sign bit. Usually, 1 on the sign bit represents a negative number, 0 represents a positive number, and the remaining bits are numerical bits. For an unsigned fixed-point number, the value has no sign bit in all the binary bits of the word length in the machine, and all are numerical bits. In the present embodiment, the multiple arrays to be subjected to fixed-point number multiplication and multiplication-accumulation operations may include a first array and a second array, the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers.

[0036] S120. Determine the product results between the N first fixed-point numbers and the N second fixed-point numbers in at least two groups of arrays based on the multiplication instructions configured in the multiplier, and form the product results into a third array.

[0037] The multiplication instruction in this embodiment may be a Single Instruction Multiple Data (SIMD) instruction, and the multiplier includes at least two multiplication instructions.

[0038] In one embodiment, each multiplication instruction corresponds to a preset first clock cycle; the target number of multiplication instructions corresponds to a preset second clock cycle, wherein the preset first clock cycle is less than the preset second clock cycle; the target number of multiplication instructions is selected according to the demand. Exemplarily, the preset first clock cycle is one clock cycle, and the preset second clock cycle is four clock cycles, then each multiplication instruction can be represented as one clock cycle, and four multiplication instructions can be represented as four clock cycles. In the process of determining the product result between N first fixed-point numbers and N second fixed-point numbers in at least two groups of arrays according to the multiplication instruction, the first accumulation instruction in the accumulation instruction in the adder starts to execute after the preset second clock cycle of the multiplication instruction. It can be understood that after executing 4 multiplication instructions, the first accumulation instruction can be executed without all multiplication instructions being executed.

[0039] In this embodiment, the product results between the N first fixed-point numbers and the N second fixed-point numbers in at least two arrays can be determined by using a plurality of multiplication instructions configured in the multiplier, and the product results are formed into a third array, and the third array includes N product results. In some embodiments, when performing multiplication, the multiplication can be performed by shifting, that is, to identify the data types corresponding to the N first fixed-point numbers and the N second fixed-point numbers, respectively, and then use at least two multiplication instructions configured in the multiplier to perform bitwise multiplication of the N first fixed-point numbers and the N second fixed-point numbers to obtain the corresponding N product results; it can also be implemented by using multiplication accumulation and addition, that is, converting the two fixed-point numbers into integers and multiplying them to obtain the product, and then shifting the product right by the decimal place to obtain a new fixed-point number. This embodiment does not limit the specific method of multiplying fixed-point numbers.

[0040] S130. Determine the accumulation result corresponding to the product result contained in the third array based on the accumulation instruction configured in the adder.

[0041] The accumulated result is the result of accumulating the N product results in the third array.

[0042] In this embodiment, the accumulation instruction is a very long instruction word (VLIW) instruction, and the accumulation instruction includes at least two accumulation instructions; the first accumulation instruction in the accumulation instruction starts to execute after the first preset second clock cycle corresponding to the target number of multiplication instructions. It should be noted that the first accumulation instruction starts to execute after the first preset second clock cycle of the multiplication instruction, and the second accumulation instruction starts to execute after the second preset second clock cycle, until all the preset second clock cycles are executed.

[0043] In this embodiment, the accumulation instruction configured in the adder can be used to determine the result after the N product results contained in the third array are accumulated. In some embodiments, in each preset second clock cycle, for the N product results under each multiplication instruction, the VLIW very long instruction word configured in the adder is used to calculate the accumulation result corresponding to the N product results under each multiplication instruction. Specifically, for the N product results under each multiplication instruction, a first equal division is first performed to obtain the same number of third arrays and fourth arrays, and the same number of third arrays and fourth arrays are accumulated in a bitwise manner to obtain a first bitwise accumulation result. Then, for the first bitwise accumulation result, a second equal division is performed to obtain the same number of fifth arrays and sixth arrays, and the same number of fifth arrays and sixth arrays are accumulated in a bitwise manner to obtain a second bitwise accumulation result. Each time, the obtained bitwise accumulation result is divided equally and accumulated in a bitwise manner until the total accumulation result of the N product results is obtained, and the total accumulation result is used as the target result of accumulation.

[0044] The technical solution of the embodiment of the present invention determines the product results between N first fixed-point numbers and N second fixed-point numbers in at least two groups of arrays through multiplication instructions in a multiplier, and forms the product results into a third array. Then, the accumulation results corresponding to the product results contained in the third array are determined according to the accumulation instructions configured in the adder, which can improve the overall calculation speed, eliminate the need for memory cache, and save space.

[0045] In one embodiment, Figure 2 A flowchart of another method for fixed-point number multiplication and product accumulation operation provided for one embodiment of the present invention. Based on the above embodiments, this embodiment further refines the method of determining the product results between N first fixed-point numbers and N second fixed-point numbers in at least two groups of arrays based on the multiplication instructions configured in the multiplier, and forming the product results into a third array, and determining the accumulation results corresponding to the product results contained in the third array based on the accumulation instructions configured in the adder.

[0046] like Figure 2 As shown, the method for fixed-point multiplication and product-addition operation in this embodiment may specifically include the following steps:

[0047] S210, obtaining at least two groups of arrays to be subjected to fixed-point multiplication and product-addition operations; wherein the at least two groups of arrays include a first array and a second array; wherein the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers.

[0048] S220 , identifying data types corresponding to the N first fixed-point numbers and the N second fixed-point numbers, respectively.

[0049] In this embodiment, the data types corresponding to the N first fixed-point numbers and the N second fixed-point numbers are identified to obtain whether the data types corresponding to the N first fixed-point numbers and the N second fixed-point numbers are signed fixed-point numbers or unsigned fixed-point numbers.

[0050] S230. For N first fixed-point numbers and N second fixed-point numbers of the data type, use at least two multiplication instructions configured in the multiplier to perform bitwise multiplication of the N first fixed-point numbers and the N second fixed-point numbers according to a preset first clock cycle to obtain corresponding N product results.

[0051] In this embodiment, for N first fixed-point numbers and N second fixed-point numbers of the data type, at least two multiplication instructions configured in the multiplier are used to perform bitwise multiplication of the N first fixed-point numbers and the N second fixed-point numbers according to the preset first clock cycle to obtain the corresponding N product results. Specifically, it can be divided into two steps. The first step is to extract the sign bits of the multiplier and the multiplicand and perform an exclusive OR operation separately. The second step is to take the absolute values ​​of the numerical parts of the multiplier and the multiplicand and perform a shift addition operation. Exemplarily, the multiplication instruction can realize the multiplication of two arrays of N fixed-point numbers: A is the first array, expressed as A[0,1,2,3,…,(N-1)], and B is the second array, expressed as B[0,1,2,3,…,(N-1)], then after the bitwise multiplication, C[0,1,2,3,…,(N-1)] is obtained.

[0052] S240. In each preset second clock cycle, for each N product results under each multiplication instruction, use the VLIW very long instruction word configured in the adder to calculate the accumulated result corresponding to the N product results under each multiplication instruction.

[0053] In this embodiment, in each preset second clock cycle, for each multiplication instruction, the VLIW very long instruction word configured in the adder is used to calculate the accumulation result corresponding to the N product results under each multiplication instruction. Exemplarily, the VLIW (very long instruction word) accumulation instruction can accumulate the product results corresponding to each multiplication instruction to obtain Sum_C=C[0]+C[1]+C[2]+C[3]+…+C[N-1].

[0054] In this embodiment, for N first fixed-point numbers and N second fixed-point numbers of the data type, at least two multiplication instructions configured in the multiplier are used to perform bitwise multiplication of the N first fixed-point numbers and the N second fixed-point numbers according to a preset first clock cycle to obtain corresponding N product results. At the same time, in each preset second clock cycle, for the N product results under each multiplication instruction, the VLIW very long instruction word configured in the adder is used to calculate the cumulative result corresponding to the N product results under each multiplication instruction, thereby achieving the effect of performing multiplication and addition calculations in parallel, thereby further increasing the overall calculation speed.

[0055] In this embodiment, S240 may include: S2401-S2403.

[0056] S2401. In each preset second clock cycle, for each multiplication instruction, the N product results are first divided equally to obtain the third array and the fourth array of the same number, and the third array and the fourth array of the same number are aligningly accumulated to obtain a first aligning accumulation result.

[0057] In this embodiment, in each preset second clock cycle, for each multiplication instruction, the N product results are first divided equally to obtain the same number of third arrays and fourth arrays, and the same number of third arrays and fourth arrays are added bit by bit to obtain a first bit-by-bit accumulation result; wherein the number of the first bit-by-bit accumulation results is the same as the number in the third array and the fourth array.

[0058] S2402, performing a second equal division on the first alignment accumulation result to obtain a fifth array and a sixth array of the same number, and performing alignment accumulation on the fifth array and the sixth array of the same number to obtain a second alignment accumulation result.

[0059] In this embodiment, the first alignment accumulation result is divided into the fifth array and the sixth array of the same number for the second time, and the fifth array and the sixth array of the same number are aligned and accumulated to obtain the second alignment accumulation result. The number of the second alignment accumulation result is the same as the number in the fifth array and the sixth array.

[0060] S2403: Use the second positional accumulation result as the first positional accumulation result, and repeat the above-mentioned equal division and positional accumulation operation until the total accumulation result of N product results is obtained, and use the total accumulation result as the target result of accumulation.

[0061] In this embodiment, the second position-aligned accumulation result is used as the first position-aligned accumulation result, and the above-mentioned equal division and position-aligned accumulation operation is repeated until the total accumulation result of N product results is obtained, and the total accumulation result is used as the target result of accumulation. Among them, the number of the third array and the fourth array is greater than the number of the fifth array and the sixth array.

[0062] Exemplarily, when performing accumulation, for the multiplication results of N fixed-point numbers, taking N as 16 as an example, the C array includes 16 product results; the accumulation instruction first executes the first 8 product results + the last 8 fixed-point product results, and then obtains 8 fixed-point product results, and then these 8 fixed-point product results are divided into the first 4 and the last 4 for accumulation to obtain 4 fixed-point product results, and then these 4 fixed-point product results are divided into the first 2 and the last 2 for accumulation to obtain 2 fixed-point product results, and finally, these 2 fixed-point product results are accumulated again to obtain the final accumulation result.

[0063] In this embodiment, in order to better understand the execution of multiplication instructions in the multiplier, the execution of accumulation instructions in the adder, and the corresponding result output memory, Table 1 is a schematic diagram of the execution of multiplication instructions in the multiplier, the execution of accumulation instructions in the adder, and the corresponding result output memory provided in an embodiment of the present invention.

[0064] Table 1 is a schematic diagram of the execution of a multiplication instruction in a multiplier, the execution of an accumulation instruction in an adder, and the execution of the corresponding result output memory provided by an embodiment of the present invention.

[0065]

[0066] As can be seen from Table 1, from the 3rd row onwards, each row represents a computer clock cycle. Assuming that each multiplication instruction requires 4 clock cycles, the calculation result of the multiplication instruction 1 in the 3rd row is passed to the adder in the 7th row, and the adder executes the accumulation instruction 1, accumulates the N product results of the multiplication instruction 1 and temporarily stores them. At this time, the multiplier in the 7th row can continue to execute the multiplication instruction 5, that is, from the 7th row onwards, the multiplier and the adder are working in parallel at the same time. Assuming that the accumulation instruction requires 1 clock cycle to execute the accumulation and output the accumulation result, the final calculation result of 10 multiplication instructions and 10 accumulation instructions can be seen in the output memory in the 17th row.

[0067] The technical solution of the embodiment of the present invention obtains corresponding N product results by using at least two multiplication instructions configured in the multiplier to perform bitwise multiplication on the N first fixed-point numbers and the N second fixed-point numbers of the data type according to a preset first clock cycle. At the same time, in each preset second clock cycle, for the N product results under each multiplication instruction, the VLIW very long instruction word configured in the adder is used to calculate the cumulative result corresponding to the N product results under each multiplication instruction, thereby achieving the effect of performing multiplication and addition calculations in parallel, further increasing the overall calculation speed, and eliminating the need for memory cache during the accumulation process, saving space.

[0068] For example, to better understand the method of fixed-point multiplication and multiplication-addition operations, Figure 3 A schematic diagram of the architecture of a method for fixed-point multiplication and product-addition operation provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the architecture includes a multiplier and an adder, wherein the multiplication instructions included in the multiplier are single instruction multiple data (SIMD) instructions, and the addition instructions included in the adder are very long instruction words (VLIW) instructions. In this embodiment, the multiplier includes a plurality of multiplication instructions, and the plurality of multiplication instructions are used to calculate the multiplication of N fixed-point numbers in a plurality of arrays. Exemplarily, there are 4 arrays, respectively represented as array A, array B, array C, and array D, and each array includes N fixed-point numbers; multiplication instruction 1 is used to calculate the product between array A and array B, and multiplication instruction 2 is used to calculate the product between array C and array D. Similarly, the addition instructions in this embodiment are also a plurality of addition instructions, and the addition instructions are used to accumulate the product results of the above multiplication instructions.

[0069] In this embodiment, through the cooperation of hardware multipliers and adders, VLIW (very long instruction word) is used to accumulate products, so that multiplication and addition calculations are performed in parallel, which speeds up the overall calculation speed and saves memory space. It can be understood that the two single instruction multiple data stream instructions can be executed in parallel on the multiplier and adder respectively, without waiting for all multiplications to be completed before accumulation, thereby improving the overall calculation rate.

[0070] In one embodiment, Figure 4 The present invention provides a block diagram of a device for fixed-point multiplication and multiplication-accumulation operation according to an embodiment of the present invention. The device is applicable to the case of fixed-point multiplication and multiplication-accumulation operation. The device can be implemented by hardware / software. The device can be configured in an electronic device to implement a method for fixed-point multiplication and multiplication-accumulation operation according to an embodiment of the present invention.

[0071] like Figure 4 As shown, the device includes: an array acquisition module 410, a multiplier module 420 and an adder module 430;

[0072] The array acquisition module 410 is used to acquire at least two arrays to be subjected to fixed-point multiplication and product-addition operations; wherein the at least two arrays include a first array and a second array; wherein the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers;

[0073] A multiplier module 420, configured to determine the product results between the N first fixed-point numbers and the N second fixed-point numbers in the at least two arrays based on the multiplication instruction configured in the multiplier, and form the product results into a third array;

[0074] An adder module 430, configured to determine an accumulation result corresponding to the product results contained in the third array based on an accumulation instruction configured in the adder;

[0075] Wherein, the multiplication instruction is a single instruction multiple data (SIMD) instruction; and the accumulation instruction is a very long instruction word (VLIW) instruction.

[0076] In an embodiment of the present invention, a multiplier module determines the product results between N first fixed-point numbers and N second fixed-point numbers in at least two groups of arrays through a multiplication instruction in the multiplier, and forms a third array with the product results. Then, an adder module determines the accumulation results corresponding to the product results contained in the third array according to the accumulation instruction configured in the adder, so as to achieve the effect of performing multiplication calculation and addition calculation in parallel, improve the calculation speed, speed up the overall calculation speed, save memory space, and do not require memory cache, thereby saving space.

[0077] In one embodiment, the multiplication instructions include at least two multiplication instructions; each of the multiplication instructions corresponds to a preset first clock cycle; the target number of multiplication instructions corresponds to a preset second clock cycle, wherein the preset first clock cycle is smaller than the preset second clock cycle; the target number of multiplication instructions is selected according to demand.

[0078] In one embodiment, the multiplier module 420 includes:

[0079] A type identification unit, used to identify data types corresponding to the N first fixed-point numbers and the N second fixed-point numbers, respectively; wherein the data types include signed fixed-point numbers and unsigned fixed-point numbers;

[0080] The product result determination unit is used to use at least two multiplication instructions configured in the multiplier to perform bitwise multiplication of the N first fixed-point numbers and the N second fixed-point numbers of the data type according to a preset first clock cycle to obtain corresponding N product results.

[0081] In one embodiment, the accumulation instructions include at least two accumulation instructions; the first accumulation instruction among the accumulation instructions starts to be executed after the first preset second clock cycle corresponding to the target number of multiplication instructions.

[0082] In one embodiment, the adder module 430 includes:

[0083] The accumulation result determination unit is used to calculate the accumulation result corresponding to the N product results under each multiplication instruction in each preset clock cycle using the VLIW very long instruction word configured in the adder for the N product results under each multiplication instruction.

[0084] In one embodiment, the accumulation result determination unit includes:

[0085] A first result determination unit is used to perform a first equal division on the N product results under each multiplication instruction to obtain a third array and a fourth array of the same number, and perform bitwise accumulation on the third array and the fourth array of the same number to obtain a first bitwise accumulation result; wherein the number of the first bitwise accumulation result is the same as the number in the third array and the fourth array;

[0086] A second result determination unit is used to perform a second equal division on the first alignment accumulation result to obtain a fifth array and a sixth array of the same number, and perform alignment accumulation on the fifth array and the sixth array of the same number to obtain a second alignment accumulation result; wherein the number of the second alignment accumulation result is the same as the number in the fifth array and the sixth array;

[0087] a target result determination unit, configured to use the second aligned cumulative result as the first aligned cumulative result, and repeat the above-mentioned equal division and aligned cumulative operation until a cumulative total result of the N multiplication results is obtained, and use the cumulative total result as a target result of accumulation;

[0088] Among them, the number of the third array and the fourth array is greater than the number of the fifth array and the sixth array.

[0089] The device for fixed-point multiplication and product-accumulation operations provided by the embodiment of the present invention can execute the method for fixed-point multiplication and product-accumulation operations provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0090] In one embodiment, Figure 5 A schematic diagram of the structure of an electronic device provided for an embodiment of the present invention. The electronic device 10 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0091] like Figure 5As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0092] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0093] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as methods for fixed-point multiplication and multiplication-addition operations.

[0094] In some embodiments, the method of fixed-point multiplication and multiplication-accumulation operation may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the method of fixed-point multiplication and multiplication-accumulation operation described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the method of fixed-point multiplication and multiplication-accumulation operation by any other appropriate means (e.g., by means of firmware).

[0095] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0096] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable fixed-point multiplication and multiplication-addition device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0097] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0098] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0099] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0100] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0101] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0102] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for fixed-point multiplication and product-addition operations, characterized in that: The method for fixed-point number multiplication and product-addition operation comprises: Obtain at least two groups of arrays to be subjected to fixed-point multiplication and product-addition operations; wherein the at least two groups of arrays include a first array and a second array; wherein the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers; Determine the product results between the N first fixed-point numbers and the N second fixed-point numbers in the at least two arrays based on the multiplication instruction configured in the multiplier, and form the product results into a third array; Determine the accumulation result corresponding to the product result contained in the third array based on the accumulation instruction configured in the adder; Wherein, the multiplication instruction is a single instruction multiple data (SIMD) instruction; and the accumulation instruction is a very long instruction word (VLIW) instruction.

2. The method according to claim 1, characterized in that The determining, based on the multiplication instruction configured in the multiplier, the product result between the N first fixed-point numbers and the N second fixed-point numbers in the at least two groups of arrays comprises: Identify data types corresponding to the N first fixed-point numbers and the N second fixed-point numbers, respectively; wherein the data types include signed fixed-point numbers and unsigned fixed-point numbers; For N first fixed-point numbers and N second fixed-point numbers of the data type, at least two multiplication instructions configured in the multiplier are used to perform bitwise multiplication of the N first fixed-point numbers and the N second fixed-point numbers according to a preset first clock cycle to obtain corresponding N product results.

3. The method according to any one of claims 1 or 2, characterized in that: The multiplication instruction includes at least two multiplication instructions; each of the multiplication instructions corresponds to a preset first clock cycle; The target number of multiplication instructions corresponds to a preset second clock cycle, wherein the preset first clock cycle is smaller than the preset second clock cycle; The target number of multiplication instructions is selected according to demand.

4. The method according to claim 1, characterized in that: The accumulation instructions include at least two accumulation instructions; the first accumulation instruction among the accumulation instructions starts to be executed after the first preset second clock cycle corresponding to the target number of multiplication instructions.

5. The method according to claim 4, characterized in that The determining, based on the accumulation instruction configured in the adder, the accumulation result corresponding to the product result contained in the third array comprises: In each of the preset second clock cycles, for the N product results under each multiplication instruction, the accumulated result corresponding to the N product results under each multiplication instruction is calculated using the VLIW very long instruction word configured in the adder.

6. The method according to claim 5, characterized in that The method of using the VLIW very long instruction word configured in the adder to calculate the accumulated result corresponding to the N product results under each multiplication instruction includes: For each N product result of each multiplication instruction, a first equal division is first performed to obtain a third array and a fourth array of the same number, and the third array and the fourth array of the same number are bitwise accumulated to obtain a first bitwise accumulated result; wherein the number of the first bitwise accumulated result is the same as the number in the third array and the fourth array; For the first alignment accumulation result, perform a second equal division to obtain a fifth array and a sixth array of the same number, and perform alignment accumulation on the fifth array and the sixth array of the same number to obtain a second alignment accumulation result; wherein the number of the second alignment accumulation result is the same as the number in the fifth array and the sixth array; The second position-aligned accumulation result is used as the first position-aligned accumulation result, and the above-mentioned equal division and position-aligned accumulation operation is repeated until the total accumulation result of the N multiplication results is obtained, and the total accumulation result is used as the target accumulation result; Among them, the number of the third array and the fourth array is greater than the number of the fifth array and the sixth array.

7. A device for fixed-point multiplication and product-addition operations, characterized in that: The device for fixed-point number multiplication and product-addition operation comprises: An array acquisition module, used to acquire at least two groups of arrays to be subjected to fixed-point multiplication and product-addition operations; wherein the at least two groups of arrays include a first array and a second array; wherein the first array includes N first fixed-point numbers, and the second array includes N second fixed-point numbers; A multiplier module, configured to determine the product results between the N first fixed-point numbers and the N second fixed-point numbers in the at least two arrays based on the multiplication instruction configured in the multiplier, and form the product results into a third array; An adder module, configured to determine an accumulation result corresponding to the product result contained in the third array based on an accumulation instruction configured in the adder; Wherein, the multiplication instruction is a single instruction multiple data (SIMD) instruction; and the accumulation instruction is a very long instruction word (VLIW) instruction.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the method for fixed-point multiplication and product-addition operations according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method of fixed-point number multiplication and product-addition operation according to any one of claims 1 to 6 when executed.

10. A computer program product, characterized in that The computer program product comprises a computer program, which, when executed by a processor, implements the method for fixed-point number multiplication and product-addition operation according to any one of claims 1 to 6.

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