Instruction processing method and device, processor, medium, program and computer equipment

Abstract

The embodiment of the invention provides an instruction processing method and device, a processor, a medium, a program and computer equipment. The method on the processor side comprises the steps that an instruction of an application program is obtained; judging whether the instruction is a support instruction of a processor or not; if the instruction is a non-supporting instruction of the processor, determining the type of the instruction in the non-supporting instruction; if the instruction is an extension instruction in a non-support instruction, decoding the instruction to obtain decoding information of the instruction, and storing the decoding information of the instruction to a corresponding register; wherein the extended instruction is an instruction which can be decoded and identified by the processor but cannot be executed; and on the basis that the instruction is a non-support instruction of the processor, triggering an illegal instruction exception, so that an exception handling function corresponding to the illegal instruction exception performs software simulation execution on the basis of decoded decoding information of the extended instruction. According to the embodiment of the invention, the non-support instruction can be efficiently processed, and the hardware cost is controlled.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processor technology, and specifically to an instruction processing method, apparatus, processor, medium, program, and computer equipment. Background Art

[0002] Instructions, as operation commands in a program, can guide the processor to complete calculations and data operations, so that the processor can read, parse and execute instructions (i.e., the processor processes instructions) to realize program functions.

[0003] As a set of instructions that a processor can understand and execute, the instruction set of a processor can be designed specifically according to specific application scenarios, for example, by streamlining and customizing the instruction set, so that the processor can optimize performance, power consumption and cost to adapt to different application scenarios. Therefore, the processor has supported instructions and unsupported instructions. For example, based on a specific application scenario, the instruction set of the processor is designed with supported instructions (i.e., supported instructions), and instructions that are not in the instruction set of the processor can be regarded as unsupported instructions (i.e., unsupported instructions).

[0004] However, the targeted design of the above instruction set will also bring compatibility issues, especially when the program uses instructions that are not supported by the processor, the processor is faced with the situation of processing unsupported instructions. Therefore, how to provide an instruction processing solution to improve the processing efficiency of unsupported instructions and reduce the hardware cost of processing unsupported instructions has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] In view of this, the embodiments of the present application provide an instruction processing method, apparatus, processor, medium, program and computer equipment to improve the processing efficiency of unsupported instructions and reduce the hardware cost of processing unsupported instructions, thereby achieving efficient processing of unsupported instructions and controlling hardware costs.

[0006] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides an instruction processing method, applied to a processor, the method comprising:

[0008] Get instructions for the application;

[0009] Determining whether the instruction is a supported instruction of the processor;

[0010] If the instruction is an unsupported instruction of the processor, determining the type of the instruction among the unsupported instructions;

[0011] If the instruction is an extended instruction among the unsupported instructions, the instruction is decoded to obtain the decoding information of the instruction, and the decoding information of the instruction is saved to a corresponding register; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute;

[0012] And, based on the fact that the instruction is an unsupported instruction of the processor, an illegal instruction exception is triggered, so that an exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

[0013] In a second aspect, an embodiment of the present application provides an instruction processing method, which is applied to system software, wherein a processor runs the system software through a kernel space; the method comprises:

[0014] Calling an exception handling function corresponding to an illegal instruction exception, wherein the exception handling function is deployed in the system software, and the exception handling function is used to handle an illegal instruction exception triggered by an instruction of the application program being an instruction not supported by the processor;

[0015] Using the exception handling function to determine whether the register contains the decoding information of the instruction;

[0016] If the register contains decoding information of the instruction, it is determined that the instruction is an extended instruction among unsupported instructions, and based on the decoding information of the instruction, the instruction is executed by software simulation to obtain a software simulation execution result as the execution result of the instruction; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute.

[0017] In a third aspect, an embodiment of the present application provides an instruction processing device, applied to a processor, the instruction processing device comprising:

[0018] Instruction fetch module, used to fetch instructions from application programs;

[0019] A decoding module, used to determine whether the instruction is a supported instruction of the processor; if the instruction is an unsupported instruction of the processor, determine the type of the instruction in the unsupported instructions; if the instruction is an extended instruction in the unsupported instructions, decode the instruction to obtain the decoding information of the instruction, and save the decoding information of the instruction to a corresponding register; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute;

[0020] The exception handling unit is used to trigger an illegal instruction exception based on the fact that the instruction is an unsupported instruction of the processor, so that the exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

[0021] In a fourth aspect, an embodiment of the present application provides an instruction processing device, which is applied to system software, wherein a processor runs the system software through a kernel space; the instruction processing device includes:

[0022] A calling entry module, used to call an exception handling function corresponding to an illegal instruction exception, wherein the exception handling function is deployed in the system software, and the exception handling function is used to handle an illegal instruction exception triggered by an instruction of the application program that is not supported by the processor;

[0023] The exception handling function module is used to determine whether the register has the decoding information of the instruction; if the register has the decoding information of the instruction, it is determined that the instruction is an extended instruction in the unsupported instruction, and based on the decoding information of the instruction, the instruction is executed by software simulation to obtain the execution result of the software simulation as the execution result of the instruction; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute.

[0024] In a fifth aspect, an embodiment of the present application provides a processor, comprising an instruction processing device as described in the third aspect above.

[0025] In a sixth aspect, an embodiment of the present application provides a computer device, comprising a memory and a processor, wherein the memory stores computer system instructions, and the processor calls the computer system instructions to execute the instruction processing method as described in the second aspect above.

[0026] In a seventh aspect, an embodiment of the present application provides a storage medium, wherein the storage medium stores computer system instructions, and when the computer system instructions are executed, the instruction processing method as described in the second aspect above is implemented.

[0027] In an eighth aspect, an embodiment of the present application provides a computer system program, including computer system instructions, which, when executed, implement the instruction processing method described in the second aspect above.

[0028] In a ninth aspect, an embodiment of the present application provides a computer device, comprising a processor and system software of the computer device; the processor is the processor as described in the fifth aspect above, and the system software comprises the instruction processing device as described in the fourth aspect above.

[0029] It can be seen that, for extended instructions, the processor decodes and parses the extended instructions in advance, so that the decoding information of the extended instructions is saved in advance inside the processor; further, when the instruction is an unsupported instruction of the processor and triggers an illegal instruction exception, the exception handling function corresponding to the illegal instruction exception can reuse the decoding information of the extended instruction that has been decoded inside the processor when processing the extended instruction, and perform software simulation execution on the extended instruction, thereby avoiding the process of re-acquiring the instruction from the memory for software decoding and then software simulation execution, reducing the delay of memory access and software decoding, that is, the exception handling function can directly perform software simulation execution based on the decoding information that has been decoded of the extended instruction, thereby improving the processing efficiency of the extended instruction as an unsupported instruction of the processor. That is to say, if the decoding information of the extended instruction is not saved in advance inside the processor, the exception handling function needs to re-acquire the instruction from the memory and perform software decoding before software simulation execution of the extended instruction, and then perform software simulation execution based on the result of software decoding. Therefore, the embodiment of the present application can reduce the memory access and software decoding delay of the exception handling function when processing the extended instruction, thereby improving the processing efficiency of the extended instruction as an unsupported instruction; at the same time, the embodiment of the present application can avoid adding a coprocessor to participate in the processing of unsupported instructions, reducing hardware complexity and hardware cost. Therefore, the embodiment of the present application can improve the processing efficiency of the extended instruction as an unsupported instruction, and reduce hardware cost, so as to achieve efficient processing of unsupported instructions and control hardware cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0031] Figure 1 A simplified example diagram of a computer architecture.

[0032] Figure 2 An example diagram of the stages of a pipeline.

[0033] Figure 3 An example diagram of multiple instructions being processed in parallel.

[0034] Figure 4 This is an example diagram of the decoding stage.

[0035] Figure 5 A flowchart of an instruction processing method provided in an embodiment of the present application.

[0036] Figure 6 Flowchart for determining the type of instruction among unsupported instructions.

[0037] Figure 7 This is a processing example diagram of the decoding stage provided in an embodiment of the present application.

[0038] Figure 8 Another flow chart of the instruction processing method provided in an embodiment of the present application.

[0039] Fig.9A A block diagram of an instruction processing device provided in an embodiment of the present application.

[0040] Fig. 9B Another block diagram of the instruction processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] For ease of understanding, Figure 1 A simplified example diagram showing a computer architecture is shown by way of example. Figure 1 Mainly used to illustrate that the instructions processed by the processor come from the memory, such as Figure 1 As shown, the computer architecture may include: a processor 100 , a memory 200 , and a computer bus 300 connecting the processor 100 and the memory 200 .

[0043] Among them, the processor 100 is a hardware component responsible for executing instructions and performing data processing. The memory 200 is a hardware component for storing data and programs; based on factors such as data access speed, storage capacity and persistence, the memory can have different types, including but not limited to cache, memory, hard disk, etc. The computer bus 300 can build a communication channel connecting computer components (such as processors, memory, hard disk and other computer components) for transferring data, addresses and control information between connected computer components, including but not limited to data bus, address bus, control bus, etc.

[0044] It should be noted that the processor can be a single-core processor or a multi-core processor. A single-core processor refers to a processor with only one computing core (i.e., one processor core); a multi-core processor refers to a processor with multiple computing cores (i.e., multiple processor cores), each of which can process instructions, so that multiple processor cores can process multiple tasks at the same time, thereby improving the processing power of the processor. The processor processing instructions referred to in the embodiments of the present application can be processor core processing instructions in the processor, and are not limited to single-core processors or multi-core processors.

[0045] The processor (specifically, the processor core in the processor) can obtain instructions from the memory, parse and execute the instructions to complete the computing task of the instructions. In order to improve the throughput and efficiency of the processor in processing instructions, the processor can use pipeline technology to process instructions. Specifically, the pipeline decomposes the instruction processing process into multiple stages. A stage can be regarded as a subtask of processing instructions, so that multiple instructions can be in different stages at the same time to achieve parallel execution of multiple instructions. In other words, the pipeline can decompose and parallelize the process of the processor processing instructions in stages, thereby improving the efficiency of the processor processing instructions. For example, taking a 5-stage pipeline as an example, Figure 2 An example diagram of the stages of the pipeline is shown as follows: Figure 2 As shown, the stages of the pipeline may include:

[0046] Instruction Fetch (IF) stage, used to read instructions from storage (such as memory or cache);

[0047] The Instruction Decode (ID) stage is used to decode and parse instructions, identify the instruction operation type and required operands, and other information;

[0048] The Execute (EX) stage is used to perform the operations defined by the instructions, such as addition, multiplication, or logical operations;

[0049] Memory Access (MEM) stage is used to access the memory to read or write data;

[0050] The Write Back (WB) stage is used to write the calculation results back to the register or memory.

[0051] It should be noted that the above is an example of a 5-stage pipeline of instruction fetch, decode, execute, memory access and write back. The specific number of pipeline stages (i.e., the specific number of stages of the pipeline) and the specific architecture can be adjusted and designed accordingly according to different processor requirements, and are not limited to the form of a 5-stage pipeline. For example, the processor can use pipeline stages of different numbers and complexities according to performance, power consumption, cost and other goals. Therefore, the number of pipeline stages of the processor can be more or less than 5, depending on the design goals and application scenarios of the processor.

[0052] Based on the use of pipelines, the instruction stream entering the pipeline (i.e., multiple instructions entering the pipeline) can be in different stages at the same time, thereby realizing the parallel execution of multiple instructions and shortening the processing completion time of the instruction stream; for example, the j-th stage of the latter instruction in the instruction stream can be executed simultaneously with the j+1-th stage of the previous instruction, that is, adjacent stages of adjacent instructions can be executed simultaneously, and the stage of the previous instruction in adjacent instructions is faster than the stage of the latter instruction, so that the processor can process different stages of multiple instructions simultaneously in the same clock cycle, thereby improving the instruction processing performance of the processor.

[0053] For ease of understanding, Figure 3 An example diagram showing multiple instructions being processed in parallel is shown, Figure 3 As shown, taking the multiple instructions in the instruction stream as instructions i1, i2, i3 and i4 as an example, in clock cycle 1, instruction i1 is in the IF (instruction fetch) stage; in clock cycle 2, instruction i1 is in the ID (decoding) stage, and instruction i2 enters the pipeline in the IF stage; in clock cycle 3, instruction i1 is in the EX (execution) stage, instruction i2 is in the ID stage, and instruction i3 enters the pipeline in the IF stage; in clock cycle 4, instruction i1 is in the MEM (memory access) stage, instruction i2 is in the EX stage, instruction i3 is in the ID stage, and instruction i4 enters the pipeline in the IF stage, and so on. It can be seen that the stage of the previous instruction in the pipeline is one stage faster than the stage of the next instruction in the pipeline, so that instructions i1, i2, i3 and i4 are in different stages of the pipeline in the same clock cycle, and then the processor can process different stages of instructions i1, i2, i3 and i4 simultaneously in the same clock cycle, realizing parallel processing of instructions i1, i2, i3 and i4.

[0054] It should be noted that in the pipeline, the program counter (PC) is used to store the address of the next instruction to be processed and is one of the control registers in the pipeline; for example, after each instruction fetch stage is completed, the program counter can be automatically updated to point to the address of the next instruction (such as a memory address), that is, the value of the program counter will be automatically updated with each instruction fetch stage, providing an address for the next instruction to ensure that the pipeline continues to fill new instructions. Pipeline registers are used for instructions to transfer information (such as data and status information) between various stages of the pipeline. Each stage of the pipeline can have a corresponding pipeline register to save information transferred from the previous stage; that is, pipeline registers can ensure that each stage can work in parallel and keep intermediate results. In addition, when different instructions are in different stages of the pipeline at the same time, the pipeline registers can save the intermediate data of these instructions to ensure that the parallel processing of different instructions in the pipeline can proceed smoothly.

[0055] During the process of processing instructions, if the processor finds that the instruction is an unsupported instruction of the processor, that is, the instruction is not within the support range of the processor, then the unsupported instruction of the processor can be regarded as an abnormal instruction, and an abnormal instruction processing mechanism different from that of the pipeline stage needs to be used to process the unsupported instruction.

[0056] It should be noted that the processor's unsupported instructions may be instructions that were omitted during the design phase of the processor's instruction set. For example, in the instruction set design of a processor that runs an AI (Artificial Intelligence) application, such as the instruction set design of a GPGPU (General Purpose Graphics Processing Unit), the processor's instruction set will selectively omit instructions that most AI applications will not use to improve performance, reduce power consumption and cost. For example, most AI applications will not use 64-bit floating-point numbers for calculations, so the processor will pay more attention to 16-bit and 32-bit floating-point arithmetic instructions, so that the instruction set of the processor running the AI ​​application will omit 64-bit floating-point arithmetic instructions when designing, such as omitting a 64-bit floating-point arithmetic unit in the processor. The design of omitting a 64-bit floating-point arithmetic unit is sufficient for most AI applications, but it may cause incompatibility for a small number of AI applications that require high-precision operations. For example, some AI applications and frameworks will use 64-bit floating-point numbers. At this time, the processor may still encounter 64-bit floating-point arithmetic instructions when running the application, resulting in instruction exceptions.

[0057] It is worth noting that the above uses a processor running an AI application and 64-bit floating-point arithmetic instructions to illustrate the situation where the processor does not support instructions. The processor's unsupported instructions may also exist in other forms and are not limited to 64-bit floating-point arithmetic instructions. That is, the embodiments of the present application do not limit the form of the processor or the form of the processor's unsupported instructions.

[0058] The processor's unsupported instructions can be directly treated as illegal instructions (illegal instructions are a form of abnormal instructions), so that the unsupported instructions are processed using an illegal instruction processing mechanism (a form of abnormal instruction processing mechanism).

[0059] One way to handle the illegal instruction processing mechanism is to use a coprocessor to simulate the illegal instruction, obtain the simulation result and return it to the processor, so that the processor can continue to execute subsequent instructions after obtaining the simulation result of the illegal instruction. Among them, the coprocessor is an auxiliary processing unit of the processor (such as CPU, GPGPU, etc.), which is used to provide additional functions and computing power for the processor. For example, the coprocessor can perform specific types of operations (such as floating-point operations, graphics processing operations, etc.) or process special instruction extensions.

[0060] Specifically, when the processor determines that the instruction currently being processed is an unsupported instruction, it is considered an illegal instruction. At this time, the processor does not immediately terminate the program or trigger an exception, but sends the instruction to the coprocessor for processing; after the coprocessor receives the instruction, it simulates the execution of the instruction (that is, the coprocessor simulates the execution process of the instruction through software or hardware) to obtain the simulation result of the instruction, and the coprocessor feeds the simulation result back to the processor; after the processor obtains the simulation result of the instruction, it continues to execute subsequent instructions normally.

[0061] The illegal instruction processing mechanism involving the above-mentioned coprocessor can make the processor not need to directly report an error or terminate the program, but hand over the illegal instructions to a special coprocessor for processing, avoiding system crashes or abnormal exits; however, the illegal instruction processing mechanism involving the coprocessor requires the configuration of an additional coprocessor to handle illegal instructions, which means that in addition to setting up the processor, additional coprocessor hardware must be added, which incurs additional hardware costs; and in order to support the coprocessor, the design of the computer architecture requires major hardware changes. For example, tasks originally handled by the processor now require the participation of the coprocessor, which requires adjustments and changes to the design of the instruction set architecture, bus structure, data flow, etc., and the hardware changes undoubtedly further increase the hardware cost. Furthermore, the coprocessor can only handle specific types of operations or special instruction extensions. If new instructions or requirements are encountered, the coprocessor may need to be upgraded or replaced, so the flexibility of the coprocessor is limited.

[0062] It can be seen that the illegal instruction processing mechanism based on the participation of the coprocessor has a high hardware cost and low flexibility.

[0063] Another way to handle the illegal instruction processing mechanism is to check whether the instruction is a supported instruction of the processor during the decoding stage of the pipeline. If the instruction is not supported by the processor, an illegal instruction exception is triggered, so that the illegal instruction exception can be reported to the computer's operating system, and the operating system responds.

[0064] To facilitate understanding of reporting illegal instruction exceptions, Figure 4 An example diagram of the decoding stage is shown as an example. Figure 4 As shown, the decoding stage can be implemented by a decoding module in the processor, and the decoding module can be a decoder group formed by multiple decoders. The input of the decoding module is the instruction output in the instruction fetch stage, and the output of the decoding module is the decoding information of the instruction, such as the decoding information such as the opcode and operand after the instruction is parsed. The decoding information of the instruction is used in the subsequent execution stage; in the decoding stage, according to the type of supported instructions of the processor, the decoding module decodes different types of supported instructions, so the decoding module can set decoding units of multiple types of supported instructions, including but not limited to:

[0065] A memory access instruction decoding unit. A memory access instruction is an instruction that needs to access memory, such as a load instruction and a store instruction. The memory access instruction decoding unit needs to parse the address corresponding to the memory access instruction and identify whether the memory access instruction is a load or store operation;

[0066] A branch instruction decoding unit. Branch instructions are used to control program flow, such as conditional branch instructions (such as jump instructions) and unconditional branch instructions. The branch instruction decoding unit needs to determine whether the branch condition is met (such as whether the condition for executing the jump is met) and determine the branch target address;

[0067] Computational instruction decoding unit: Computational instructions are instructions for performing arithmetic or logical operations, such as addition, subtraction, and operation, or operation, etc. The operands of the computational instructions can come from registers or immediate values ​​(i.e., constant values ​​given in the instructions). The computational instruction decoding unit needs to parse out information such as the source operands of the computational instructions;

[0068] Vector instruction decoding unit. Vector instructions are instructions for processing vector data. They are used for multi-data parallel computing and can operate multiple data elements at one time. The vector instruction decoding unit needs to parse out relevant information about the vector operation, such as the operand, the length of the vector, etc.

[0069] It should be noted that the types of instructions supported by the processor and the corresponding decoding units described above are only examples, and the types of instructions supported by the processor and the corresponding decoding units are not limited to the above description. It should be further noted that in the decoding stage, the processor needs to read and parse the operands corresponding to the instructions, which are stored in registers, so the decoding stage needs to store and transfer information through registers.

[0070] Combination Figure 4 As shown, if the instruction input into the decoding stage is an unsupported instruction, the decoding stage will trigger an illegal instruction exception. For example, the decoding module can pass the information of the unsupported instruction to the exception handling unit inside the processor, thereby reporting the illegal instruction exception through the exception handling unit.

[0071] Among them, the exception handling unit is a module component inside the processor, which is responsible for handling exceptions during the execution of the processor; for example, the exception handling unit can be an interrupt controller in the processor, and the interrupt controller can respond to and manage exceptions or interrupt signals. Of course, the interrupt controller is only an example of an exception handling unit, and the exception handling unit can also have other forms.

[0072] The exception handling unit can report the illegal instruction exception to the computer's operating system, so that the operating system can determine a response mechanism to handle the illegal instruction exception. The operating system's response to the illegal instruction exception can be divided into two ways: implementing instruction extension through software and terminating the application.

[0073] Implementing instruction extension through software means that when the operating system receives a reported illegal instruction exception, it does not directly terminate the application program, but extends the instruction through software so that the processor can continue to execute; specifically, for instructions that report illegal instruction exceptions, the operating system can read the instruction from the memory according to the memory address of the instruction (for example, calculate the memory address of the instruction from the instruction pointer register, and then obtain the instruction from the memory address), and then parse the instruction through software decoding (that is, understand the meaning of the instruction through a software algorithm), and then implement the function of the instruction through software simulation based on the instruction information parsed by software decoding. However, this method involves re-acquiring instructions from the memory, and then performing software decoding and simulation execution, which is a relatively slow process, resulting in low processing efficiency for unsupported instructions.

[0074] Terminating an application means that the operating system directly terminates the application corresponding to the instruction. For example, the operating system passes the instruction exception information to the application, thereby informing the application that an illegal instruction is encountered, and then terminating the application. After the application is terminated, the user can perform subsequent processing as needed, such as restarting the program, checking for problems in the code, updating the processor or system configuration, etc., to solve the problem caused by the illegal instruction. However, this method will cause the instruction function to be unable to execute, and the application will not be able to run normally due to encountering illegal instructions, which reduces the reliability of the application. If the user is required to handle the crash or stop of the application by himself, he may need to restart the program, reload data, or manually adjust settings, which will increase the burden on the user, and the user's operation threshold is high and it is not user-friendly.

[0075] It can be seen that the illegal instruction processing mechanism of the operating system that implements instruction extension through software has low processing efficiency, and the illegal instruction processing mechanism that terminates the application has problems such as missing instruction functions and low application reliability.

[0076] Based on this, the embodiments of the present application provide an improved instruction processing solution that supports processing of unsupported instructions of the processor, and can improve the processing efficiency of unsupported instructions, and reduce the hardware cost of processing unsupported instructions, thereby achieving efficient processing of unsupported instructions and controlling hardware costs.

[0077] As an optional implementation, the instruction processing method provided in the embodiment of the present application can be interactively executed by the processor and the system software, so that the instruction processing method provided in the embodiment of the present application is divided into a process on the processor side and a process on the system software side. Among them, the system software is, for example, an operating system; it can be understood that the operating system is a system-level software that manages computer hardware and software resources, and is used to manage and coordinate the work of various hardware of the computer (such as CPU, memory, hard disk, peripherals, etc.); the processor is the hardware part of the computer, responsible for executing machine instructions and performing data processing; that is, the processor interacts directly with the hardware resources of the computer, and the operating system is responsible for managing the hardware resources of the computer, providing an abstract layer to coordinate the execution of different tasks, and providing a running environment for applications.

[0078] The following is an introduction to the process on the processor side as an optional implementation. Figure 5 An optional flow chart of the instruction processing method provided in the embodiment of the present application is shown as an example. Figure 5 As shown, the process on the processor side may include the following steps.

[0079] Step S510: Obtain application program instructions.

[0080] For example, through the instruction fetch stage of the pipeline, the instructions of the application are obtained from a storage such as a cache or a memory, and the instructions of the application include but are not limited to the instructions of the application such as an AI application, which can be regarded as the instructions of the program in the user space. In an optional implementation, step S510 can be executed by an instruction fetch module that implements the instruction fetch stage in the processor.

[0081] Step S511, determine whether the instruction is a supported instruction of the processor, if so, execute step S512, if not, execute step S513.

[0082] Step S511 enters the decoding stage. In the decoding stage, the decoding module (such as a decoder) of the processor can determine whether the instruction is a supported instruction of the processor before decoding the instruction. If the instruction is a supported instruction, the embodiment of the present application processes the instruction in a normal pipeline stage. If the instruction is an unsupported instruction, it is processed using the illegal instruction processing mechanism provided in the embodiment of the present application.

[0083] As an optional implementation, the instruction set of the processor defines the supported instructions of the processor. The embodiment of the present application can determine whether the instruction is a supported instruction by determining whether the instruction belongs to the instruction set of the processor; for example, if the instruction does not belong to the instruction set of the processor, it means that the instruction is an unsupported instruction, and if the instruction belongs to the instruction set of the processor, it means that the instruction is a supported instruction. For example, the instruction set, as a set of supported instructions of the processor, can include information such as the opcode and function description of each supported instruction. The embodiment of the present application can compare the opcode of the instruction with the instruction set. If the opcode of the instruction is included in the instruction set, the instruction is a supported instruction of the processor; if the opcode of the instruction is not included in the instruction set, the instruction is an unsupported instruction of the processor.

[0084] Step S512: Process the instruction in normal pipeline stages.

[0085] In an alternative implementation, the normal pipeline stages are divided into processor support instruction decoding (e.g. Figure 4 The memory access instruction decoding, branch instruction decoding, calculation instruction decoding, vector instruction decoding, etc. shown in the figure), the subsequent execution stage, memory access stage, write back stage, etc., can refer to the description of the pipeline process in the previous article and will not be expanded here.

[0086] Step S513: Determine the type of the instruction in the unsupported instructions, where the unsupported instruction types are divided into extended instructions and illegal instructions.

[0087] In the case where the instruction is determined to be an unsupported instruction (i.e., step S511 determines that the instruction is not a supported instruction), the embodiment of the present application does not directly treat the unsupported instruction as an illegal instruction, but rather classifies the unsupported instructions of the processor into extended instructions and illegal instructions. In other words, if the instruction is an unsupported instruction, the embodiment of the present application can determine the type of the instruction in the unsupported instructions to determine whether the instruction is an extended instruction or an illegal instruction.

[0088] Among them, the extended instruction is an instruction that is not included in the instruction set when the processor is designed, but can be decoded and recognized. In other words, the format of the extended instruction is legal, and the processor can correctly parse the extended instruction in the decoding stage (such as the decoder) (that is, the extended instruction can be decoded and recognized), but because the extended instruction is not included in the instruction set, there is no execution unit corresponding to the extended instruction in the processor to actually execute the extended instruction; it can be understood that the execution unit corresponds to the execution stage of the pipeline, and the extended instruction does not have a corresponding execution unit in the processor, so the extended instruction cannot be executed and processed in the execution stage. For example, the extended instruction such as 64-bit floating-point operation instructions can be decoded and recognized in the decoding stage (such as the decoder), but the processor does not have the corresponding execution unit instruction.

[0089] An illegal instruction is an instruction that cannot be decoded and cannot be executed. In other words, the processor's decoder and execution unit cannot identify the instruction as an illegal instruction. For example, an illegal instruction may be unable to be decoded and recognized by the processor and cannot be executed by the processor due to reasons such as an instruction format error or not belonging to any supported instruction set.

[0090] As an optional implementation, Figure 6 An exemplary flowchart of determining the type of an instruction among unsupported instructions is shown, referring to Figure 6 The method flow may include the following steps.

[0091] Step S610: Determine the operation code of the instruction.

[0092] Step S611, compare the operation code of the instruction with the instruction set extension information of the processor.

[0093] When an instruction does not belong to the instruction set of the processor (for example, the opcode of the instruction is not included in the instruction set of the processor), the instruction is not a standard instruction defined by the instruction set of the processor, that is, the instruction is an unsupported instruction. In an optional implementation, for an unsupported instruction, the embodiment of the present application may further compare the opcode of the unsupported instruction with the instruction set extension information of the processor to determine whether the unsupported instruction is an extended instruction.

[0094] The instruction set extension information of the processor, such as the instruction set extension table, can define the additional extended instructions of the processor, such as recording the opcode, format, instruction function, and tag information of the additional extended instructions of the processor; for example, in the instruction set extension table, the instruction will have a tag to indicate whether the instruction has a corresponding execution unit. If the tag in the entry corresponding to the instruction in the instruction set extension table indicates that the instruction has no corresponding execution unit, it means that the instruction is legal and can be decoded and recognized, but there is no corresponding execution unit for subsequent execution. Therefore, by comparing the opcode of the unsupported instruction with the instruction set extension information, and checking the corresponding tag of the unsupported instruction in the entry of the instruction set extension information, it can be determined whether the unsupported instruction is an extended instruction.

[0095] It should be noted that the processor's instruction set (i.e., the processor's standard instruction set, also called the basic instruction set) is a collection of instructions supported by the processor, while the instruction set extension information (such as the instruction set extension table) defines additional extended instructions based on the processor's instruction set.

[0096] Step S612: If the operation code of the instruction is recorded in the instruction set extension information, and the mark of the instruction in the instruction set extension information indicates that the instruction has no corresponding execution unit, then the instruction is confirmed to be an extended instruction.

[0097] For instructions that are not supported, after comparing the opcode of the instruction with the instruction set extension information, if it is found that the opcode of the instruction is recorded in the instruction set extension information, it can be confirmed that the instruction is a legal instruction, that is, although the instruction is not a standard supported instruction defined by the instruction set of the processor, it is an additional extended instruction of the instruction set extension information; in this case, if the mark of the corresponding entry of the instruction in the instruction set extension information also indicates that the instruction has no corresponding execution unit, then the instruction is confirmed to be an extended instruction in the unsupported instruction.

[0098] Step S613: If the operation code of the instruction is not recorded in the instruction set extension information, the instruction is confirmed to be an illegal instruction.

[0099] For instructions that are unsupported instructions, after comparing the instruction's opcode with the instruction set extension information, if it is found that the instruction's opcode is not recorded in the instruction set extension information, the instruction is confirmed to be an illegal instruction among the unsupported instructions, that is, the instruction is neither a standard supported instruction defined by the processor's instruction set nor an additional extended instruction by the instruction set extension information. At this time, the instruction cannot be decoded and identified, nor can it be executed and processed, and corresponds to an illegal instruction.

[0100] It should be noted that Figure 6It is only an optional way to classify instructions as extended instructions and illegal instructions when the instructions are unsupported instructions. Any way that can determine that the instructions can be decoded and recognized and have no corresponding execution unit can be regarded as a way for the embodiments of the present application to classify instructions as extended instructions. Any way that can determine that the instructions cannot be decoded and recognized and cannot be executed can be regarded as a way for the embodiments of the present application to classify instructions as illegal instructions. For example, when it is determined that the instruction does not belong to the instruction set of the processor, that is, when the instruction is confirmed to be an unsupported instruction, the embodiments of the present application can further perform a legality check on the instruction format of the instruction. If the format of the instruction is found to be illegal, the instruction is deemed to be an illegal instruction.

[0101] Back to Figure 5 As shown, in step S514, if the instruction is an extended instruction, the instruction is decoded to obtain decoding information of the instruction, and the decoding information of the instruction is saved in a corresponding register.

[0102] If the instruction is judged to be an unsupported instruction and an extended instruction among unsupported instructions, the instruction can be decoded and identified, so that the processor can decode and parse the instruction in the decoding stage (for example, the decoder in the processor can decode and parse the extended instruction) to obtain the decoding information of the instruction, that is, the decoding result of the instruction.

[0103] In an optional implementation, the processor may set an extended instruction decoding unit in the decoding stage to support decoding and parsing of extended instructions. As an optional implementation, Figure 7 The following is an exemplary diagram showing the processing example of the decoding stage provided in the embodiment of the present application, combined with Figure 4 and Figure 7 As shown, in addition to the memory access instruction decoding unit, branch instruction decoding unit, calculation instruction decoding unit, vector instruction decoding unit and other types of decoding units supporting instructions, the decoding module of the processor is also provided with an extended instruction decoding unit to support the decoding and parsing of extended instructions. Among them, the extended instruction decoding unit can be regarded as a logic unit set by the processor in the decoding stage (such as the decoding module) for parsing and identifying extended instructions. That is to say, in the decoding stage, if the decoding module checks that the instruction is an extended instruction, the instruction is handed over to the extended instruction decoding unit for further decoding and parsing.

[0104] After decoding the instruction belonging to the extended instruction, the embodiment of the present application can obtain the decoding information of the instruction, that is, the specific information that can be understood by the processor after the instruction is converted during the decoding and parsing process, including but not limited to:

[0105] Machine code, the binary representation of instructions, is the code that the processor can directly understand and execute, including opcodes (the operation part of the instruction, which defines the type of operation of the instruction), operands (that is, the number of operands required for the instruction to perform the operation), etc.

[0106] Destination operand, the location where the execution result of the instruction is stored. The execution result of the instruction can be stored in a register or memory;

[0107] Source operand, the input data required when the instruction is executed;

[0108] Modifiers are additional information of instructions used to control the execution mode. For example, for floating-point operation instructions, modifiers are used to specify the precision, rounding method, overflow mode, etc. of floating-point numbers.

[0109] Furthermore, the decoding information of the instruction can be saved in the corresponding register, and different types of decoding information can be saved in different types of registers. For example, after the instruction is decoded, different types of decoding information such as machine code, destination operand, source operand, modifier, etc. can be obtained. These different types of decoding information can be saved in different types of registers respectively. For example, Figure 7 As shown, the registers of the decoding module include but are not limited to:

[0110] Machine code register, used to store the machine code of the instruction;

[0111] Destination operand register, used to store the destination operand of the instruction;

[0112] A source operand register for storing a source operand of an instruction; wherein the source operand register may be in the form of a register group, and the number of source operand register groups may be determined based on the maximum number of source operands of the extended instruction. For example, different instructions may require different numbers of source operands. In the embodiment of the present application, the size of the source operand register group may be determined based on the maximum number of source operands of the extended instruction; that is, the number of source operand register groups is set to the corresponding number of source operands required by the extended instruction at most;

[0113] A modifier register is used to store the modifier of the instruction; different instructions may require different modifiers, or some instructions may not require modifiers, so the embodiment of the present application can increase or decrease the modifier register based on the needs of the extended instruction, or even not set the modifier register.

[0114] It should be noted that the content of the decoding information of the above-mentioned instructions and the corresponding registers are only used as an example. The embodiments of the present application can also support other contents in the decoding information of the instructions, which are correspondingly saved in other registers of the decoding module. The embodiments of the present application do not limit the specific content form of the decoding information of the instructions and the corresponding register form.

[0115] Step S515: If the instruction is an illegal instruction, clear the corresponding register.

[0116] If the instruction is judged to be an unsupported instruction and an illegal instruction among the unsupported instructions, the instruction cannot be decoded and recognized and cannot be executed. Therefore, for the illegal instruction, the processor can clear the relevant registers to ensure that no invalid or erroneous information affects subsequent processing. In an optional implementation, for the illegal instruction, the embodiment of the present application can clear the machine code register, the destination operand register, the source operand register, the modifier register and other related registers.

[0117] Step S516: Generate an illegal instruction exception signal.

[0118] In the embodiment of the present application, if the instruction is judged to be an unsupported instruction, whether the instruction is an extended instruction in the unsupported instruction or an illegal instruction, it is reported to the system software (such as an operating system) through an illegal instruction exception, so that the system software can respond and process; that is, if the instruction is judged to be an unsupported instruction in the embodiment of the present application, the illegal instruction exception can be triggered based on the instruction being an unsupported instruction of the processor. It should be noted that the difference between the extended instruction and the illegal instruction when triggering the illegal instruction exception is that the extended instruction can be decoded and identified but cannot be executed, so the register stores the decoding information of the extended instruction, that is, there is a value in the register; and the illegal instruction cannot be decoded and identified and cannot be executed, so the register is cleared, that is, there is no value in the register. Therefore, when the system software is processed later, the system software can distinguish whether the current instruction is an extended instruction in the unsupported instruction or an illegal instruction in the unsupported instruction by whether there is a value in the register, such as whether there is a machine code value in the machine code register.

[0119] As an optional implementation, the decoding module of the processor can generate an illegal instruction exception signal. Further, based on the illegal instruction exception report being performed by the exception handling unit in the processor, the illegal instruction exception signal generated by the decoding module can be transmitted to the exception handling unit in the processor, thereby triggering an illegal instruction exception, that is, the decoding module notifies the exception handling unit of the illegal instruction exception signal, so that the exception handling unit triggers an illegal instruction exception, such as triggering an illegal instruction interrupt. For example, in combination with Figure 7As shown, for extended instructions, after the decoding module decodes and analyzes the extended instructions and saves the decoding information to the corresponding register, it can pass an illegal instruction exception signal to the exception handling unit to trigger an illegal instruction exception; for illegal instructions, after the decoding module clears the corresponding register, it can pass an illegal instruction exception signal to the exception handling unit to trigger an illegal instruction exception.

[0120] In an optional implementation, Figure 5 Steps S511 to S516 shown may be executed by a decoding module in a processor that implements a decoding stage. Figure 5 Subsequent steps S517 to S518 of the process shown may be executed by an exception handling unit (eg, an interrupt controller) in the processor.

[0121] Step S517: Save the return address of the processor.

[0122] Step S518: Based on the illegal instruction exception signal, jump to the exception handling function corresponding to the illegal instruction exception.

[0123] Based on the fact that the instruction is an unsupported instruction of the processor, the exception handling unit can obtain an illegal instruction exception signal. For example, the exception handling unit can receive the illegal instruction exception signal transmitted by the decoding module to obtain the illegal instruction exception signal. After the exception handling unit obtains the illegal instruction exception signal, it can parse the illegal instruction exception signal and save the return address of the processor; and, based on the illegal instruction exception signal, jump to the exception handling function corresponding to the illegal instruction exception, wherein the exception handling function is deployed in the system software, so that the subsequent process can be transferred to the system software for processing.

[0124] As an optional implementation, the exception handling unit can jump to the exception handling function corresponding to the processor exception type of illegal instruction exception predefined by the system software based on the processor exception type corresponding to the illegal instruction exception signal being illegal instruction exception, that is, jump to the exception handling function corresponding to the illegal instruction exception.

[0125] Among them, the processor exception type is the classification of the abnormal event of the processor, including but not limited to illegal instruction exception, memory access exception, arithmetic error exception, hardware fault exception, etc. In an optional implementation, when the processor encounters an unsupported instruction (not limited to the extended instruction or illegal instruction referred to in the embodiment of the present application), it may belong to the processor exception type of illegal instruction exception; that is, the extended instruction and illegal instruction in the embodiment of the present application uniformly use the processor exception type of illegal instruction exception, that is, the extended instruction and the illegal instruction share the illegal instruction exception signal to indicate that the processor exception type is an illegal instruction exception, so that the illegal instruction exception signal may not distinguish whether it is an illegal instruction exception caused by an extended instruction or an illegal instruction. As mentioned above, the system software side can distinguish whether the unsupported instruction is an extended instruction or an illegal instruction by whether there is a value in the register (for example, whether there is a machine code value in the machine code register).

[0126] In other possible implementations, the embodiments of the present application may also support distinguishing between illegal instruction exceptions caused by extended instructions and illegal instruction exceptions caused by illegal instructions through illegal instruction exception signals, for example, carrying information about extended instructions or illegal instructions in illegal instruction exception signals for distinction; of course, this is only an optional implementation method.

[0127] In a further optional implementation, different processor exception types can be identified using different exception vector numbers, and correspondingly, the processor exception type of the illegal instruction exception can be identified using the vector number of the illegal instruction exception (referred to as the illegal instruction exception vector number for short); thus, after receiving the illegal instruction exception signal, the exception handling unit can determine the illegal instruction exception vector number corresponding to the illegal instruction exception by parsing the illegal instruction exception signal. For example, through the format and signal information of the illegal instruction exception signal, it can be confirmed that the processor has pre-associated the illegal instruction exception signal with the illegal instruction exception vector number corresponding to the processor exception type; further, based on the illegal instruction exception vector number, determine the entry address of the exception handling function of the processor exception type of the illegal instruction exception; based on the entry address, jump to the exception handling function of the illegal instruction exception, that is, jump to the exception handling function corresponding to the illegal instruction exception.

[0128] That is to say, various processor exception types are respectively pre-defined with corresponding exception vector numbers (such as digital numbers), which are used to uniquely identify the processor exception type and correspond to the entry address of the exception handling function of the processor exception type; thus, for the processor exception type of illegal instruction exception, the exception handling unit can determine the entry address of the exception handling function corresponding to the illegal instruction exception through the illegal instruction exception vector number, and then jump to the exception handling function corresponding to the illegal instruction exception to continue subsequent processing.

[0129] In a further optional implementation, the processor can set an interrupt vector data structure (such as an interrupt vector table) to record the exception vector numbers of various processor exception types and the entry addresses of the exception handling functions, for example, recording the correspondence between the exception vector numbers of various processor exception types and the entry addresses of the exception handling functions; thus, after receiving the illegal instruction exception signal, the exception handling unit can determine the illegal instruction exception vector number; in the interrupt vector data structure (such as the interrupt vector table), based on the illegal instruction exception vector number, search for the entry address of the corresponding exception handling function, that is, search for the entry address of the exception handling function of the illegal instruction exception; and then, based on the entry address of the exception handling function found, jump to the exception handling function of the illegal instruction exception.

[0130] In a further optional implementation, when the computer system is initialized, the operating system or processor may associate and bind the entry address of the exception handling function of each processor exception type with the exception vector number corresponding to the processor exception type, and record it in an interrupt vector data structure (such as an interrupt vector table); when a certain processor exception type occurs in the processor, the exception handler unit can find the entry address of the corresponding exception handling function through the exception vector number of the processor exception type, and then jump to the corresponding exception handler for execution based on the entry address.

[0131] In a further optional implementation, the exception vector numbers of various processor exception types may be predefined by the processor, and the exception handling functions of various processor exception types (including exception handling functions for illegal instruction exceptions) may be pre-written in the system software, thereby being predefined in the system software.

[0132] In order to facilitate the processor to continue subsequent execution after the exception handling function of the illegal instruction exception is executed, the exception handling unit can also save the return address of the processor after receiving the illegal instruction exception signal. The return address of the processor is the address to which the processor returns to continue execution after the illegal instruction exception is processed by the corresponding exception handling function. In an optional implementation, the exception handling unit can save the return address of the processor by reading the program counter (PC) and saving the value of the program counter.

[0133] Furthermore, in an optional implementation of jumping to an exception handling function corresponding to an illegal instruction exception based on the entry address of the exception handling function corresponding to the illegal instruction exception, the exception handling unit may set the program counter (PC) to the entry address of the exception handling function corresponding to the illegal instruction exception, thereby enabling the processor to jump to the exception handling function corresponding to the illegal instruction exception for execution.

[0134] After jumping to the exception handling function corresponding to the illegal instruction exception, based on the fact that the exception handling function belongs to the function component in the system software, the process can jump to the system software side for execution. It can be understood that the exception handling function is part of the system software (such as the operating system) and belongs to the code of the system software (such as the operating system); although the exception handling function belongs to the code of the operating system, it is still executed by the processor because the final execution depends on the processor hardware. Specifically, the instructions in the exception handling function belong to the code of the operating system and are responsible for handling the abnormal events of the processor, and the instructions in the exception handling function are Figure 5 The instructions of the application (such as AI application, etc.) in the shown process are different, that is, the application can be understood as a user space program, and the application instructions interact with the hardware through the interface provided by the operating system, while the exception handling function runs in the operating system kernel space and is mainly used to respond to hardware events, such as handling processor exception events.

[0135] That is to say, Figure 5 The process shown can be understood as the process of the processor's pipeline architecture in processing instructions of application programs in user space; and the process on the system software side can be understood as the process of the processor executing the exception handling function in the operating system kernel space, that is, the processor runs the system software through the kernel space, so the execution of the exception handling function in the system software can be regarded as the process of handling illegal instruction exceptions in the kernel space.

[0136] The following is a follow-up introduction to the process from the system software side as an optional implementation. Figure 8 Another optional flow chart of the instruction processing method provided in the embodiment of the present application is shown as an example. Figure 8 As shown, the process on the system software side may include the following steps.

[0137] Step S810: Call an exception handling function corresponding to an illegal instruction exception, where the exception handling function is used to handle an illegal instruction exception triggered by an instruction of the application program that is not supported by the processor.

[0138] As mentioned above, the processor's unsupported instructions (not limited to extended instructions or illegal instructions) will cause an illegal instruction exception signal to be generated in the decoding stage and transmitted to the exception handling unit, thereby triggering an illegal instruction exception, which is then jumped to the exception handling function corresponding to the illegal instruction exception for processing. When the control flow jumps to the exception handling function corresponding to the illegal instruction exception (for example, based on the corresponding entry address, the processor jumps to the exception handling function corresponding to the illegal instruction exception), the processor enters kernel mode, at which time the processor can access the code and resources of the operating system kernel to call the exception handling function corresponding to the illegal instruction exception to process the illegal instruction exception triggered by the application's instruction being an unsupported instruction of the processor.

[0139] Step S811: Use the exception handling function to save the status of registers related to the illegal instruction exception.

[0140] After being called, the exception handling function can save the state of the registers related to the illegal instruction exception, so that after the exception handling function completes the illegal instruction exception, the processor can resume to the normal execution state; this process can be regarded as the exception handling function protecting the scene. In other words, protecting the scene means saving the current state of the registers, and the state of the registers can correspond to the execution state of the application, so that after the exception handling function completes the illegal instruction exception, the execution of the application can be resumed.

[0141] In an optional implementation, the processing of the exception handling function does not modify all registers, so the exception handling function can only protect the registers used by the exception handling function when protecting the scene, that is, the exception handling function can save the status of the registers related to the illegal instruction exception, rather than saving the status of all registers. For example, the exception handling function may use machine code registers, program counters, status registers, etc., while other registers may not be affected during the exception handling process. Therefore, the exception handling function only needs to protect the machine code registers, program counters, status registers and other registers that will be modified by the exception handling function, so as to save and back up the status of the machine code registers, program counters, status registers and other registers to reduce the overhead of saving the scene and subsequently restoring the scene.

[0142] In an optional implementation, the exception handling function may push the status of registers related to the illegal instruction exception into a stack or save it to a specific memory area to save the status of the related registers.

[0143] Step S812: Use the exception handling function to determine whether there is instruction decoding information in the register. If so, execute step S813; if not, execute step S815.

[0144] As mentioned above, when the instruction is an extended instruction, the instruction will be decoded and identified during the decoding stage, and the decoding information of the instruction will exist in the register; when the instruction is an illegal instruction, the register will be cleared, so that the decoding information of the instruction does not exist in the register; therefore, the embodiment of the present application can use the exception handling function to determine whether there is decoding information of the instruction in the register, so as to confirm whether the unsupported instruction that triggers the illegal instruction exception encountered by the processor is an extended instruction or an illegal instruction.

[0145] As an optional implementation, the opcode in the machine code can define the operation type of the instruction, thereby indicating how the instruction is implemented. Further, the embodiment of the present application can use the exception handling function to determine whether there is a value in the machine code register, so as to determine whether there is decoding information of the instruction in the register.

[0146] Step S813, determining that the instruction is an extended instruction among unsupported instructions, performing software simulation execution on the instruction based on the decoding information of the instruction, and obtaining a software simulation execution result as the execution result of the instruction.

[0147] If it is judged that there is decoding information of the instruction in the register (for example, it is judged that there is a value in the machine code register, that is, it is judged that there is valid machine code in the machine code register), the exception handling function can determine that the unsupported instruction that triggers the illegal instruction exception is an extended instruction; for extended instructions, the exception handling function can perform software simulation execution of the instruction through software simulation based on the decoding information of the instruction that the processor has decoded and identified in the decoding stage, thereby obtaining the software simulation execution result of the instruction as the execution result of the instruction.

[0148] That is to say, in the case of extended instructions, the decoding information of the instruction already exists in the register, for example, the machine code register has saved the machine code of the instruction, the destination operand register has saved the destination operand of the instruction, the source operand register has saved the source operand of the instruction, and the modifier register has saved the modifier of the instruction. The decoding information of the instruction saved in these registers can be reused by the exception handling function, so as to perform software simulation execution on the instruction in a software simulation manner to obtain the execution result of the software simulation, and then the execution result of the software simulation can be used as the execution result of the instruction.

[0149] In an optional implementation, the software simulation referred to in the embodiment of the present application refers to simulating instruction operations through a combination of basic instructions, that is, for extended instructions, the operation of extended instructions can be implemented through a combination of multiple basic instructions. Specifically, although the extended instruction does not have a corresponding execution unit in the processor and cannot be directly executed by the processor, the operation of the extended instruction can be implemented by combining the basic instructions through software simulation using existing basic instructions (such as multiplication, addition, shift, integer operations, etc.), that is, when the processor hardware does not support the extended instruction, the software simulation conversion processing method is adopted.

[0150] For example, taking the MAD (Multiply Add) instruction as an example, it can be a combination of multiplication and addition operations. If the processor can decode and identify the MAD instruction, but there is no execution unit that supports the MAD instruction (for example, there is no dedicated multiplication and addition unit in the processor), the MAD instruction can be implemented by software simulation of a combination of basic multiplication instructions and addition instructions. For example, taking the four floating-point arithmetic operations (addition, subtraction, multiplication, and division) as an example, if the processor can decode and identify the operation instructions of the four floating-point arithmetic operations, but there is no corresponding execution unit, the operation instructions of the four floating-point arithmetic operations (addition, subtraction, multiplication, and division) can be simulated by converting them into integer operations. For example, the floating-point addition in the four floating-point arithmetic operations can be simulated using a combination of integer addition instructions and shift, rounding and other instructions, where shift, rounding and other instructions can process the mantissa and exponent part of the floating-point number.

[0151] In an optional implementation, an embodiment of the present application can determine the operation type of the instruction based on the decoding information of the instruction, and thus determine the instruction implementation program according to the operation type of the instruction. The instruction implementation program may include a combination of basic instructions corresponding to the operation type of the instruction, so that the instruction implementation program implements the software simulation process. The specific introduction and examples of the instruction implementation program combining basic instructions can be referred to the previous description and will not be expanded here; further, based on the combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction, an operation is performed on the operation information of the instruction to obtain the execution result of the software simulation as the execution result of the instruction.

[0152] Specifically, the operation type of the instruction can be indicated by the operation code of the instruction, and the operation code of the instruction can be regarded as a part of the machine code, so that the operation code of the instruction can be read from the machine code register; the operation information of the instruction can include the source operand, modifier and other information of the instruction, wherein the source operand of the instruction can be read from the source operand register, and the modifier of the instruction can be read from the modifier register. Thus, when the embodiment of the present application uses the exception handling function to confirm that there is a value in the machine code register, the operation code of the instruction in the machine code register can be read, and based on the operation code of the instruction, the instruction implementation program corresponding to the operation type indicated by the operation code is selected; further, the source operand of the instruction in the source operand register and the modifier of the instruction in the modifier register are read by the instruction implementation program, and the operation information such as the source operand and modifier of the instruction are performed with the combination of the basic instructions included in the instruction implementation program to obtain the execution result of the software simulation; further, the embodiment of the present application can also read the destination operand of the instruction in the destination operand register by using the instruction implementation program, and write the execution result of the software simulation into the destination operand, so as to realize that the execution result of the software simulation is used as the execution result of the instruction.

[0153] Step S814: restore the saved status of the registers related to the illegal instruction exception, and exit the exception handling function.

[0154] After the extended instruction is processed in a software simulation manner and the execution result of the instruction is obtained, the embodiment of the present application can use the exception handling function to restore the scene, that is, to restore the state of the register saved in step S811, so that the processor can return to the state when the illegal instruction exception occurs. In an optional implementation, the exception handling function can restore the state of registers such as the value of the register and the value of the program counter, so that the processor can continue to execute the application from the location where the exception occurs, instead of executing the next instruction in the exception handling program.

[0155] That is to say, the protection scene saves the register state corresponding to the application when the illegal instruction exception occurs, and the recovery scene restores the register state to the register to ensure that the application continues to execute. For example, after the exception handling function exits, the processor (specifically, it can be the processor core in the processor) can continue to fetch, decode, execute and other pipeline stages for the next instruction of the application.

[0156] Furthermore, after using the exception handling function to restore the scene, the exception handling function can be exited, so that the processor jumps back to the code location when the exception occurred to continue execution. For example, after restoring the value of the program counter, the value restored by the program counter is the instruction address (that is, the return address) of the processor when the illegal instruction exception occurred. Therefore, the value of the program counter can be used to jump back to the instruction address of the processor when the illegal instruction exception occurred, and the execution of the application program can be continued.

[0157] It can be seen that for extended instructions, the processor decodes and parses the extended instructions in advance. For example, an extended instruction decoding unit can be set in the decoding stage to decode and parse the extended instructions, so that the decoding information of the extended instructions is saved in advance in the processor; further, the exception handling function can reuse the decoding information of the extended instructions saved in the processor to implement software simulation of the extended instructions. Therefore, software simulation can avoid the process of re-acquiring instructions from the memory and performing software decoding, reducing the delay of memory access and software decoding, and improving the processing efficiency of the extended instructions as unsupported instructions of the processor. It should be noted that if the decoding information of the extended instructions is not saved in advance in the processor, the exception handling function needs to re-acquire the instructions from the memory for software decoding before performing software simulation execution on the extended instructions, and then can perform software simulation execution based on the result of software decoding. Therefore, the embodiment of the present application can reduce the delay of memory access and software decoding of the exception handling function when processing extended instructions.

[0158] That is to say, if the instruction is an extended instruction in an unsupported instruction, the processor can decode the instruction, obtain the decoding information of the instruction, and save the decoding information of the instruction to the corresponding register; then trigger the illegal instruction exception, so that the exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoding information of the instruction to obtain the execution result of the instruction. That is, the embodiment of the present application optimizes the processing method of the extended instruction as an unsupported instruction by combining the processor hardware decoding of the extended instruction in advance with the software simulation of the exception handling function, and can improve the processing efficiency of the extended instruction as an unsupported instruction; at the same time, it avoids adding a coprocessor to participate in the processing of unsupported instructions, reducing hardware complexity and hardware cost; therefore, the embodiment of the present application can improve the processing efficiency of the extended instruction as an unsupported instruction, and reduce hardware cost, so as to achieve efficient processing of unsupported instructions and control hardware cost.

[0159] Step S815: determine that the instruction is an illegal instruction among unsupported instructions, report an illegal instruction exception to the application program, or read the instruction from the memory, perform software decoding on the instruction and then perform software simulation execution.

[0160] If it is determined that there is no decoding information of the instruction in the register (for example, it is determined that there is no value in the machine code register), the embodiment of the present application can determine that the unsupported instruction that triggers the illegal instruction exception is an illegal instruction, that is, the current instruction of the processor is an illegal instruction among the unsupported instructions. In the case where the instruction is an illegal instruction, the exception handling function can have two processing methods:

[0161] 1. Report illegal instruction exceptions to the application so that users can handle them later;

[0162] 2. Read instructions from the memory, perform software decoding on the instructions, and then perform software simulation execution; for example, the exception handling function can obtain the address of the instruction (an illegal instruction in this case) from the instruction pointer register, read the instruction from the memory based on the address of the instruction, and then parse the operation code and operand of the instruction through basic operation instructions in a software decoding manner; thereby, according to the operation code of the instruction, select an instruction implementation program corresponding to the operation type indicated by the operation code, use a combination of basic instructions included in the instruction implementation program, perform operations on the operation information such as the operands of the instruction (such as source operands), and obtain a software simulated execution result as the execution result of the instruction.

[0163] That is to say, compared with the extended instruction case, the second processing method in the above illegal instruction case has the additional process of re-reading the instruction from the memory and performing software decoding. This is because the register of the illegal instruction needs to be cleared.

[0164] It should be noted that the decoding of the processor at the decoding stage (such as the decoding of the decoder) refers to the decoding process at the hardware level. For example, the decoder parses the meaning of the instruction through the opcode and operand of the instruction, and then generates the corresponding control signal to drive the hardware execution. Software decoding refers to the use of software programs to decode and parse instructions when the processor hardware cannot directly identify illegal instructions, rather than relying on dedicated hardware decoding units; specifically, software decoding can extract key information (such as opcodes, operands, etc.) in the instruction by executing some basic operation instructions (such as addition, displacement, etc.) without modifying the hardware structure or adding dedicated hardware decoding units.

[0165] Furthermore, after processing the second processing method in the above-mentioned illegal instruction situation, it is necessary to restore the status of the saved registers related to the illegal instruction exception and exit the exception handling function so that the processor returns to the instruction address when the illegal instruction exception occurs and continues the execution of the application.

[0166] The embodiment of the present application is optimized for the situation that the instruction is an extended instruction, and the extended instruction is decoded in advance by the processor hardware, so that the exception handling function needs to obtain the instruction and the process of software decoding from the internal memory, so that the extended instruction is accelerated in the processing process of the exception handling function, not only reducing the memory access, but also improving the efficiency of the processor in processing the extended instruction, reducing delay. Meanwhile, compared to increasing a special coprocessor, the embodiment of the present application utilizes the processor hardware to the early decoding (i.e. decoding) of the extended instruction and the flexible implementation of the software simulation of the exception handling function, avoiding the problem of high cost, high hardware complexity and low flexibility of processing the unsupported instruction. Therefore, the embodiment of the present application is through the combination of processor hardware and system software (specifically the exception handling function in the system software), while ensuring flexibility, improving the processing efficiency of the extended instruction as the unsupported instruction, and reducing hardware cost and complexity, and can adapt to different architectures and instruction sets.

[0167] The following is an introduction to the instruction processing device provided in the embodiment of the present application, and the following description can be referenced to the above description.

[0168] As an optional implementation, the embodiment of the present application provides an instruction processing device from the perspective of processor hardware. Fig.9A The block diagram of the instruction processing device provided by the embodiment of the present application is exemplarily shown. The instruction processing device can be applied to a processor and can be regarded as a hardware logic device in the processor. Fig.9A , the instruction processing device may include:

[0169] The instruction fetch module 910 is used to fetch instructions of the application program;

[0170] The decoding module 911 is used to determine whether the instruction is a supported instruction of the processor; if the instruction is an unsupported instruction of the processor, determine the type of the instruction in the unsupported instructions; if the instruction is an extended instruction in the unsupported instructions, decode the instruction to obtain the decoding information of the instruction, and save the decoding information of the instruction to the corresponding register; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute;

[0171] The exception handling unit 912 is used to trigger an illegal instruction exception based on the fact that the instruction is an unsupported instruction of the processor, so that the exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

[0172] In an optional implementation, the decoding module 911 is further used for:

[0173] If the instruction is an illegal instruction among the unsupported instructions, the corresponding register is cleared; wherein the illegal instruction is an instruction that the processor cannot decode, identify and execute.

[0174] In an optional implementation, combined with Fig.9A As shown, an extended instruction decoding unit 9111 can be set in the decoding module 911, and the extended instruction decoding unit is a logic unit set by the decoding module for parsing and identifying extended instructions; wherein, the extended instruction decoding unit 9111 is specifically used to decode the instruction if the instruction is an extended instruction in the unsupported instruction, so as to obtain the decoding information of the instruction.

[0175] In an optional implementation, the decoding module 911 is further configured to generate an illegal instruction exception signal based on the fact that the instruction is an unsupported instruction of the processor, and transmit the signal to the exception handling unit 912 .

[0176] The exception handling unit 912 is configured to trigger an illegal instruction exception based on the instruction being an unsupported instruction of the processor, including:

[0177] Get illegal instruction exception signal;

[0178] Based on the illegal instruction exception signal, jump to the exception handling function corresponding to the illegal instruction exception.

[0179] In an optional implementation, the extended instruction and the illegal instruction may share the illegal instruction exception signal to indicate that the processor exception type is an illegal instruction exception.

[0180] In an optional implementation, the exception handling unit 912 is configured to jump to an exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception signal, including:

[0181] Parsing the illegal instruction exception signal and determining the illegal instruction exception vector number, wherein the illegal instruction exception vector number is used to uniquely identify the processor exception type as an illegal instruction exception;

[0182] Based on the illegal instruction exception vector number, determining an entry address of an exception handling function corresponding to the illegal instruction exception;

[0183] Based on the entry address, jump to the exception handling function corresponding to the illegal instruction exception.

[0184] In an optional implementation, the exception handling unit 912 is configured to determine the entry address of the exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception vector number, including:

[0185] In the interrupt vector data structure, the entry address of the corresponding exception handling function is searched based on the illegal instruction exception vector number; wherein the interrupt vector data structure records the exception vector numbers of various processor exception types and the corresponding relationship between the entry address of the exception handling function, and the illegal instruction exception belongs to a processor exception type.

[0186] In an optional implementation, the exception handling unit 912 is also used to save the return address of the processor before jumping to the exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception signal, and the return address is: the address to which the processor returns to continue execution after the illegal instruction exception is processed by the exception handling function.

[0187] In an optional implementation, the decoding module 911 is used to determine whether the instruction is a supported instruction of the processor, including: determining whether the instruction belongs to the instruction set of the processor, if so, the instruction is a supported instruction of the processor, if not, the instruction is an unsupported instruction of the processor, and the instruction set defines supported instructions of the processor.

[0188] In an optional implementation, the decoding module 911 is used to determine the type of the instruction in the unsupported instructions, including: comparing the opcode of the instruction with the instruction set extension information of the processor, wherein the instruction set extension information defines instructions with additional extensions of the processor; if the opcode of the instruction is recorded in the instruction set extension information, and the mark of the instruction in the instruction set extension information indicates that the instruction has no corresponding execution unit, then the instruction is confirmed to be an extended instruction; if the opcode of the instruction is not recorded in the instruction set extension information, or if it is checked that the format of the instruction is illegal, then the instruction is confirmed to be an illegal instruction.

[0189] In an optional implementation, the decoding information of the instruction includes: a machine code, a destination operand, a source operand, and a modifier of the instruction; the decoding module 911 is used to save the decoding information of the instruction to a corresponding register, including:

[0190] The machine code of the instruction is saved in a machine code register, the destination operand is saved in a destination operand register, the source operand is saved in a source operand register, and the modifier is saved in a modifier register.

[0191] Furthermore, an embodiment of the present application also provides a processor, including the instruction processing device provided in the above embodiment of the present application.

[0192] As an optional implementation, the embodiment of the present application provides an instruction processing device from the perspective of system software. Fig. 9B Another block diagram of the instruction processing device provided in an embodiment of the present application is exemplarily shown. The instruction processing device can be applied to system software and can be regarded as a software function device in the system software.

[0193] Reference Fig. 9B , the instruction processing device may include:

[0194] A calling entry module 920 is used to call an exception handling function corresponding to an illegal instruction exception, wherein the exception handling function is deployed in the system software, and the exception handling function is used to handle an illegal instruction exception triggered by an instruction of the application program that is not supported by the processor;

[0195] The exception handling function module 921 is used to determine whether the register contains the decoding information of the instruction; if the register contains the decoding information of the instruction, it is determined that the instruction is an extended instruction in the unsupported instruction, and based on the decoding information of the instruction, the instruction is executed by software simulation to obtain the execution result of the software simulation as the execution result of the instruction; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute.

[0196] In an optional implementation, the software simulation simulates instruction operations by combining basic instructions; the exception handling function module 921 is used to perform software simulation execution on the instruction based on the decoding information of the instruction to obtain the execution result of the software simulation, which includes:

[0197] Determining an operation type of the instruction based on the decoding information of the instruction;

[0198] Determining an instruction implementation program according to the operation type of the instruction, wherein the instruction implementation program includes a combination of basic instructions corresponding to the operation type of the instruction;

[0199] Based on the combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction, an operation is performed on the operation information of the instruction to obtain a software simulated execution result as the execution result of the instruction.

[0200] In an optional implementation, the exception handling function module 921 is used to determine the operation type of the instruction based on the decoding information of the instruction, including: reading the operation code of the instruction in the machine code register;

[0201] The exception handling function module 921 is used to determine the instruction implementation program according to the operation type of the instruction, including: based on the operation code of the instruction, selecting the instruction implementation program corresponding to the operation type indicated by the operation code;

[0202] The exception handling function module 921 is used to perform operations on the operation information of the instruction based on the combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction, and obtain the execution result of the software simulation, which includes: using the instruction implementation program to read the source operand of the instruction in the source operand register and the modifier of the instruction in the modifier register; using the combination of basic instructions included in the instruction implementation program to perform operations on the source operand and modifier of the instruction to obtain the execution result of the software simulation as the execution result of the instruction.

[0203] In an optional implementation, the exception handling function module 921 is also used to use the instruction implementation program to read the destination operand of the instruction in the destination operand register; wherein the execution result of the software simulation is written into the destination operand as the execution result of the instruction.

[0204] In an optional implementation, the exception handling function module 921 is also used to use the exception handling function to save the state of the register related to the illegal instruction exception before using the exception handling function to determine whether the register contains the decoding information of the instruction; after obtaining the execution result of the software simulation as the execution result of the instruction, the saved state of the register related to the illegal instruction exception is restored, and the exception handling function is exited, so that the processor returns to the state when the illegal instruction exception occurs.

[0205] In an optional implementation, the exception handling function module 921 is also used to determine that the instruction is an illegal instruction among unsupported instructions if the register does not contain decoding information of the instruction, and report the illegal instruction exception to the application, or read the instruction from the memory, perform software decoding on the instruction and then perform software simulation execution; wherein the illegal instruction is an instruction that the processor cannot decode, identify and execute.

[0206] In an optional implementation, the exception handling function module 921 is used to determine whether the register contains the decoding information of the instruction, including: determining whether the machine code register contains a value.

[0207] Furthermore, an embodiment of the present application also provides a computer device, such as a terminal device or a server device, comprising a memory and a processor, the memory storing computer system instructions (such as instructions in system software), and the processor calling the computer system instructions to execute the instruction processing method on the system software side provided in the embodiment of the present application.

[0208] Furthermore, an embodiment of the present application also provides a storage medium, which stores computer system instructions (such as instructions in system software). When the computer system instructions are executed (such as when executed by a processor), the instruction processing method on the system software side provided in the embodiment of the present application is implemented.

[0209] Furthermore, an embodiment of the present application also provides a computer system program, including computer system instructions (such as instructions in system software). When the computer system instructions are executed (such as when executed by a processor), the instruction processing method on the system software side provided in the embodiment of the present application is implemented.

[0210] Furthermore, an embodiment of the present application also provides a computer device, such as a terminal device or a server device, including a processor and system software of the computer device, wherein the processor is a processor as provided above in the embodiment of the present application, and the system software of the computer device includes an instruction processing device on the system software side provided in the embodiment of the present application.

[0211] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0212] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A command processing method, characterized in that: Applied to a processor, the method comprises: Get instructions for the application; Determining whether the instruction is a supported instruction of the processor; If the instruction is an unsupported instruction of the processor, determining the type of the instruction among the unsupported instructions; If the instruction is an extended instruction among the unsupported instructions, the instruction is decoded to obtain the decoding information of the instruction, and the decoding information of the instruction is saved to a corresponding register; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute; And, based on the fact that the instruction is an unsupported instruction of the processor, an illegal instruction exception is triggered, so that an exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

2. The method according to claim 1, characterized in that: The method further comprises: If the instruction is an illegal instruction among the unsupported instructions, the corresponding register is cleared; wherein the illegal instruction is an instruction that the processor cannot decode, identify and execute.

3. The method according to claim 1, characterized in that If the instruction is an extended instruction in an unsupported instruction, the instruction is decoded, and the decoding information of the instruction obtained includes: If the instruction is an extended instruction among the unsupported instructions, the instruction is decoded using an extended instruction decoding unit set in the decoding module of the processor to obtain decoding information of the instruction; wherein the extended instruction decoding unit is a logic unit set in the decoding module of the processor for parsing and identifying extended instructions.

4. The method according to claim 2, characterized in that: The triggering of the illegal instruction exception based on the instruction being an unsupported instruction of the processor includes: Based on the fact that the instruction is an unsupported instruction of the processor, an illegal instruction exception signal is obtained; wherein the extended instruction and the illegal instruction share the illegal instruction exception signal to indicate that the processor exception type is an illegal instruction exception; Based on the illegal instruction exception signal, jump to the exception handling function corresponding to the illegal instruction exception.

5. The method according to claim 4, characterized in that The step of jumping to an exception handling function corresponding to an illegal instruction exception based on the illegal instruction exception signal comprises: Parsing the illegal instruction exception signal and determining the illegal instruction exception vector number, wherein the illegal instruction exception vector number is used to uniquely identify the processor exception type as an illegal instruction exception; Based on the illegal instruction exception vector number, determining an entry address of an exception handling function corresponding to the illegal instruction exception; Based on the entry address, jump to the exception handling function corresponding to the illegal instruction exception.

6. The method according to claim 5, characterized in that Determining the entry address of the exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception vector number includes: In the interrupt vector data structure, the entry address of the corresponding exception handling function is searched based on the illegal instruction exception vector number; wherein the interrupt vector data structure records the exception vector numbers of various processor exception types and the corresponding relationship between the entry address of the exception handling function, and the illegal instruction exception belongs to a processor exception type.

7. The method according to claim 4, characterized in that Before jumping to an exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception signal, the method further includes: The return address of the processor is saved, where the return address is the address to which the processor returns to continue execution after the illegal instruction exception is processed by the exception handling function.

8. The method according to claim 2, characterized in that: The step of determining whether the instruction is a supported instruction of the processor comprises: Determine whether the instruction belongs to the instruction set of the processor, if so, the instruction is a supported instruction of the processor, if not, the instruction is an unsupported instruction of the processor, and the instruction set defines supported instructions of the processor; Determining the type of the instruction among the unsupported instructions comprises: Comparing the operation code of the instruction with instruction set extension information of the processor, wherein the instruction set extension information defines instructions additionally extended by the processor; If the operation code of the instruction is recorded in the instruction set extension information, and the mark of the instruction in the instruction set extension information indicates that the instruction has no corresponding execution unit, then confirming that the instruction is an extended instruction; If the operation code of the instruction is not recorded in the instruction set extension information, or if the format of the instruction is found to be illegal, the instruction is confirmed to be an illegal instruction.

9. The method according to claim 1, characterized in that: The decoding information of the instruction includes: the machine code, destination operand, source operand and modifier of the instruction; Saving the decoding information of the instruction to the corresponding register includes: The machine code of the instruction is saved in a machine code register, the destination operand is saved in a destination operand register, the source operand is saved in a source operand register, and the modifier is saved in a modifier register.

10. A command processing method, characterized in that: Applied to system software, wherein the processor runs the system software through the kernel space; the method comprises: Calling an exception handling function corresponding to an illegal instruction exception, wherein the exception handling function is deployed in the system software, and the exception handling function is used to handle an illegal instruction exception triggered by an instruction of the application program being an instruction not supported by the processor; Using the exception handling function to determine whether the register contains the decoding information of the instruction; If the register contains decoding information of the instruction, it is determined that the instruction is an extended instruction among unsupported instructions, and based on the decoding information of the instruction, the instruction is executed by software simulation to obtain a software simulation execution result as the execution result of the instruction; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute.

11. The method according to claim 10, characterized in that The software simulation simulates instruction operations by combining basic instructions; the software simulation execution of the instructions is performed based on the decoding information of the instructions to obtain the execution results of the software simulation, which include: Determining an operation type of the instruction based on the decoding information of the instruction; Determining an instruction implementation program according to the operation type of the instruction, wherein the instruction implementation program includes a combination of basic instructions corresponding to the operation type of the instruction; Based on the combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction, an operation is performed on the operation information of the instruction to obtain a software simulated execution result as the execution result of the instruction.

12. The method according to claim 11, characterized in that Determining the operation type of the instruction based on the decoding information of the instruction includes: Read the opcode of the instruction described in the machine code register; Determining the instruction implementation program according to the operation type of the instruction includes: Based on the operation code of the instruction, selecting an instruction implementation program corresponding to the operation type indicated by the operation code; The combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction are used to perform operations on the operation information of the instruction to obtain the execution result of the software simulation, which includes: Using the instruction to implement the program to read the source operand of the instruction in the source operand register and the modifier of the instruction in the modifier register; The instruction implementation program includes a combination of basic instructions, performs operations on source operands and modifiers of the instructions, and obtains a software simulated execution result as the execution result of the instruction.

13. The method according to claim 12, characterized in that Also includes: Using the instruction to implement the program to read the destination operand of the instruction in the destination operand register; The execution result of the software simulation is written into the destination operand as the execution result of the instruction.

14. The method according to claim 10, characterized in that Before using the exception handling function to determine whether the register contains the decoding information of the instruction, the method further includes: Use the exception handling function to save the state of the registers related to the illegal instruction exception; After obtaining the execution result of the software simulation as the execution result of the instruction, the method further includes: The saved state of the registers related to the illegal instruction exception is restored, and the exception handling function is exited so that the processor returns to the state when the illegal instruction exception occurs.

15. The method according to claim 10, characterized in that The method further comprises: If the register does not contain decoding information of the instruction, the instruction is determined to be an illegal instruction among unsupported instructions, and the illegal instruction exception is reported to the application, or the instruction is read from the memory, software-decoded and then executed in software simulation; wherein the illegal instruction is an instruction that the processor cannot decode, identify and execute.

16. An instruction processing device, characterized in that: Applied to a processor, the instruction processing device comprises: Instruction fetch module, used to fetch instructions from application programs; A decoding module, used to determine whether the instruction is a supported instruction of the processor; if the instruction is an unsupported instruction of the processor, determine the type of the instruction in the unsupported instructions; if the instruction is an extended instruction in the unsupported instructions, decode the instruction to obtain the decoding information of the instruction, and save the decoding information of the instruction to a corresponding register; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute; The exception handling unit is used to trigger an illegal instruction exception based on the fact that the instruction is an unsupported instruction of the processor, so that the exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

17. An instruction processing device, characterized in that: Applied to system software, wherein the processor runs the system software through the kernel space; the instruction processing device includes: A calling entry module is used to call an exception handling function corresponding to an illegal instruction exception, wherein the exception handling function is deployed in the system software, and the exception handling function is used to handle an illegal instruction exception triggered by an instruction of the application program that is not supported by the processor; The exception handling function module is used to determine whether the register has the decoding information of the instruction; if the register has the decoding information of the instruction, it is determined that the instruction is an extended instruction in the unsupported instruction, and based on the decoding information of the instruction, the instruction is executed by software simulation to obtain the execution result of the software simulation as the execution result of the instruction; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute.

18. A processor, characterized in that: Comprising the instruction processing device as claimed in claim 16.

19. A computer device, characterized in that: It comprises a memory and a processor, wherein the memory stores computer system instructions, and the processor calls the computer system instructions to execute the instruction processing method according to any one of claims 10-15.

20. A storage medium, characterized in that: The storage medium stores computer system instructions, and when the computer system instructions are executed, the instruction processing method according to any one of claims 10 to 15 is implemented.

21. A computer system program, characterized in that: It comprises computer system instructions, and when the computer system instructions are executed, the instruction processing method according to any one of claims 10 to 15 is implemented.

22. A computer device, characterized in that: A system software comprising a processor and a computer device; the processor is the processor as claimed in claim 18, and the system software comprises the instruction processing device as claimed in claim 17.

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