Inter-chip communication system and method

Abstract

The invention discloses an inter-chip communication system and method, the system comprises a plurality of connection nodes and a switching structure, each connection node is connected to the switching structure, for any connection node, the connection node comprises a calculation chip and a connection module, the calculation chip is used for generating to-be-transmitted data according to a calculation task, and the to-be-transmitted data is transmitted to the switching structure. The connection module is used for determining a target connection node of the to-be-transmitted data and transmitting the to-be-transmitted data to the target connection node through the switching structure, and the connection module is further used for receiving the to-be-transmitted data transmitted by other connection nodes and transmitting the to-be-transmitted data to the connection module through the switching structure. And transmitting the data to be transmitted to the computing chips, and realizing high-speed connection communication of multiple computing chips by utilizing a uniform communication link formed by the connection nodes.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an inter-chip communication system and method. Background Art

[0002] The development of large AI models depends on the continuous improvement of computing power. Increasing the model scale and the amount of training data are key ways to directly improve the intelligence level and performance of large AI models. However, correspondingly, the demand for cluster computing power is also showing an exponential growth trend.

[0003] However, there are some obvious constraints in improving cluster computing power, such as mask limitation, which limits the performance improvement of single chip, and frequent communication and limited data volume of single communication under model parallel architecture, which limits the utilization of computing power. Therefore, the interconnection between computing chips has become an effective way to improve the computing power of the system that needs to be developed urgently.

[0004] The high-speed inter-chip interconnection of computing chips is different from the traditional model of parallel computing process in which computing chips are allocated to each computing node and the computing nodes are connected through the Internet architecture for communication. It aims to connect several computing chips within a single computing node to form a computing structure with stronger computing power.

[0005] For high-speed inter-chip interconnection, domestic technical personnel usually use direct connection between computing chips for inter-chip interconnection. However, the direct connection of computing chips is limited by the bandwidth of a single line, and it is difficult to achieve a larger interconnection scale (the interconnection scale of direct connection of computing chips usually does not exceed 8).

[0006] Therefore, the present invention provides an inter-chip communication system and method. Summary of the invention

[0007] This specification provides an inter-chip communication system and method to partially solve the above-mentioned problems existing in the prior art.

[0008] This manual adopts the following technical solutions:

[0009] This specification provides an inter-chip communication system, the system comprising:

[0010] A plurality of connection nodes and a switching structure, each connection node being connected to the switching structure;

[0011] For any connection node, the connection node includes a computing chip and a connection module;

[0012] The computing chip is used to generate data to be transmitted according to the computing task, and transmit the data to be transmitted to the connection module;

[0013] The connection module is used to determine the target connection node of the data to be transmitted, and transmit the data to be transmitted to the target connection node through the switching structure;

[0014] The connection module is also used to receive data to be transmitted transmitted by other connection nodes, and transmit the data to be transmitted to the computing chip.

[0015] Optionally, the connection module is specifically used to encapsulate the data to be transmitted into a plurality of data frames to be transmitted, and transmit the data frames to be transmitted to the target connection node through the switching structure.

[0016] Optionally, the switching structure specifically includes: a number of switching nodes equal to the number of connection nodes, each switching node is connected to form a two-dimensional grid structure, each connection node is directly connected to a switching node, and the switching nodes directly connected to each connection node are different.

[0017] Optionally, the connection module is specifically used to encapsulate the data to be transmitted into a plurality of data frames to be transmitted containing sorting information, and transmit the data to be transmitted to the target connection node through the switching structure, wherein the data in each data frame to be transmitted is combined according to the sorting information to represent the complete data to be transmitted;

[0018] The connection module specifically includes: a data buffer, the data buffer being used to store data to be transmitted by the switching structure;

[0019] The connection module is specifically used to determine whether the transmission of any data frame to be transmitted is out of order based on the sorting information in the data frame to be transmitted and the historical sorting information when receiving the data frame to be transmitted; when the transmission of the data to be transmitted is out of order, the data frame to be transmitted is stored in a data buffer until a delayed data frame to be transmitted that can be sequentially combined with the data frame to be transmitted is received; the data frame to be transmitted and the delayed data frame to be transmitted are combined in order according to their respective sorting information, and then transmitted to the computing chip.

[0020] Optionally, the connection module is specifically used to determine the target connection node of the data to be transmitted, and transmit the data to be transmitted including the address information of the target connection node to the switching node directly connected to the connection module;

[0021] The switching node is used to determine the target switching node according to the address information in the data to be transmitted when receiving the data to be transmitted, and if the current switching node is the target switching node, transmit the received data to be transmitted to the directly connected connection module; otherwise, determine the target path according to the target switching node and the communication load of each switching node in the switching structure, and transmit the data to be transmitted to the next switching node according to the target path.

[0022] Optionally, the connection module is specifically used to generate and add a corresponding check code for each data frame to be transmitted using a cyclic redundancy check function;

[0023] The switching node is specifically configured to, when receiving a data frame to be transmitted, determine the availability of the data frame to be transmitted according to a check code in the data frame to be transmitted, and transmit the available data frame to be transmitted to the next switching node or a directly connected connection module;

[0024] The connection module is specifically configured to, when receiving a data frame to be transmitted, determine the availability of the data frame to be transmitted according to a check code in the data frame to be transmitted, and transmit the available data frame to be transmitted to the computing chip.

[0025] Optionally, the connection module is specifically used to encapsulate the data to be transmitted into data frames to be transmitted, and for any data frame to be transmitted, the data frame to be transmitted includes original content and redundant content, the original content is the content in the data to be transmitted, and the redundant content is the forward error correction code generated according to the original content;

[0026] The switching node is specifically configured to, when receiving a data frame to be transmitted, verify the original content in the data frame to be transmitted according to the redundant content in the data frame to be transmitted, and when the verification succeeds, transmit the data frame to be transmitted to the next switching node or a directly connected connection module, and when the verification fails, restore the original content according to the redundant content, and transmit the restored data frame to be transmitted to the next switching node or a directly connected connection module;

[0027] The connection module is further used to verify the original content in the data frame to be transmitted according to the redundant content in the data frame to be transmitted when receiving the data frame to be transmitted, and restore the original content according to the redundant content when the verification fails.

[0028] Optionally, the connection module is specifically used to determine the amount of data that can be received by the target connection node, and if the amount of data that can be received is not less than the amount of data to be transmitted, transmit the data to be transmitted to the target connection node through the switching structure, and update the amount of data that can be received by the target connection node;

[0029] The connection module is further used to update the amount of receivable data of the connection node to which the current connection module belongs after receiving the data to be transmitted transmitted by other connection nodes and transmitting the data to be transmitted to the computing chip.

[0030] Optionally, the connection module is specifically used to: for any data frame to be transmitted, cut the data frame to be transmitted into flow control units of equal length according to a preset length threshold, and transmit each flow control unit to the target connection node through the switching structure.

[0031] Optionally, the connection module is further used to transmit a flow control unit containing clock information to each other connection node through the switching structure at a preset time interval when there is no data to be transmitted.

[0032] Optionally, the switch nodes are connected using SerDes technology.

[0033] This specification provides a method for inter-chip communication, the method is applied to an inter-chip communication system, the inter-chip communication system includes: a plurality of connection nodes, each connection node is connected to each other;

[0034] For any connection node, the method includes:

[0035] Using the computing chip in the connection node, according to the computing task, to generate data to be transmitted, and transmitting the data to be transmitted to the connection module in the connection node;

[0036] Using the connection module, determining a target connection node for the data to be transmitted, and transmitting the data to be transmitted to the target connection node;

[0037] When receiving data to be transmitted transmitted by other connection nodes, the connection module is used to receive the data to be transmitted, and the data to be transmitted is transmitted to the computing chip.

[0038] This specification provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned inter-chip communication method is implemented.

[0039] This specification provides a device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned inter-chip communication method when executing the program.

[0040] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0041] In the inter-chip communication system of this specification, a unified communication link formed by each connection node can be used to achieve high-speed connection and communication of multiple computing chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

[0043] Figure 1 A schematic diagram of the structure of an inter-chip communication system in this specification;

[0044] Figure 2 A schematic diagram of the structure of an inter-chip communication system including a switching node in this specification;

[0045] Figure 3 A schematic diagram of a flow chart of a method for inter-chip communication in this specification;

[0046] Figure 4 The corresponding Figure 3 Schematic diagram of electronic equipment. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0049] High-speed inter-chip interconnection is to solve the contradiction between the serious mismatch between the computing power demand of large applications and the computing power supply of single chips. The method provided in this specification proposes the concept of "one logic crossbar" for high-speed inter-chip interconnection. This concept aims to shield the differences in latency, bandwidth, reliability, etc. between chips and on chips through high-speed inter-chip interconnection, while ensuring that the programming model of the computing power chip remains unchanged. On the other hand, this concept aims to overcome the problems existing in the existing technology, so that the inter-chip communication system built has the ability to smoothly increase the system scale as the application scale increases.

[0050] Specifically, Figure 1 This is a structural diagram of an inter-chip communication system in this specification. The inter-chip communication system specifically includes a number of connection nodes and a switching structure. Each connection node is connected to the switching structure. For any connection node, the connection node includes a computing chip and a connection module.

[0051] Among them, each connection node is physically connected to the switching structure through a signal line; the computing chip in a connection node and the connection module can also be physically connected through a signal line; the computing chip mentioned in this specification can be a commonly used computing power chip such as a GPU chip or a CPU chip; the connection module may include a network adapter or a bus converter to provide routing guidance for communication between connection nodes; the switching structure can be composed of switching nodes, and each switching node is a physical device with routing selection and de-framing and sealing functions.

[0052] In this inter-chip communication system, according to the aforementioned "one logic crossbar" concept, the complexity and cost of implementing the switching structure are reduced, and each connection node can use the connection module in its own connection node to determine its own target connection node, and complete the communication through the switching structure shared by each connection node. As a result, each connection node does not need to establish a direct connection between each other, and the bandwidth of the shared switching structure can be much higher than the bandwidth when the connection nodes are directly connected to each other, thereby increasing the available bandwidth of a single connection node and reducing the delay in communication between connection nodes. When expanding the inter-chip communication system, it is only necessary to connect the connection node to be added that also has a computing chip and a connection module to the shared switching structure.

[0053] The computing chip is used to generate data to be transmitted according to a computing task, and transmit the data to be transmitted to the connection module.

[0054] When data is transmitted between connection nodes, the connection node serving as the output party first uses the computing chip in the connection node to generate data to be transmitted according to the computing task, and at the same time, adds the transmission information of the target connection node serving as the recipient of the data to be transmitted to the data to be transmitted, and then transmits the data to be transmitted to the connection module in the connection node serving as the output party.

[0055] The recipient of the data to be transmitted may be determined according to the computing task.

[0056] The connection module is used to determine a target connection node for the data to be transmitted, and transmit the data to be transmitted to the target connection node through the switching structure.

[0057] When the connection module receives the data to be transmitted from the computing chip of the same connection node as the inter-chip interconnection module, it can determine the connection node that serves as the recipient of the data to be transmitted in the inter-chip communication system, that is, the target connection node, based on the transmission information attached to the data to be transmitted, and transmit the data to be transmitted to the target connection node through the switching structure.

[0058] Specifically, the data to be transmitted including the address information of the target connection node may be transmitted to the switching structure, so that the switching structure transmits the data to be transmitted to the target connection node according to the address information.

[0059] In one or more embodiments of the present specification, one piece of data to be transmitted may correspond to several receivers, so the connection module may determine several target connection nodes for the data to be transmitted, and transmit the data to be transmitted to the determined several target connection nodes.

[0060] The connection module is also used to receive data to be transmitted transmitted by other connection nodes, and transmit the data to be transmitted to the computing chip.

[0061] For the target connection node of the receiver, the connection module of the target connection node can receive the data to be transmitted transmitted by other connection nodes, and transmit the data to be transmitted to the computing chip in the receiver.

[0062] like Figure 1 The chip-to-chip communication system shown can complete the communication between each connection node through the connection module built into each connection node and the switching structure connected to each connection node, thereby ensuring the low latency, high bandwidth and high reliability requirements of the communication between each connection node.

[0063] In this chip interconnection system, the complete interconnection protocol is divided into four layers: physical layer, data link layer, transaction layer, and application layer. Among them, each connection node deploys the protocol content of the physical layer, data link layer, transaction layer, and application layer, and the switching structure deploys the protocol content of the physical layer and data link layer. In a communication process, the output side processes the data to be transmitted in the order of application layer-transaction layer-data link layer-physical layer, and the receiving side reversely processes the data to be transmitted in the order of physical layer-data link layer-transaction layer-application layer.

[0064] In one or more embodiments of the present specification, the connection module is specifically configured to encapsulate the data to be transmitted into a plurality of data frames to be transmitted, and transmit the data frames to be transmitted to the target connection node through the switching structure.

[0065] The data frame is a protocol data unit of the data link layer, which mainly consists of three parts: frame header, data part, and frame trailer. The frame header and frame trailer contain some necessary control information, such as synchronization information, address information, error control information, etc. The data part contains the data content to be transmitted. The switching structure and each connection node can support the encapsulation and de-framing of data frames.

[0066] In one or more embodiments of the present specification, a number of switching nodes equal to the number of connecting nodes are connected to form a two-dimensional grid structure, each connecting node is directly connected to a switching node, and the switching nodes directly connected to each connecting node are different.

[0067] The structure of the inter-chip communication system including the switching node is as follows Figure 2 As shown, the switching nodes are connected to each other in a two-dimensional grid structure, each switching node is connected to a different connection node, and the switching nodes are directly connected to the connection nodes through the connection modules in the connection nodes. Therefore, there are multiple communication links of equal length between any two switching nodes in the figure, which provides a variety of routing options for information transmission between the connection nodes, can improve the fault tolerance and load balancing of the inter-chip communication system, and convert a single communication with a longer delay when the connection nodes are directly connected into multiple communications with a shorter delay in the inter-chip communication system, which can meet the experimental requirements when multiple connection nodes communicate with each other.

[0068] In addition, the two-dimensional grid structure can easily expand the network by adding connection nodes without making large-scale modifications to the entire topology architecture. However, in order to ensure that the delay of the inter-chip communication system does not affect the normal communication between the connection nodes, the two-dimensional grid still has a maximum network radius limitation, that is, the expansion capacity of the inter-chip communication system provided in this specification has a maximum value and does not support unlimited expansion.

[0069] Assuming that the delay budget when connecting nodes directly is T, and the delay between two adjacent connecting nodes in the inter-chip communication system is t, the maximum network radius is: Radix = T / t;

[0070] On the other hand, if the connection nodes are connected to form a two-dimensional torus (2D-Torus) structure, the number of connection nodes that can be connected theoretically is: (Radix*2)*(Radix*2).

[0071] For example, the delay of a PCIe switch chip is generally no more than 350ns, and the delay of a single crossbar on a NoC is about 5ns. Based on the above calculation, Radix = 70, and the number of nodes that can be connected is 19,600.

[0072] In one or more embodiments of the present specification, the connection module is specifically used to encapsulate the data to be transmitted into a plurality of data frames to be transmitted containing sorting information, and transmit the data to be transmitted to the target connection node through the switching structure, and the data in each data frame to be transmitted represents the complete data to be transmitted after being combined according to the sorting information; the connection module specifically includes: a data buffer, and the data buffer is used to store the data to be transmitted transmitted by the switching structure; the connection module is specifically used to determine whether the transmission of the data to be transmitted is out of order according to the sorting information in the data frame to be transmitted and the historical sorting information when any data frame to be transmitted is received, and when the transmission of the data to be transmitted is out of order, the data frame to be transmitted is saved in the data buffer until a delayed data frame to be transmitted that can be sequentially combined with the data frame to be transmitted is received, and the data frame to be transmitted and the delayed data frame to be transmitted are combined in order according to their respective sorting information, and then transmitted to the computing chip.

[0073] In the actual data transmission process, a complete set of data will be divided into multiple data frames for batch transmission. Since the availability of the communication link will change over time, the data frames sent before and after may arrive at the target connection node in a disordered manner. The method provided in this manual can support disordered reordering to ensure the stability of communication between the connection nodes.

[0074] Further, according to the above-mentioned "until a delayed data frame to be transmitted is received that can be combined with the sequence of the data frame to be transmitted, the data frame to be transmitted and the delayed data frame to be transmitted are combined in order of their respective sorting information, and then transmitted to the computing chip", the process of the disorderly reordering does not need to wait for the complete reception of the data to be transmitted, and has the characteristics of partial reordering and partial delivery, which can further disperse the transmission pressure and ensure low latency in communication between each connected node.

[0075] The system provided in this specification can realize the function of partial reordering and partial delivery of data frames on each connection module. This function is set in the transaction layer, that is, it only needs to be implemented on the connection node side without having to be implemented in the connection structure.

[0076] In one or more embodiments of the present specification, the connection module is specifically used to determine the target connection node of the data to be transmitted, and transmit the data to be transmitted including the address information of the target connection node to the switching node directly connected to the connection module; the switching node is used to determine the target switching node according to the address information in the data to be transmitted when receiving the data to be transmitted, and if the current switching node is the target switching node, transmit the received data to be transmitted to the directly connected connection module; otherwise, determine the target path according to the target switching node and the communication load of each switching node in the switching structure, and transmit the data to be transmitted to the next switching node according to the target path.

[0077] Specifically, in the process of the connection module transmitting the data to be transmitted to the target connection node, the data to be transmitted is transmitted in the communication link between each switching node, and each switching node can determine the route with the lowest load among the routes to complete the transmission of the data to be transmitted according to the usage status of each branch in the current communication link. Among them, in a complete data transmission process (data transmission from one connection node to another connection node), multiple switching nodes may be passed through. Any switching node passed through during the data transmission process can re-determine the transmission route and update the next switching node for the current switching node according to the usage status of each branch in the current communication link when receiving the data to be transmitted. The next switching node is the switching node directly connected to the current switching node, which will receive the data to be transmitted transmitted by the current switching node.

[0078] In one or more embodiments of the present specification, the connection module is specifically used to: after encapsulating the data to be transmitted into a number of data frames to be transmitted containing sorting information, generate and add a corresponding check code for each data frame to be transmitted using a cyclic redundancy check function; the switching node is specifically used to, when receiving the data frame to be transmitted, determine the availability of the data frame to be transmitted according to the check code in the data frame to be transmitted, and transmit the available data frame to be transmitted to the next switching node or a directly connected connection module; the connection module is specifically used to, when receiving the data frame to be transmitted, determine the availability of the data frame to be transmitted according to the check code in the data frame to be transmitted, and transmit the available data frame to be transmitted to the computing chip.

[0079] In order to avoid data frame damage caused by communication link problems, cyclic redundancy check (CRC) technology can be used to perform error detection on each data frame to be transmitted. When the connection module or switching node receives the data frame to be transmitted, the check code can be recalculated based on the data frame to be transmitted using the same redundancy check function. When the recalculated check code is inconsistent with the check code in the data frame to be transmitted, it can be determined that the data frame to be transmitted is damaged, and the data frame to be transmitted cannot continue to be transmitted, further ensuring the reliability of the inter-chip communication system.

[0080] The system provided in this specification can implement the above-mentioned cyclic redundancy check function on each connection module and each switching node. This function is set in the data link layer, that is, the above-mentioned partial reordering and partial delivery function must be implemented on the connection node side and the connection node.

[0081] In one or more embodiments of the present specification, the connection module is specifically used to encapsulate the data to be transmitted into data frames to be transmitted. For any data frame to be transmitted, the data frame to be transmitted includes original content and redundant content, the original content is the content in the data to be transmitted, and the redundant content is the forward error correction code generated according to the original content. The switching structure is specifically used to verify the original content in the data frame to be transmitted according to the redundant content in the data frame to be transmitted when the data frame to be transmitted is received. When the verification is successful, the data frame to be transmitted is transmitted to the next switching node or a directly connected connection module. When the verification fails, the original content is restored according to the redundant content, and the restored data frame to be transmitted is transmitted to the next switching node or a directly connected connection module. The connection module is also used to verify the original content in the data frame to be transmitted according to the redundant content in the data frame to be transmitted when the data frame to be transmitted is received. When the verification fails, the original content is restored according to the redundant content.

[0082] In order to avoid data frame damage caused by communication link problems, forward error correction code (FEC) technology can be used to generate redundant content based on the data to be transmitted, so that when the original content is damaged, the original content can be repaired based on the redundant content, and the repaired data to be transmitted can continue to be transmitted. Without the need for an additional retransmission mechanism, the stability and reliability of communication can be guaranteed.

[0083] The system provided in this specification can implement the above-mentioned forward error correction code function on each connection module and each switching node. This function is set at the physical layer, that is, the above-mentioned forward error correction code function must be implemented on the connection node side and the connection node.

[0084] In one or more embodiments of the present specification, the connection module is specifically used to determine the amount of receivable data of the target connection node. If the amount of receivable data is not less than the amount of data to be transmitted, the data to be transmitted is transmitted to the target connection node through the switching structure, and the amount of receivable data of the target connection node is updated; the connection module is also used to update the amount of receivable data of the connection node to which the current connection module belongs after receiving the data to be transmitted transmitted by other connection nodes and transmitting the data to be transmitted to the computing chip.

[0085] When data is transmitted between each connection node, a credit mechanism can be used. When any connection node needs to transmit data to be transmitted to other connection nodes, the receivable data amount of the target connection node of the data to be transmitted can be determined based on the receivable data amount of other connection nodes stored in itself. Only when the receivable data amount is not less than the data amount of the data to be transmitted, the data to be transmitted is transmitted to the target connection node, and the receivable data amount of the target connection node stored in the own connection node is updated - the data amount corresponding to the data to be transmitted is subtracted from the receivable data amount of the target node, and the receivable data amount of the target connection node stored in other connection nodes in the inter-chip communication system is updated through the communication link between each connection node. Correspondingly, the inter-chip interconnection module of the target connection node of the data to be transmitted can update the receivable data amount of the target connection node stored in each connection node in the inter-chip communication system after receiving the data to be transmitted - the data amount corresponding to the data to be transmitted is added to the receivable amount of the target node. In this way, it can be ensured that the data to be transmitted will not be lost due to congestion after reaching the target connection node.

[0086] In one or more embodiments of the present specification, the connection module is specifically used to: for any data frame to be transmitted, cut the data frame to be transmitted into flow control units of equal length according to a preset length threshold, and transmit each flow control unit to the target connection node through the switching structure.

[0087] The flow control unit is transmitted to the target connection node at a preset time interval. The connection module is also used to transmit an idle data stream to each other connection node at a preset time interval when there is no data to be transmitted.

[0088] Cutting a data frame into several flow control units (flits) of equal length will further refine the granularity of the communication process. Splitting a data frame into multiple flow control units for parallel transmission can further reduce communication delay and improve bandwidth utilization. Specifically, virtual channel VC technology can be used to split a communication link into several VCs, and each flow control unit corresponding to a data frame is mapped to each VC and transmitted simultaneously. This can also reduce the implementation cost of the inter-chip communication system.

[0089] On the other hand, the connection module is also used to transmit the flow control unit containing clock information to each other connection node through the switching structure at a preset time interval when there is no data to be transmitted.

[0090] Scrambling technology can be used to set the transmission of the control flow control unit to ensure that each connection node receiving the control data stream correctly recovers the clock.

[0091] In one or more embodiments of the present specification, the computing chip is specifically used to transmit the data to be transmitted to the connection module via an AXI interface, and the connection module is specifically used to transmit the data to be transmitted to the computing chip via an AXI interface.

[0092] The AXI protocol supports out-of-order, outstanding, interleave, bidirectional handshake flow control and other features. It is a high-performance, high-bandwidth, low-latency on-chip bus protocol. The inter-chip communication system provided in this specification draws on the design of the on-chip system and sets the interface between the computing chip in the connection node and the connection module as the AXI interface.

[0093] The system provided in this specification can implement the above-mentioned AXI interface function on each connection module and each computing chip. This function is set at the application layer, that is, it needs to be implemented on both the connection module side and the computing chip side, but it does not need to be implemented on the switching structure side.

[0094] In one or more embodiments of the present specification, the switch nodes are connected using SerDes technology.

[0095] SerDes technology can convert multiple parallel data channels into a single high-speed serial link, thereby improving the bandwidth utilization of the inter-chip communication system provided in this specification.

[0096] This specification also provides a method for establishing the inter-chip communication system. Specifically, the complete interconnection protocol can be divided into four layers: physical layer, data link layer, transaction layer, and application layer, wherein:

[0097] Application layer, completes the AXI standard interface.

[0098] Transaction layer, application layer data transmission and reception; efficient allocation of communication link resources; support for partial reordering and partial delivery of out-of-order parts; support for equal-length data frame segmentation.

[0099] Data link layer: data frame encapsulation and de-framing; maintenance of data frame sequence number; data frame CRC appending and verification; control or status data stream generation and analysis; link state machine maintenance.

[0100] Physical layer, realizing low-latency FEC; data frame scrambling; SerDes transmission.

[0101] When dealing with the situation where data frames are lost and need to be retransmitted, the method provided in this specification adopts an end-to-end retransmission mechanism at the application layer. Compared with the point-to-point retransmission mechanism at the link layer, on the one hand, it avoids the waste of resources of "one person is sick and everyone takes medicine", reduces the resource requirements for the intermediate path (such as the switching structure, etc.), and makes each connection node form an organic whole. On the second hand, it reduces the complexity and cost of implementing the switching structure, making it easier to build a large-capacity switching chip. On the third hand, the method provided in this specification sets the application layer as an AXI bus, and by integrating the retransmission mechanism with the error handling mechanism of AXI, it can be implemented efficiently and at a low cost.

[0102] Figure 3 The present invention is a flowchart of a method for inter-chip communication in this specification. The method is applied to an inter-chip communication system. The inter-chip communication system includes: a plurality of connection nodes and a switching structure. Each connection node is connected to the switching structure. For any connection node, the method includes the following steps:

[0103] S300: using the computing chip in the connection node to generate data to be transmitted according to the computing task, and transmitting the data to be transmitted to the connection module in the connection node;

[0104] S302: using the connection module to determine a target connection node for the data to be transmitted, and transmitting the data to be transmitted to the target connection node through the switching structure;

[0105] S310: When receiving data to be transmitted transmitted by other connection nodes, using the connection module to receive the data to be transmitted, and transmitting the data to be transmitted to the computing chip.

[0106] Optional, in Figure 3 In step S302 shown, the data to be transmitted is encapsulated into a plurality of data frames to be transmitted, and the data frames to be transmitted are transmitted to the target connection node through the switching structure.

[0107] Optionally, the switching structure specifically includes: a number of switching nodes equal to the number of connection nodes, each switching node is connected to form a two-dimensional grid structure, each connection node is directly connected to a switching node, and the switching nodes directly connected to each connection node are different.

[0108] Optional, in Figure 3 In step S302 shown in the figure, the data to be transmitted is encapsulated into a plurality of data frames to be transmitted containing sorting information, and the data to be transmitted is transmitted to the target connection node through the switching structure, and the data in each data frame to be transmitted is combined according to the sorting information to represent the complete data to be transmitted; the connection module specifically includes: a data buffer, the data buffer is used to store the data to be transmitted transmitted by the switching structure; Figure 3 In the step S310 shown, when any data frame to be transmitted is received, it is determined whether the transmission of the data to be transmitted is out of order based on the sorting information in the data frame to be transmitted and the historical sorting information. When the transmission of the data to be transmitted is out of order, the data frame to be transmitted is saved in the data buffer until a delayed data frame to be transmitted that can be sequentially combined with the data frame to be transmitted is received. The data frame to be transmitted and the delayed data frame to be transmitted are combined in the order of the sorting information in each data frame to be transmitted and transmitted to the computing chip.

[0109] Optional, in Figure 3 In step S302 shown, the target connection node of the data to be transmitted is determined, and the data to be transmitted including the address information of the target connection node is transmitted to the switching node directly connected to the connection module, so that when the switching node in the switching structure receives the data to be transmitted, the target switching node is determined according to the address information in the data to be transmitted. If the current switching node is the target switching node, the received data to be transmitted is transmitted to the directly connected connection module; otherwise, the target path is determined according to the target switching node and the communication load of each switching node in the switching structure, and the data to be transmitted is transmitted to the next switching node according to the target path.

[0110] Optional, in Figure 3 In step S302 shown in the figure, a cyclic redundancy check function is used to generate and add a corresponding check code for each data frame to be transmitted, so that when a switching node in the switching structure receives a data frame to be transmitted, the availability of the data frame to be transmitted is determined according to the check code in the data frame to be transmitted, and the available data frame to be transmitted is transmitted to the next switching node or a directly connected connection module; Figure 3 In step S310 shown, when a data frame to be transmitted is received, the connection module is used to determine the availability of the data frame to be transmitted according to the check code in the data frame to be transmitted, and the available data frame to be transmitted is transmitted to the computing chip.

[0111] Optional, in Figure 3 In step S302 shown, the data to be transmitted is encapsulated into data frames to be transmitted. For any data frame to be transmitted, the data frame to be transmitted includes original content and redundant content, the original content is the content in the data to be transmitted, and the redundant content is the forward error correction code generated according to the original content, so that when the switching node in the switching structure receives the data frame to be transmitted, the original content in the data frame to be transmitted is verified according to the redundant content in the data frame to be transmitted. When the verification is successful, the data frame to be transmitted is transmitted to the next switching node or the directly connected connection module. When the verification fails, the original content is restored according to the redundant content, and the restored data frame to be transmitted is transmitted to the next switching node or the directly connected connection module; in the example of Figure 3 In step S302 shown, when a data frame to be transmitted is received, the original content in the data frame to be transmitted is verified according to the redundant content in the data frame to be transmitted, and when the verification fails, the original content is restored according to the redundant content.

[0112] Optional, in Figure 3 In the step S302 shown, the receivable data amount of the target connection node is determined. If the receivable data amount is not less than the data amount of the data to be transmitted, the data to be transmitted is transmitted to the target connection node through the switching structure, and the receivable data amount of the target connection node is updated; in the step S310 shown, after receiving the data to be transmitted transmitted by other connection nodes and transmitting the data to be transmitted to the computing chip, the receivable data amount of the connection node to which the current connection module belongs is updated.

[0113] Optional, in Figure 3 In step S302 shown, for any data frame to be transmitted, the data frame to be transmitted is cut into flow control units of equal length according to a preset length threshold, and each flow control unit is transmitted to the target connection node through the switching structure.

[0114] Optionally, when there is no data to be transmitted, for any connection node, the connection node may transmit a flow control unit containing clock information to each other connection node through the switching structure at a preset time interval.

[0115] Optionally, the switch nodes are connected using SerDes technology.

[0116] This specification also provides a computer-readable storage medium, which stores a computer program, which can be used to execute the above Figure 3 A method for inter-chip communication is provided.

[0117] This manual also provides Figure 4 The schematic structure diagram of the electronic device shown in FIG. Figure 4 As mentioned above, at the hardware level, the inter-chip communication device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and may also include hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to achieve the above Figure 3 Of course, in addition to the software implementation, this specification does not exclude other implementations, such as logic devices or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0118] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0119] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0120] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0121] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0122] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0123] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0126] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0127] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0128] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0129] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0130] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0131] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0132] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0133] The above description is only an embodiment of this specification and is not intended to limit this specification. For those skilled in the art, this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification should be included in the scope of the claims of this application.

Claims

1. An inter-chip communication system, characterized in that: The system comprises: a plurality of connection nodes and a switching structure, each connection node being connected to the switching structure; For any connection node, the connection node includes a computing chip and a connection module; The computing chip is used to generate data to be transmitted according to the computing task, and transmit the data to be transmitted to the connection module; The connection module is used to determine the target connection node of the data to be transmitted, and transmit the data to be transmitted to the target connection node through the switching structure; The connection module is also used to receive data to be transmitted transmitted by other connection nodes, and transmit the data to be transmitted to the computing chip.

2. The system according to claim 1, characterized in that The connection module is specifically used to encapsulate the data to be transmitted into a plurality of data frames to be transmitted, and transmit the data frames to be transmitted to the target connection node through the switching structure.

3. The system according to claim 2, characterized in that The switching structure specifically includes: a number of switching nodes equal to the number of connection nodes, each switching node is connected to form a two-dimensional grid structure, each connection node is directly connected to a switching node, and the switching nodes directly connected to each connection node are different from each other.

4. The system according to claim 2, characterized in that The connection module is specifically used to encapsulate the data to be transmitted into a plurality of data frames to be transmitted containing sorting information, and transmit the data to be transmitted to the target connection node through the switching structure, wherein the data in each data frame to be transmitted is combined according to the sorting information to represent the complete data to be transmitted; The connection module specifically includes: a data buffer, the data buffer being used to store data to be transmitted by the switching structure; The connection module is specifically used to determine whether the transmission of any data frame to be transmitted is out of order based on the sorting information in the data frame to be transmitted and the historical sorting information when receiving the data frame to be transmitted; when the transmission of the data to be transmitted is out of order, the data frame to be transmitted is stored in a data buffer until a delayed data frame to be transmitted that can be sequentially combined with the data frame to be transmitted is received; the data frame to be transmitted and the delayed data frame to be transmitted are combined in order according to their respective sorting information, and then transmitted to the computing chip.

5. The system according to claim 3, characterized in that The connection module is specifically used to determine the target connection node of the data to be transmitted, and transmit the data to be transmitted including the address information of the target connection node to the switching node directly connected to the connection module; The switching node is used to determine the target switching node according to the address information in the data to be transmitted when receiving the data to be transmitted, and if the current switching node is the target switching node, transmit the received data to be transmitted to the directly connected connection module; otherwise, determine the target path according to the target switching node and the communication load of each switching node in the switching structure, and transmit the data to be transmitted to the next switching node according to the target path.

6. The system according to claim 3, characterized in that The connection module is specifically used to generate and add a corresponding check code for each data frame to be transmitted using a cyclic redundancy check function; The switching node is specifically configured to, when receiving a data frame to be transmitted, determine the availability of the data frame to be transmitted according to a check code in the data frame to be transmitted, and transmit the available data frame to be transmitted to the next switching node or a directly connected connection module; The connection module is specifically configured to, when receiving a data frame to be transmitted, determine the availability of the data frame to be transmitted according to a check code in the data frame to be transmitted, and transmit the available data frame to be transmitted to the computing chip.

7. The system according to claim 3, characterized in that The connection module is specifically used to encapsulate the data to be transmitted into data frames to be transmitted. For any data frame to be transmitted, the data frame to be transmitted includes original content and redundant content, the original content is the content in the data to be transmitted, and the redundant content is the forward error correction code generated according to the original content; The switching node is specifically configured to, when receiving a data frame to be transmitted, verify the original content in the data frame to be transmitted according to the redundant content in the data frame to be transmitted, and when the verification succeeds, transmit the data frame to be transmitted to the next switching node or a directly connected connection module, and when the verification fails, restore the original content according to the redundant content, and transmit the restored data frame to be transmitted to the next switching node or a directly connected connection module; The connection module is further used to verify the original content in the data frame to be transmitted according to the redundant content in the data frame to be transmitted when receiving the data frame to be transmitted, and restore the original content according to the redundant content when the verification fails.

8. The system of claim 1, wherein: The connection module is specifically used to determine the amount of data that can be received by the target connection node, and if the amount of data that can be received is not less than the amount of data to be transmitted, transmit the data to be transmitted to the target connection node through the switching structure, and update the amount of data that can be received by the target connection node; The connection module is further used to update the amount of receivable data of the connection node to which the current connection module belongs after receiving the data to be transmitted transmitted by other connection nodes and transmitting the data to be transmitted to the computing chip.

9. The system according to claim 2, characterized in that The connection module is specifically used to: for any data frame to be transmitted, cut the data frame to be transmitted into flow control units of equal length according to a preset length threshold, and transmit each flow control unit to the target connection node through the switching structure.

10. The system according to claim 9, characterized in that The connection module is also used to transmit the flow control unit containing clock information to each other connection node through the switching structure at a preset time interval when there is no data to be transmitted.

11. The system according to claim 2, characterized in that Each switching node is connected using SerDes technology.

12. A method for inter-chip communication, characterized in that: The method is applied to an inter-chip communication system, the inter-chip communication system comprising: a plurality of connection nodes and a switching structure, each connection node being connected to the switching structure; For any connection node, the method includes: Using the computing chip in the connection node, according to the computing task, to generate data to be transmitted, and transmitting the data to be transmitted to the connection module in the connection node; Determine the target connection node of the data to be transmitted by using the connection module, and transmit the data to be transmitted to the target connection node through the switching structure; When receiving data to be transmitted transmitted by other connection nodes, the connection module is used to receive the data to be transmitted, and the data to be transmitted is transmitted to the computing chip.

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