System and method for implementing memory and bandwidth expansion by dynamically switching a single shared memory

Abstract

The present invention provides a system and method for realizing memory and bandwidth expansion by dynamically switching a single shared memory. The system includes: multiple processors, each processor is provided with a memory controller and a serial communication interface, and a high-speed serial data bus is connected between the serial communication interfaces of two adjacent processors; independent memory is mounted on the memory controller of each processor, and the shared memory is connected to the memory controller of each processor through a hardware switching unit, and a memory signal is transmitted between the shared memory and the memory controller of each processor through the memory bus, and the processor sends a control signal to the hardware switching unit to control the hardware switching unit to switch the memory signal. The present invention can utilize the dynamic switching of shared memory to realize the memory expansion of the processor and the communication bandwidth expansion between the processors, optimize and improve the performance of different task stages of the system, thereby improving the calculation processing and high-speed data transmission performance of the optimized system.

Description

Technical Field

[0001] The present invention relates to the field of electronic communication technology, and in particular to a system and method for dynamically switching a single shared memory to achieve memory and bandwidth expansion. Background Art

[0002] Single-board systems with multiple processors used for large-scale computing and information forwarding generally use high-speed serial communication interfaces (such as PCIe, Ethernet, Serdes) or parallel communication interfaces (such as Localbus, parallel data bus) to achieve high-speed interconnection and transmission between multiple processors on the board. Serial communication interfaces have gradually become dominant in modern high-speed signal transmission, while parallel communication interfaces have a low cost-performance ratio in modern high-speed signal transmission and have gradually been eliminated in high-speed interconnection applications. In addition, a single processor unit in a multi-processor system generally needs to mount random dynamic memory (RAM) to cache data variables during the calculation process, which affects the computing and processing performance of the system. However, in general, the current system has a fixed transmission bandwidth between processors, and it is impossible to use dynamic expansion to improve the high-speed transmission of the system; and the memory capacity mounted on a single processor is fixed, and it is also impossible to use dynamic expansion to improve the computing and processing performance of the system. Summary of the invention

[0003] In view of the above situation, the present invention provides a system and method for dynamically switching a single shared memory to achieve memory and bandwidth expansion, placing shared access memory units between multiple processors, and dynamically adjusting the memory according to the calculation and transmission requirements at different times, so as to achieve the purpose of expanding memory and bandwidth, and optimize and improve the system's computing processing and high-speed data transmission performance. To achieve the above-mentioned purpose, the technical solution adopted by the present invention is to provide a system and method for dynamically switching a single shared memory to realize memory and bandwidth expansion, which includes: multiple processors, each of which is provided with a memory controller and a serial communication interface, and a high-speed serial data bus is connected between the serial communication interfaces of two adjacent processors; an independent memory, mounted on the memory controller of each processor; a shared memory, the shared memory is connected to each memory controller through a hardware switching unit, and a memory signal is transmitted between the shared memory and the memory controller of each processor through the memory bus, and the processor sends a control signal to the hardware switching unit to control the hardware switching unit to switch the memory signal.

[0004] Preferably, there are multiple hardware switching units, and the multiple hardware switching units are connected in series, one hardware switching unit is connected between every two adjacent processors, and one of the hardware switching units is connected to the shared memory.

[0005] Preferably, the hardware switching unit comprises S1, S2...Sn, a total of N high-speed hardware switching switch groups, and the number of switches contained in each of the high-speed hardware switching switch groups satisfies the total number of switches required for the data signal lines, address signal lines, and command signal lines of the processor when one of the memory controllers of the processor is configured to the maximum bit width.

[0006] Preferably, the high-speed hardware switching switch group is configured to be selected from a pure hardware analog switch group, a high-speed digital isolator or a high-speed integrated multi-channel switch.

[0007] Preferably, the processor is configured to be selected from a CPU processor and an FPGA programmable logic array.

[0008] Preferably, the serial communication interface is configured to be selected from PCIe, Ethernet or Serdes.

[0009] Preferably, the memory signal includes a memory data signal, a memory address signal, and a memory control signal.

[0010] Preferably, the independent memory and the shared memory are configured as a DDR memory group.

[0011] The present invention provides a system expansion method for implementing memory and bandwidth expansion by adopting a single shared memory dynamic switching, comprising the following steps: When a single processor needs to perform a computational task, The single processor sends a control signal to the hardware switching unit, controlling the hardware switching unit to switch the memory signal to the single processor, so that the single processor simultaneously mounts the independent memory and the shared memory to expand the memory; When data needs to be transferred between processors, there are two steps: Step S1, a part of data of the transmission processor of the data to be transmitted is transmitted to the receiving processor of the data to be received through a high-speed serial data bus; Step S2, the transmission processor sends a control signal to the hardware switching unit, controlling the hardware switching unit to switch the memory signal to the transmission processor, so that the transmission processor mounts the shared memory and writes another part of the data into the shared memory; After writing is completed, the signal is synchronously transmitted to the receiving processor, and the receiving processor sends the control signal to the hardware switching unit to control the hardware switching unit to switch the memory signal to the receiving processor, so that the receiving processor mounts the shared memory and reads the other part of the data in the shared memory, thereby expanding the communication bandwidth between processors.

[0012] The beneficial effect of the present invention is that a system and method for dynamically switching a single shared memory to achieve memory and bandwidth expansion of the present invention, in which shared memory between chips is placed in a multi-processor system, and shared memory between multiple processors is switched by hardware. When a processor in the system needs large-scale data calculation, the memory capacity of the processor can be expanded, thereby improving its computing and processing performance; when large-scale data transmission is required during processing in the system, the shared memory switching processor can be used to complete read and write operations respectively to achieve data transmission, further expand the data transmission bandwidth between processors, improve transmission efficiency, and reduce transmission time. This method of dynamic shared memory switching realizes the memory expansion of the processor and the communication bandwidth expansion between processors, optimizes and improves the performance of different task stages of the system, and further brings into play the potential performance of the system. The present invention enables part of the data to be transmitted through a high-speed serial data transmission channel, while another part of the data can be transmitted using a shared memory switching processor, eliminating processes such as serial-to-parallel conversion, encoding and decoding, and cache processing, thereby improving the transmission efficiency of the entire system and reducing transmission time. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 It is a structural composition block diagram of Embodiment 1 of the system for implementing memory and bandwidth expansion by dynamically switching a single shared memory according to the present invention.

[0015] Figure 2 This is a structural composition block diagram of Embodiment 2 of the system for implementing memory and bandwidth expansion by dynamically switching a single shared memory according to the present invention.

[0016] Figure 3 This is a structural composition block diagram of Embodiment 3 of the system for implementing memory and bandwidth expansion by dynamically switching a single shared memory according to the present invention.

[0017] 1. Processor; 2. Independent memory; 3. Shared memory; 4. Hardware switching unit; 401. High-speed hardware switching switch group; 5. High-speed serial data bus. DETAILED DESCRIPTION

[0018] To facilitate understanding of the present invention, the following description is provided in conjunction with the accompanying drawings and embodiments.

[0019] Multi-processor systems often include interconnect interfaces for high-speed data transmission between chips and their own running memory units. The high-speed data transmission interconnect interfaces between chips are only used for data transmission and forwarding, and are important parameters for measuring the system's data forwarding capabilities. The running memory units are only used for computing and processing to store cache, which affects the system's computing and processing performance. Both are very critical parameters of the system and affect the overall performance of the system.

[0020] The present invention considers placing shared memory units between multiple processors, switching shared memory mechanisms according to different needs, improving performance in different aspects at different times, and optimizing and improving the system's computing processing and high-speed data transmission performance, which is mainly reflected in two aspects: First, when the system needs intensive computing tasks, the shared memory is switched to the processor that executes the corresponding computing tasks through the hardware switching unit for use as extended memory, thereby increasing the cache capacity of the processor, improving the computing performance of the processor, shortening the computing time, and thus improving the efficiency of the entire system. The expansion of the shared memory capacity space can be expanded according to the processor memory bit width, bus bit width, and chip particle number, and can also be expanded in multiple groups through the memory chip select signal; Secondly, when the system requires large-scale data transmission between multiple processors, the shared memory is switched to a certain processor through a hardware switching unit to write the data, and then switched to another processor to directly read the data in the shared memory for processing, thereby realizing parallel data transmission. On the basis of serial transmission, the transmission bandwidth between multiple processors is further expanded, the data transmission capacity between chips is improved, and the data transmission time is shortened. Moreover, compared with data transmission through a high-speed serial bus, the use of shared memory to realize data transmission saves the processes of serial-to-parallel conversion, encoding and decoding, and cache processing, thereby improving the efficiency of the entire system.

[0021] See also Figures 1 to 3 As shown, the present invention provides a system for dynamically switching a single shared memory to achieve memory and bandwidth expansion, comprising a processor 1, an independent memory 2, and a shared memory 3. Among them: There are multiple processors 1, and the processors 1 are configured to be selected from CPU processors, FPGA programmable logic arrays or other types of processors. Each processor 1 is provided with a memory controller and a serial communication interface. The serial communication interface is configured to be selected from PCIe, Ethernet or Serdes. A high-speed serial data bus 5 is connected between the serial communication interfaces of two adjacent processors 1, so that each processor 1 has a high-speed serial data transmission channel to provide high-speed data transmission capability, and also ensure that when the shared memory 3 is used for the extended memory of a processor 1, the high-speed channel can still maintain high-speed real-time data transmission between the processors 1.

[0022] The independent memory 2 is mounted on the memory controller of each processor 1, so that each processor 1 can execute an independent computing task when not switching to the shared memory 3.

[0023] The shared memory 3 is connected to the memory controller of each processor through the hardware switching unit 4, and a memory signal is transmitted between the shared memory 3 and the memory controller of each processor 1 through the memory bus. The memory signal includes a memory data signal, a memory address signal, and a memory control signal. The processor sends a control signal to the hardware switching unit 4 to control the hardware switching unit 4 to switch the memory signal.

[0024] Independent memory 2 and shared memory 3 are configured as a DDR memory group.

[0025] There are multiple hardware switching units 4 , and the multiple hardware switching units 4 are connected in series. There is a hardware switching unit 4 connected between every two adjacent processors 1 , and one of the hardware switching units 4 is connected to the shared memory 3 .

[0026] The hardware switching unit 4 includes S1, S2...Sn, a total of N high-speed hardware switching switch groups 401. The number of switches contained in each high-speed hardware switching switch group 401 satisfies the total number of switches required for the data signal lines, address signal lines, and command signal lines of the processor 1 when a memory controller of a processor 1 is configured to the maximum bit width.

[0027] The high-speed hardware switching switch group 401 is configured to be selected from a pure hardware analog switch group, a high-speed digital isolator, or a high-speed integrated multi-channel switch.

[0028] The present invention also provides a system expansion method for implementing memory and bandwidth expansion by using a single shared memory dynamic switching, comprising the following steps: When a single processor needs to perform a computational task, The single processor sends a control signal to the hardware switching unit, which controls the hardware switching unit to switch the memory signal to the single processor, so that the single processor can simultaneously mount the independent memory and the shared memory to expand the memory; When data needs to be transferred between processors, there are two steps: Step S1, a part of the data of the transmission processor of the data to be transmitted is transmitted to the receiving processor of the data to be received through the high-speed serial data bus 5; Step S2, the processor of the transmission processor of the data to be transmitted sends a control signal to the hardware switching unit 4, controls the hardware switching unit 4 to switch the memory signal to the transmission processor, so that the transmission processor mounts the shared memory 3, and writes another part of the data into the shared memory 3; After writing is completed, the signal is synchronously transmitted to the receiving processor, and the receiving processor sends a control signal to the hardware switching unit 4, which controls the hardware switching unit 4 to switch the memory signal to the receiving processor, so that the receiving processor 1 mounts the shared memory 3 and reads another part of the data in the shared memory 3, thereby expanding the communication bandwidth between processors.

[0029] The present invention provides three specific embodiments, as follows: Embodiment 1 like Figure 1 As shown, the system of the present invention has two processors and their shared memory, including a CPU processor and an FPGA, and a hardware switching unit 4, and the CPU processor and the FPGA are respectively mounted with an independent DDR memory group, the hardware switching unit 4 is mounted with a shared DDR memory group 3, and a high-speed serial data bus 5 is connected between the CPU processor and the FPGA.

[0030] 1. This system can be used to expand the processor's memory. The specific process is as follows: (1) CPU processor-side memory expansion When the CPU processor performs a large data processing computing task, the control hardware switching unit 4 switches the shared memory 3 to be mounted on the CPU processor. At this time, the CPU processor simultaneously mounts the independent DDR memory group 2 and the shared DDR memory group 3, and its memory capacity is greatly expanded, which can temporarily store more computing cache variables and processes, thereby improving the computing processing performance of the CPU processor, shortening the processing time, and improving the overall efficiency of the system; (2) FPGA-side memory expansion When the FPGA performs a large-scale raw data preprocessing task, the control hardware switching unit 4 switches the shared memory 3 to be mounted on the FPGA. At this time, the FPGA simultaneously mounts the independent DDR memory group 2 and the shared DDR memory group 3, and its memory capacity is greatly expanded, which can temporarily store more calculation cache variables and processes, thereby improving the FPGA calculation processing performance, shortening the processing time, and improving the overall efficiency of the system; 2. This system can achieve the expansion of communication bandwidth between CPU processor and FPGA. The specific process is as follows: After the FPGA collects data and completes preprocessing, a large amount of preprocessing result data needs to be transferred to the CPU processor through the high-speed serial data bus 5 for in-depth analysis and processing. At this time, the control hardware switching unit 4 switches the shared DDR memory group 3 to be mounted on the FPGA end, and the FPGA sends part of the data to the CPU processor through the serial high-speed bus 5, and encapsulates the other part of the data according to the protocol requirements, and writes it into the shared DDR memory group 3 in sequence. After the writing is completed, it is synchronously transmitted to the CPU processor end, and the CPU processor controls the hardware switching unit 4 to switch the shared memory 3 to be mounted on the CPU processor, and reads the data in the shared DDR memory group 3 through the memory controller, thereby completing a data transmission, and the data can be directly transferred to the core cache of the CPU processor for processing, without the need for the serial-to-parallel, encoding-decoding, and cache processing of the high-speed serial data bus 5. Repeatedly, through the shared memory 3 unit, part of the data can be smoothly transferred from the FPGA end to the CPU processor end. On the basis of the original high-speed serial bus, the data transmission realized by the shared memory 3 provides a new high-speed data transmission path between the CPU processor end and the FPGA end, which reduces the transmission pressure of the high-speed serial bus, reduces the transmission time, and improves the transmission efficiency. In addition, this method saves the processes of serial-to-parallel, encoding and decoding, and scrambling in high-speed serial transmission, and also relieves the pressure of the original cache. Similarly, after the CPU processor writes data, it can switch the shared memory 3 to the FPGA end, and the FPGA reads it, and the cycle is repeated to complete the data transmission from the CPU processor end to the FPGA end.

[0031] Embodiment 2 like Figure 2 As shown, based on the above described one CPU processor and one FPGA solution, the present invention can also be transformed into the following form: two CPU processors, two FPGAs and a shared memory unit 3, two-level switching channels can realize two cross-memory and bandwidth expansion. The system of the present invention has four processors, including two CPU processors and two FPGAs, and three hardware switching units 4, and each CPU processor and each FPGA is mounted with an independent DDR memory group ( Figure 2 Independent DDR memory groups are omitted), a hardware switching unit 4 is connected between CPU processor 2 and CPU processor 1, a hardware switching unit 4 is connected between CPU processor 1 and FPGA1, and a hardware switching unit 4 is connected between FPGA1 and FPGA2. The three hardware switching units 4 are connected in series, wherein the middle hardware switching unit 4 is mounted with a shared DDR memory group 3, and a high-speed serial data bus 5 is connected between two adjacent processors.

[0032] The working state similar to the above-mentioned single CPU processor and single FPGA is not described again. The processor and the processor can use the hardware switching unit 4 to complete the access to the shared DDR group 3. Based on this, combined with the memory expansion and communication bandwidth expansion method implemented by switching the shared memory 3 using the hardware switching unit 4 described above, the following is: 1. This system can be used to expand the processor's memory. The specific process is as follows: When CPU processor 1, CPU processor 2, FPGA 1, and FPGA 2 need to run large-scale computing tasks, they can expand the memory through hardware switching unit 4, occupy shared memory 3 for their own computing and processing cache, thereby improving the processing capability of a single processor and saving processing time. 2. This system can be used to expand the communication bandwidth between processors. The specific process is as follows: (1) Communication bandwidth expansion between CPU processor 1 and CPU processor 2 The shared memory 3 can be accessed in time-sharing manner through the hardware switching unit 4, and data transmission can be realized by using the method of writing on one side and reading on the other side. On the basis of the original high-speed serial data bus 5, the bandwidth between the CPU processor 1 and the CPU processor 2 is improved, and the data transmission time is shortened; (2) Communication bandwidth expansion between FPGA1 and FPGA2 The shared memory 3 can be accessed in time-sharing manner through the hardware switching unit 4, and data transmission can be realized by using the method of writing on one side and reading on the other side. On the basis of the original high-speed serial data bus 5, the bandwidth between FPGA1 and FPGA2 is improved, and the data transmission time is shortened; (3) Communication bandwidth expansion between CPU processor 2 and FPGA 1 The shared memory 3 can be accessed in time-sharing manner through the hardware switching unit 4, and data transmission can be realized by using the method of writing on one side and reading on the other side. On the basis of the original high-speed serial data bus 5, the bandwidth between the CPU processor 2 and the FPGA 1 is improved, and the data transmission time is shortened; (4) Communication bandwidth expansion between CPU processor 1 and FPGA 2 The shared memory 3 can be accessed in time-sharing manner through the hardware switching unit 4, and data transmission can be achieved by using the method of writing on one side and reading on the other side. On the basis of the original high-speed serial data bus 5, the bandwidth between the CPU processor 1 and the FPGA 2 is improved, and the data transmission time is shortened.

[0033] Embodiment 3 like Figure 3As shown, similarly, on the basis of the above, a multi-level hardware switching unit 4 and N processors can be added to realize the switching of the shared memory 3 between the N processors and the N FPGAs to expand the memory and communication bandwidth. The above N processors and N FPGAs access the same shared memory 3 through the multi-level switching unit, which can achieve the following points: 1. N processors and N FPGAs can expand their own memory and improve the computing speed through the multi-level hardware switching unit 4; 2. N processors and N FPGAs can be realized through a multi-level hardware switching unit 4: a high-speed transmission channel based on a shared memory 3 is constructed between any two processors, and the transmission speed between the processors is improved on the basis of the original high-speed serial bus between the two processors; a high-speed transmission channel based on a shared memory 3 is constructed between any two FPGAs, and the transmission speed between the processors is improved on the basis of the original high-speed serial bus between the two FPGAs; a high-speed transmission channel based on a shared memory 3 is constructed between any processor and any FPGA, and the transmission speed between the processor and the FPGA is improved on the basis of the original high-speed serial bus between the processor and the FPGA.

[0034] The present invention is actually applied to the field of information processing. The system with CPU processor and FPGA is limited by the bandwidth of the serial communication interface of CPU processor and the maximum rate that FPGA can achieve. Taking PCIe serial interface as an example, the theoretical maximum rate that PCIe3.0 interface with bit width x16 can achieve is 16GB / s transmission rate, but because the actual processing needs to consume resources such as serial-to-parallel conversion, encoding and decoding, and cache processing, it can actually only reach a rate of 6.4GB / s. Using a shared memory with a 64-bit bit width and 8GB capacity as a data transmission channel, even if the switching switch affects the memory read and write speed, thanks to the advantages of the memory parallel port, the bandwidth it can contribute is considerable. After testing, using shared memory as a data transmission channel can stably reach a rate of 1.6GB / s, which can effectively increase the rate between the CPU processor and FPGA to about 8GB / s, and improve the data transmission efficiency in the system.

[0035] At the same time, the processor memory capacity can be expanded to increase to 8GB. During the calculation process, more cache can be placed, reducing the possibility of memory overflow. It also avoids the problem of having to store part of the data in a relatively low-speed hard disk when the memory overflows, and then reading it out when needed, saving time and improving the efficiency of calculation processing.

[0036] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A system for implementing memory and bandwidth expansion by dynamically switching a single shared memory, characterized in that: include: A plurality of processors, each of which is provided with a memory controller and a serial communication interface, and a high-speed serial data bus is connected between the serial communication interfaces of two adjacent processors; Independent memory mounted on the memory controller of each of the processors; Shared memory, the shared memory is connected to the memory controller of each processor through a hardware switching unit, and a memory signal is transmitted between the shared memory and the memory controller of each processor through a memory bus, and the processor sends a control signal to the hardware switching unit to control the hardware switching unit to switch the memory signal.

2. The system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 1, characterized in that: There are multiple hardware switching units, and the multiple hardware switching units are connected in series. One hardware switching unit is connected between every two adjacent processors, and one of the hardware switching units is connected to the shared memory.

3. The system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 1, characterized in that: The hardware switching unit includes S1, S2...Sn, a total of N high-speed hardware switching switch groups, and the number of switches contained in each high-speed hardware switching switch group meets the total number of switches required for the data signal lines, address signal lines, and command signal lines of the processor when one of the memory controllers of the processor is configured to the maximum bit width.

4. The system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 3, characterized in that: The high-speed hardware switching switch group is configured to be selected from a pure hardware analog switch group, a high-speed digital isolator or a high-speed integrated multi-channel switch.

5. The system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 1, characterized in that: The processor is configured to be selected from a CPU processor and an FPGA programmable logic array.

6. The system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 1, characterized in that: The serial communication interface is configured to be selected from PCIe, Ethernet or Serdes.

7. The system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 1, characterized in that: The memory signal includes a memory data signal, a memory address signal, and a memory control signal.

8. The system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 1, characterized in that: The independent memory and the shared memory are configured as a DDR memory group.

9. A method for expanding a system for implementing memory and bandwidth expansion by dynamically switching a single shared memory as claimed in claim 1, characterized in that: The steps include: When a single processor needs to perform a computational task, The single processor sends a control signal to the hardware switching unit, controlling the hardware switching unit to switch the memory signal to the single processor, so that the single processor simultaneously mounts the independent memory and the shared memory to expand the memory; When data needs to be transferred between processors, Step S1, a part of data of the transmission processor of the data to be transmitted is transmitted to the receiving processor of the data to be received through a high-speed serial data bus; Step S2, the transmission processor sends a control signal to the hardware switching unit, controlling the hardware switching unit to switch the memory signal to the transmission processor, so that the transmission processor mounts the shared memory and writes another part of the data into the shared memory; After writing is completed, the signal is synchronously transmitted to the receiving processor, and the receiving processor sends the control signal to the hardware switching unit to control the hardware switching unit to switch the memory signal to the receiving processor, so that the receiving processor mounts the shared memory and reads the other part of the data in the shared memory, thereby expanding the communication bandwidth between processors.

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