Design method and design equipment of semiconductor structure and computer readable storage medium

Abstract

The invention provides a semiconductor structure design method and device and a computer readable storage medium, and the method comprises the steps: adjusting the wiring modes of metal wires in representative volume elements, so as to obtain a plurality of representative volume elements with different metal wire wiring modes; establishing a plurality of first finite element simulation models for the plurality of representative volume elements, and respectively acquiring equivalent material performance of the plurality of first finite element simulation models; and based on the equivalent material performance of the plurality of first finite element simulation models and the material performance of the substrate, establishing a plurality of second finite element simulation models for the to-be-designed semiconductor structure, and simulating buckling deformation conditions of the plurality of second finite element simulation models in the heat treatment process and after the heat treatment process.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor structure design, and in particular to a semiconductor structure design method, design equipment and computer-readable storage medium. Background Art

[0002] Semiconductor structures (such as memory) generally include a wafer and an interconnect structure formed on the wafer, wherein the interconnect structure is composed of a plurality of metal wires. During the manufacturing process of the interconnect structure, the wafer may be warped due to thermal expansion coefficient mismatch and other reasons, thereby reducing the performance of the semiconductor structure. Summary of the invention

[0003] The present disclosure provides a design method for a semiconductor structure. The semiconductor structure to be designed includes a substrate and an interconnection layer located on the substrate. The interconnection layer includes a plurality of periodically arranged minimum repeatable volume units. The minimum repeatable volume unit is used as a representative volume element of the interconnection layer. The representative volume element includes an interlayer dielectric layer and a plurality of metal wires located in the interlayer dielectric layer. The design method includes:

[0004] Adjusting the wiring mode of the metal wires in the representative volume element to obtain a plurality of representative volume elements with different wiring modes of the metal wires;

[0005] Establishing a plurality of first finite element simulation models for the plurality of representative volume elements, and respectively obtaining equivalent material properties of the plurality of first finite element simulation models;

[0006] Based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate, multiple second finite element simulation models are established for the semiconductor structure to be designed, and the warping deformation of the multiple second finite element simulation models during and after the heat treatment process is simulated.

[0007] In some embodiments, the representative volume element includes multiple metal layers located in the interlayer dielectric layer, and any of the metal layers includes at least one metal line extending in a direction parallel to a substrate plane; adjusting the wiring mode of the metal lines in the representative volume element includes:

[0008] Adjust the wiring mode of the metal lines in at least one of the metal layers.

[0009] In some embodiments, any of the metal layers includes one region or multiple regions, each region having multiple metal wires extending in the same direction and uniformly arranged in a direction intersecting the extending direction.

[0010] In some embodiments, respectively obtaining equivalent material properties of a plurality of the first finite element simulation models includes:

[0011] Apply stress to each of the first finite element simulation models along multiple directions respectively, and perform finite element simulation calculation to obtain a first strain of each of the first finite element simulation models in the stress direction;

[0012] Based on the applied stress and the first strain of the first finite element simulation model, an equivalent elastic modulus and a Poisson's ratio of each of the first finite element simulation models in the multiple directions are obtained.

[0013] In some embodiments, the equivalent elastic modulus of the first finite element simulation model in any direction is calculated according to the following relationship (1):

[0014]

[0015] Among them, V m is the volume of the first finite element simulation model, dV m is the integral variable, which refers to the small volume element during integration, σ S When stress is applied to the first finite element simulation model along any direction, the small volume element dV in the first finite element simulation model m The stress borne, ε S1 is the tiny volume element dV m At stress σ S The strain generated along the stress direction under the action of is the equivalent stress applied to the first finite element simulation model, is the equivalent strain of the first finite element simulation model along the stress direction.

[0016] In some embodiments, respectively obtaining equivalent material properties of a plurality of the first finite element simulation models further includes:

[0017] Applying thermal loads to each of the first finite element simulation models along multiple directions respectively, and performing finite element simulation calculations to obtain temperature changes of each of the first finite element simulation models and second strains along the thermal load directions;

[0018] Based on the applied thermal load, the temperature change, and the second strain, an equivalent thermal expansion coefficient of each of the first finite element simulation models in the multiple directions is obtained.

[0019] In some embodiments, the equivalent thermal expansion coefficient of the first finite element simulation model is obtained according to the following relationship (2):

[0020]

[0021] Among them, Vm is the volume of the first finite element simulation model, dV m is the integral variable, which refers to the small volume element during integration, ε S2 For a small volume unit dV m The deformation along the direction of the thermal load when the temperature changes by ΔT.

[0022] In some embodiments, the shape of the first finite element simulation model includes a cuboid, a surface of the cuboid parallel to the substrate plane includes vertices A, B, C, and D, wherein vertices A and B are adjacent in a straight line, vertices A and C are adjacent diagonally, and vertices B and D are adjacent diagonally, and the direction from vertex A to vertex B is defined as the x-axis direction, the direction from vertex A to vertex D is defined as the y-axis direction, and the direction perpendicular to the x-axis direction and the y-axis direction is defined as the z-axis direction; applying stress and thermal load to the first finite element simulation model along multiple directions respectively includes:

[0023] Stress and thermal load are applied to the first finite element simulation model along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction and the third direction respectively; wherein the first direction forms an angle of 45° with the x-axis direction and the y-axis direction; the second direction forms an angle of 45° with the x-axis direction and the z-axis direction; and the third direction forms an angle of 45° with the y-axis direction and the z-axis direction.

[0024] The present disclosure also provides a design device for a semiconductor structure, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the design method as described in any of the above embodiments when executing the computer program.

[0025] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the design method described in any of the above embodiments is implemented.

[0026] The present disclosure provides a design method, a design device and a computer-readable storage medium for a semiconductor structure, wherein the semiconductor structure to be designed includes a substrate and an interconnection layer located on the substrate, the interconnection layer includes a plurality of periodically arranged minimum repeatable volume units, the minimum repeatable volume unit is used as a representative volume element of the interconnection layer, the representative volume element includes an interlayer dielectric layer and a plurality of metal wires located in the interlayer dielectric layer; the design method of the semiconductor structure includes: adjusting the wiring mode of the metal wires in the representative volume element to obtain a plurality of representative volume elements with different metal wire wiring modes; establishing a plurality of first finite element simulation models for the plurality of representative volume elements, and respectively obtaining equivalent material properties of the plurality of first finite element simulation models; establishing a plurality of second finite element simulation models for the semiconductor structure to be designed based on the equivalent material properties of the plurality of first finite element simulation models and the material properties of the substrate, and simulating the warping deformation of the plurality of second finite element simulation models during and after the heat treatment process. The embodiment of the present disclosure adjusts the wiring method of the metal wires within the representative volume element (RVE) and establishes a first simulation model for the representative volume element, so as to obtain the equivalent material properties of the representative volume element with different metal wire wiring methods. Then, based on the equivalent material properties of the multiple representative volume elements and the material properties of the substrate, multiple second simulation models are established, and the warping deformation conditions of the multiple second simulation models are obtained. In this way, the warping deformation conditions of the semiconductor structure when having different metal wiring methods can be obtained, so that the metal wiring method with the lowest warping value can be screened out from the limited metal wiring methods, so as to effectively adjust and control the warping deformation condition of the semiconductor structure and improve the success rate of subsequent bonding and packaging processes. At the same time, the present disclosure models the minimum repeatable volume unit in the interconnection layer of the semiconductor structure to be designed as the representative volume element, instead of modeling all metal patterns in the interconnection layer, thereby saving simulation calculation complexity and cost.

[0027] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the accompanying drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A flowchart of a semiconductor structure design method provided by an embodiment of the present disclosure;

[0030] Figure 2 A schematic diagram of a semiconductor structure to be designed according to an embodiment of the present disclosure;

[0031] Figure 3 A schematic diagram of a three-dimensional structure of a representative volume element provided in an embodiment of the present disclosure;

[0032] Figure 4 Figures (1) to (4) are different examples of the arrangement of metal lines in any metal layer in a representative volume element provided in an embodiment of the present disclosure;

[0033] Figure 5 is a schematic diagram of a first finite element simulation model established in an embodiment of the present disclosure;

[0034] Figure 6 The warpage distribution of the semiconductor structure calculated by the second finite element simulation model established for the embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of the structure of the design device provided in the embodiment of the present disclosure;

[0036] Figure 8 A schematic diagram of the computer-readable storage medium structure provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The exemplary embodiments disclosed in the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0038] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0039] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0041] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Semiconductor structures (such as memory) generally include a wafer and an interconnect structure formed on the wafer, wherein the interconnect structure is composed of a plurality of metal wires. During the manufacturing process of the interconnect structure, the wafer may be warped due to thermal expansion coefficient mismatch and other reasons, thereby reducing the performance of the semiconductor structure.

[0044] Based on this, an embodiment of the present disclosure provides a design method for a semiconductor structure, wherein the semiconductor structure to be designed includes a substrate and an interconnection layer located on the substrate, wherein the interconnection layer includes a plurality of periodically arranged minimum repeatable volume units, and the minimum repeatable volume unit is used as a representative volume element of the interconnection layer, wherein the representative volume element includes an interlayer dielectric layer and a plurality of metal wires located in the interlayer dielectric layer; for details, please refer to Figure 1 , as shown in the figure, the method includes the following steps:

[0045] Step S101, adjusting the wiring mode of metal wires in a representative volume element to obtain a plurality of representative volume elements having different wiring modes of metal wires;

[0046] Step S102, establishing a plurality of first finite element simulation models for the plurality of representative volume elements respectively, and obtaining equivalent material properties of the plurality of first finite element simulation models respectively;

[0047] Step S103, establishing multiple second finite element simulation models for the semiconductor structure to be designed based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate, and simulating the warping deformation of the multiple second finite element simulation models during and after the heat treatment process.

[0048] The embodiment of the present disclosure adjusts the wiring method of the metal wires within the representative volume element (RVE) and establishes a first simulation model for the representative volume element, so as to obtain the equivalent material properties of the representative volume element with different metal wire wiring methods. Then, based on the equivalent material properties of the multiple representative volume elements and the material properties of the substrate, multiple second simulation models are established, and the warping deformation conditions of the multiple second simulation models are obtained. In this way, the warping deformation conditions of the semiconductor structure when having different metal wiring methods can be obtained, so that the metal wiring method with the lowest warping value can be screened out from the limited metal wiring methods, so as to effectively adjust and control the warping deformation condition of the semiconductor structure and improve the success rate of subsequent bonding and packaging processes. At the same time, the present disclosure models the minimum repeatable volume unit in the interconnection layer of the semiconductor structure to be designed as the representative volume element, instead of modeling all metal patterns in the interconnection layer, thereby saving simulation calculation complexity and cost.

[0049] The design method of the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below with reference to the accompanying drawings.

[0050] like Figure 2 and Figure 3 As shown, in some embodiments, the semiconductor structure to be designed includes a substrate 10 and an interconnection layer 11 located on the substrate 10, the interconnection layer 11 includes a plurality of periodically arranged minimum repeatable volume units 12, the minimum repeatable volume unit 12 is used as a representative volume element 13 of the interconnection layer 11, and the representative volume element 13 includes an interlayer dielectric layer 14 and a plurality of metal wires 151 located in the interlayer dielectric layer 14.

[0051] Here, the semiconductor structure to be designed refers to a semiconductor structure that has not yet been layout-designed. Subsequently, after selecting a metal wiring method with the lowest warpage value from a limited number of metal wiring methods, the semiconductor structure is layout-designed based on the metal wiring method with the lowest warpage value. The semiconductor structure to be designed includes a 3D semiconductor structure.

[0052] Here, the substrate 10 may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate 10 is a silicon (Si) wafer.

[0053] In some embodiments, the substrate 10 may further include device structures (not shown) formed on the surface and / or inside the substrate 10 , such as transistors, word lines, bit lines, and other device structures.

[0054] like Figure 3 As shown, in some embodiments, the representative volume element 13 includes a plurality of metal layers 15 located in the interlayer dielectric layer 14, and any metal layer 15 includes at least one metal line 151 extending in a direction parallel to the plane of the substrate 10. In actual operation, the metal line 151 may be a metal line constituting a metal pad in the interconnection layer 11. In some embodiments, the metal line 151 may also include a virtual metal line, which is not used to transmit electrical signals. By adding a virtual metal line in the interconnection layer 11, the distribution of the metal lines 151 in the interconnection layer 11 is uniformed, so that the interconnection layer 11 can be presented as being composed of a plurality of minimum repeatable volume units 12 arranged in a periodic manner.

[0055] In actual operation, the interlayer dielectric layer 14 may be a multi-layer structure formed in different processes. Figure 3As shown, in some embodiments, the dielectric layer 14 includes multiple first sublayers 141 and at least one second sublayer 142, the first sublayers 141 and the second sublayers 142 are alternately stacked in the vertical direction, and the multiple metal layers 15 are respectively distributed in the multiple first sublayers 141. In some embodiments, the representative volume element 13 may also include a plug (not shown) formed in the second sublayer 142, and the plug may be used to electrically connect two adjacent metal layers 15.

[0056] In the actual process, the materials of the first sublayer 141 and the second sublayer 142 may be the same or different. The materials of the first sublayer 141 and the second sublayer 142 include one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.; the materials of the metal wire 151 and the plug (not shown) may include one or more of W (tungsten), Cu (copper), Co (cobalt), TiN (titanium nitride), Ti (titanium), Ta (tantalum), TaN (tantalum nitride) and Al (aluminum), etc.

[0057] First, step S101 is executed to adjust the wiring pattern of the metal wires 151 in the representative volume element 13 to obtain a plurality of representative volume elements 13 having different wiring patterns of the metal wires 151 .

[0058] In some embodiments, adjusting the wiring mode of the metal wires 151 in the representative volume element 13 includes: adjusting the wiring mode of the metal wires 151 in at least one metal layer 15. The wiring mode here may refer to at least one of the number, extension direction, arrangement direction, and placement position of the metal wires 151. In this way, by adjusting the wiring mode of the metal wires 151 in one or more metal layers 15 in the representative volume element 13, the warping deformation of the semiconductor structure to be designed can be adjusted in multiple directions parallel to the substrate 10 (for example, the x-axis direction and the y-axis direction), and is not limited to adjusting the warping deformation of the semiconductor structure to be designed in one direction.

[0059] In some embodiments, the number of metal wires 151 in each metal layer 15 can be adjusted to one or more. When the number of metal wires 151 in a metal layer 15 is multiple, the multiple metal wires 151 can be adjusted to be arranged in the same direction or different directions, and the number, extension direction, arrangement direction and other parameters of the metal wires 151 in any two metal layers 15 in the representative volume element 13 can be adjusted to be the same or different.

[0060] It should be noted that the representative volume element 13 with different wiring modes of the metal wires 151 needs to meet the layout design rules to avoid adversely affecting the performance of the semiconductor structure finally manufactured. In some embodiments, adjusting the wiring mode of the metal wires 151 in the representative volume element 13 also includes adjusting the distribution position, quantity and other parameters of the plugs (not shown) between adjacent metal layers 15.

[0061] like Figure 4 As shown, in some embodiments, any metal layer 15 includes one region Q or multiple regions Q, and each region Q has multiple metal wires 151 extending in the same direction and uniformly arranged in a direction intersecting (including perpendicular or oblique) the extending direction. In some embodiments of the present disclosure, the metal layer 15 of the representative volume element 13 is designed to include one or more regions Q, and any region Q has multiple metal wires 151 extending in the same direction and uniformly arranged in a direction intersecting the extending direction. In this way, the metal wires 151 in the representative volume element 13 are arranged in a certain regularity, which can reduce the complexity and cost of simulation calculations, and the metal wires 151 in the representative volume element 13 are distributed more uniformly, which is conducive to reducing the warping of the semiconductor structure.

[0062] In some embodiments, adjusting the wiring method of the metal wires 151 in at least one metal layer 15 includes adjusting the extension direction and / or arrangement direction of multiple metal wires 151 in at least one region Q in at least one metal layer 15, the number of regions Q, and the arrangement method of multiple regions Q.

[0063] like Figure 4 As shown in Figure (1), the metal layer 15 may include a region Q, and multiple metal wires 151 in the region Q extend along the same direction and are arranged in a direction intersecting their extension direction. The extension direction and arrangement direction of the multiple metal wires 151 can be adjusted, and the angle between the extension direction and the arrangement direction of the multiple metal wires 151 can vary between greater than 0° and less than or equal to 90°.

[0064] In some embodiments, when the metal layer 15 includes multiple regions Q, in any two regions Q in the metal layer 15, the extension direction of the multiple metal wires 151 in one region Q can be the same as or intersect (including perpendicular or oblique) with the extension direction of the multiple metal wires 151 in another region Q, and the arrangement direction of the multiple metal wires 151 in one region Q can be the same as or intersect (including perpendicular or oblique) with the arrangement direction of the multiple metal wires 151 in another region Q. The extension direction and arrangement direction of the multiple metal wires 151 in any one or more regions Q in one or more metal layers 15 can be adjusted, and the angle between the extension direction and the arrangement direction of the multiple metal wires 151 can vary between greater than 0° and less than or equal to 90°.

[0065] Figure 4Figures (2) to (4) are examples of different arrangements of metal wires 151 when the metal layer 15 includes four regions Q arranged in a 2×2 array. In fact, the multiple metal wires 151 in the four regions Q may also have other arrangements. In addition, the number and arrangement of regions Q in any metal layer 15 may also be adjusted. Any metal layer 15 may also include a greater or lesser number of regions Q, such as 2 regions Q arranged in a 1×2 array, 3 regions Q arranged in a 1×3 array, 6 regions Q arranged in a 2×3 array, 9 regions Q arranged in a 3×3 array, etc.

[0066] Next, step S102 is executed to respectively establish a plurality of first finite element simulation models for the plurality of representative volume elements 13 , and respectively obtain equivalent material properties of the plurality of first finite element simulation models.

[0067] The multiple representative volume elements 13 here refer to multiple representative volume elements 13 with different wiring modes of metal wires 151. In some embodiments, a first finite element simulation model can be established for the representative volume element 13 by finite element simulation software. Specifically, the first finite element simulation model can be established based on the geometric figure, material characteristic parameters and other properties of the representative volume element 13. Here, the material characteristic parameters include elastic modulus, Poisson's ratio, thermal expansion coefficient, thermal conductivity, heat capacity and other parameters of the metal wire 151, dielectric layer 12, plug and other materials in the representative volume element 13.

[0068] In some embodiments, obtaining the equivalent material properties of the first finite element simulation model includes obtaining parameters such as an equivalent modulus, an equivalent Poisson's ratio, and an equivalent thermal expansion coefficient of the first finite element simulation model by performing simulation calculations using finite element simulation software.

[0069] In some embodiments, respectively obtaining equivalent material properties of a plurality of first finite element simulation models includes:

[0070] Apply stress to each first finite element simulation model along multiple directions respectively, and perform finite element simulation calculation to obtain a first strain of each first finite element simulation model in the stress direction;

[0071] Based on the applied stress and the first strain of the first finite element simulation model, an equivalent elastic modulus and a Poisson's ratio of each first finite element simulation model in multiple directions are obtained.

[0072] like Figure 5As shown, in some embodiments, the shape of the first finite element simulation model is the same as the shape of the representative volume element 13, the shape of the first finite element simulation model includes a cuboid (including a cube with equal side lengths), the shape of the first finite element simulation model includes a cuboid, a surface of the cuboid parallel to the substrate plane includes vertex A, vertex B, vertex C, and vertex D, wherein vertex A and vertex B are adjacent in a straight line, vertex A and vertex C are adjacent diagonally, and vertex B and vertex D are adjacent diagonally, and the direction from vertex A to vertex B is defined as the x-axis direction, the direction from vertex A to vertex D is defined as the y-axis direction, and the direction perpendicular to the x-axis direction and the y-axis direction is defined as the z-axis direction; stress is applied to the first finite element simulation model along multiple directions, including: stress is applied to the first finite element simulation model along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction, and the third direction; wherein the first direction is at an angle of 45° with the x-axis direction and the y-axis direction; the second direction is at an angle of 45° with the x-axis direction and the z-axis direction; and the third direction is at an angle of 45° with the y-axis direction and the z-axis direction. In this way, by applying stress to the first finite element simulation model along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction and the third direction respectively, the first strain of the first finite element simulation model in the multiple directions can be obtained, and then the elastic modulus of the first finite element simulation model in the multiple directions can be obtained, and the Poisson's ratio of the first finite element simulation model can be obtained according to the elastic modulus in the multiple directions, so that the material properties of the subsequently established second finite element simulation model are closer to the material properties of the actual semiconductor structure, thereby improving the accuracy of the second finite element simulation model.

[0073] In some embodiments, a finite element simulation calculation is performed to obtain a first strain in the stress direction of each first finite element simulation model, including: obtaining the strain in the stress direction of multiple tiny volume elements in the first finite element simulation model; then, by integrating the ratio of the stress borne by the multiple tiny volume elements to the strain in the stress direction, the equivalent elastic modulus of the first finite element simulation model can be obtained.

[0074] In some embodiments, the equivalent elastic modulus of the first finite element simulation model in any direction can be calculated according to the following relationship (1):

[0075]

[0076] Among them, V m is the volume of the first finite element simulation model, dV m is the integral variable, which refers to the small volume element during integration, σ S When stress is applied to the first finite element simulation model along any direction, the small volume element dV in the first finite element simulation model m The stress borne, εS1 is a small volume element dV m At stress σ S The strain generated along the stress direction under the action of is the equivalent stress applied to the first finite element simulation model, is the equivalent strain along the stress direction of the first finite element simulation model.

[0077] Any direction here includes but is not limited to any direction along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction and the third direction. In some embodiments, stress is applied to the first finite element simulation model along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction and the third direction, and a finite element simulation calculation is performed to obtain the strains generated by the first finite element simulation model along the above multiple directions, and then the equivalent elastic modulus of the first finite element simulation model in the above multiple directions is obtained according to the above relationship (1), and then the equivalent Poisson's ratio of the first finite element simulation model in the above multiple directions is calculated according to the equivalent elastic modulus of the first finite element simulation model in different directions.

[0078] In some embodiments, when simulating the application of stress to the first finite element simulation model to calculate its first strain along the stress direction, the first finite element simulation model can be set to have only strain along the stress direction, and its strain along other directions except the stress direction can be set to 0. By adding this constraint condition, the complexity and cost of the simulation calculation can be reduced.

[0079] In some embodiments, respectively obtaining equivalent material properties of a plurality of first finite element simulation models further includes:

[0080] Applying thermal loads to each first finite element simulation model along multiple directions respectively, and performing finite element simulation calculation to obtain the temperature change of each first finite element simulation model and the second strain along the thermal load direction;

[0081] Based on the applied thermal load, temperature change and second strain, an equivalent thermal expansion coefficient of each first finite element simulation model in multiple directions is obtained.

[0082] In some embodiments, a finite element simulation calculation is performed to obtain the temperature change of each first finite element simulation model and the second strain along the direction of the thermal load, including: obtaining the temperature change of multiple tiny volume elements in the first finite element simulation model and the strain in the direction of the thermal load; then, by integrating the ratio of the strain of the multiple tiny volume elements in the direction of the thermal load to the temperature change, the equivalent thermal expansion coefficient of the first finite element simulation model can be obtained.

[0083] In some embodiments, when calculating the equivalent thermal expansion coefficient of the first finite element simulation model, the representative volume element 13 may be defined as a free expansion cycle type. Specifically, the equivalent thermal expansion coefficient of the first finite element simulation model in any direction may be obtained according to the following relationship (2):

[0084]

[0085] Among them, V m is the volume of the first finite element simulation model, dV m is the integral variable, which refers to the small volume element during integration, ε S2 For a small volume unit dV m The deformation in the direction of thermal load when the temperature changes by ΔT.

[0086] Any direction here includes but is not limited to any direction along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction and the third direction. In some embodiments, a thermal load is applied to the first finite element simulation model along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction and the third direction, respectively, and then the equivalent thermal expansion coefficients of the first finite element simulation model in the above multiple directions are obtained according to the above relationship (2).

[0087] In some embodiments, when simulating the application of a thermal load to a first finite element simulation model to calculate its second strain along the direction of the thermal load, the first finite element simulation model can be set to have only the strain along the direction of the thermal load, and its strain along other directions except the direction of the thermal load can be set to 0. By adding this constraint condition, the complexity and cost of the simulation calculation can be reduced.

[0088] But not limited to this, in some embodiments, respectively obtaining equivalent material properties of multiple first finite element simulation models also includes respectively obtaining equivalent thermal conductivity, equivalent heat capacity and other material properties of multiple first finite element simulation models.

[0089] Next, execute step S103, establish multiple second finite element simulation models for the designed semiconductor structure based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate 10, and simulate the warping deformation of the multiple second finite element simulation models during and after the heat treatment process.

[0090] A plurality of minimum repeatable volume units 12 are periodically arranged to constitute an interconnection layer 11 of a semiconductor structure. Therefore, by taking the minimum repeatable volume unit 12 as a representative volume element 13 and modeling it, the equivalent material properties of the representative volume element 13 are obtained, and thus the equivalent material properties of the interconnection layer 11 can be obtained. Then, based on the equivalent material properties of the representative volume element 13, the material properties of the substrate 10, and parameters such as the geometric figures of the interconnection layer 11 and the substrate 10, a second simulation model of the semiconductor structure can be established using finite element simulation software. Compared with modeling all metal patterns in the entire interconnection layer 11, this saves simulation calculation complexity and cost.

[0091] Here, the material properties of the substrate 10 include parameters such as elastic modulus, Poisson's ratio, thermal expansion coefficient, thermal conductivity, and heat capacity of the substrate 10. In some embodiments, the substrate 10 also includes a device structure (not shown) formed on the surface and / or inside the substrate 10, and the material properties of the substrate 10 and the device structure formed on the surface and / or inside the substrate 10 can be equivalent to the properties of the material of the substrate 10 itself. For example, when the material of the substrate 10 is silicon, the material properties of the substrate 10 and the device structure formed on the surface and / or inside the substrate 10 can be equivalent to the material properties of silicon.

[0092] In some embodiments, matching heat treatment parameters such as annealing temperature, heating rate, holding time, etc. can be set in the second finite element simulation model according to the actual heat treatment process parameters and boundary conditions of the semiconductor structure, and simulation calculations can be performed through finite element simulation software to simulate the warping deformation of the second finite element simulation model during and after the heat treatment process.

[0093] In some embodiments, simulating the warping deformation of the second finite element simulation model during and after the heat treatment process also includes: post-processing and analyzing the warping deformation obtained by simulation to extract key characteristic parameters of the warping of the second finite element simulation model, such as the maximum warping amount, warping direction, and warping area distribution. Figure 6 1 is a diagram showing the warpage distribution of a semiconductor structure along the z-axis direction after undergoing a heat treatment process obtained by simulation in one embodiment of the present disclosure.

[0094] In some embodiments, the wiring method of the metal wire 151 in the representative volume element 13 can also be adjusted according to the warping deformation obtained by simulation, and then steps S102 and S103 are performed again. In this way, the wiring method of the metal wire 151 in the representative volume element 13 can be adjusted in a targeted manner to reduce the warping of the semiconductor structure after heat treatment.

[0095] In this way, by analyzing and comparing the warping deformation of semiconductor structures with different metal wiring methods, the metal wiring method with the lowest warping value can be screened out.

[0096] It can be seen that the embodiment of the present disclosure adjusts the wiring method of the metal wire 151 within the representative volume element 13 and establishes a first simulation model for the representative volume element 13, so as to obtain the equivalent material properties of the representative volume element 13 with different wiring methods of the metal wire 151, and then establishes multiple second simulation models based on the equivalent material properties of the multiple representative volume elements 13 and the material properties of the substrate, and obtains the warping deformation conditions of the multiple second simulation models. In this way, the warping deformation conditions of the semiconductor structure when having different metal wiring methods can be obtained, so that the metal wiring method with the lowest warping value can be screened out from the limited metal wiring methods, thereby achieving effective adjustment and control of the warping deformation of the semiconductor structure and improving the success rate of subsequent bonding and packaging processes.

[0097] Here, the lowest warpage value may be that the second simulation model has the lowest overall warpage value in all directions, or has the lowest average warpage value in all directions.

[0098] It should be noted that those skilled in the art can change the order of the above steps without departing from the protection scope of the present disclosure.

[0099] The present disclosure also provides a design device 21 for a semiconductor structure, such as Figure 7 As shown, it includes: a memory 22, a processor 24, and a computer program 23 stored in the memory 22 and executable on the processor 24. When the processor 24 executes the computer program 23, a design method provided by the above-mentioned embodiments is implemented, such as: adjusting the wiring method of the metal wires in the representative volume element to obtain multiple representative volume elements with different metal wire wiring methods; establishing multiple first finite element simulation models for the multiple representative volume elements, and respectively obtaining the equivalent material properties of the multiple first finite element simulation models; establishing multiple second finite element simulation models for the semiconductor structure to be designed based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate, and simulating the warping deformation of the multiple second finite element simulation models during the process and after the heat treatment process.

[0100] The present disclosure also provides a computer-readable storage medium 25, such as Figure 8As shown, a computer program 26 is stored on the computer-readable storage medium 25. When the computer program 26 is executed by the processor, a design method for a semiconductor structure provided by the above-mentioned embodiments is implemented, such as: adjusting the wiring method of the metal wires in the representative volume element to obtain multiple representative volume elements with different metal wire wiring methods; establishing multiple first finite element simulation models for the multiple representative volume elements, and respectively obtaining equivalent material properties of the multiple first finite element simulation models; establishing multiple second finite element simulation models for the semiconductor structure to be designed based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate, and simulating the warping deformation of the multiple second finite element simulation models during and after the heat treatment process.

[0101] It should be noted that the above is only an optional embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for designing a semiconductor structure, characterized in that: The semiconductor structure to be designed includes a substrate and an interconnection layer located on the substrate, the interconnection layer includes a plurality of periodically arranged minimum repeatable volume units, the minimum repeatable volume unit is used as a representative volume element of the interconnection layer, the representative volume element includes an interlayer dielectric layer and a plurality of metal wires located in the interlayer dielectric layer; the design method includes: Adjusting the wiring mode of the metal wires in the representative volume element to obtain a plurality of representative volume elements with different wiring modes of the metal wires; Establishing a plurality of first finite element simulation models for the plurality of representative volume elements respectively, and obtaining equivalent material properties of the plurality of first finite element simulation models respectively; Based on the equivalent material properties of the multiple first finite element simulation models and the material properties of the substrate, multiple second finite element simulation models are established for the semiconductor structure to be designed, and the warping deformation of the multiple second finite element simulation models during and after the heat treatment process is simulated.

2. The design method according to claim 1, characterized in that: The representative volume element includes multiple metal layers located in the interlayer dielectric layer, and any of the metal layers includes at least one metal line extending in a direction parallel to the substrate plane; Adjusting the wiring mode of the metal wires in the representative volume element includes: Adjust the wiring mode of the metal lines in at least one of the metal layers.

3. The design method according to claim 2, characterized in that: Any of the metal layers includes one region or a plurality of regions, and each region has a plurality of metal wires extending in the same direction and uniformly arranged in a direction intersecting the extending direction.

4. The design method according to claim 1, characterized in that: Respectively obtaining equivalent material properties of a plurality of the first finite element simulation models, including: Apply stress to each of the first finite element simulation models along multiple directions respectively, and perform finite element simulation calculation to obtain a first strain of each of the first finite element simulation models in the stress direction; Based on the applied stress and the first strain of the first finite element simulation model, an equivalent elastic modulus and a Poisson's ratio of each of the first finite element simulation models in the multiple directions are obtained.

5. The design method according to claim 4, characterized in that: The equivalent elastic modulus of the first finite element simulation model in any direction is calculated according to the following relationship (1): Among them, V m is the volume of the first finite element simulation model, dV m is the integral variable, which refers to the small volume element during integration, σ S When stress is applied to the first finite element simulation model along any direction, the small volume element dV in the first finite element simulation model m The stress borne, ε S1 is the tiny volume element dV m At stress σ S The strain generated along the stress direction under the action of is the equivalent stress applied to the first finite element simulation model, is the equivalent strain of the first finite element simulation model along the stress direction.

6. The design method according to claim 4, characterized in that: Respectively obtaining equivalent material properties of a plurality of the first finite element simulation models further includes: Applying thermal loads to each of the first finite element simulation models along multiple directions respectively, and performing finite element simulation calculations to obtain temperature changes of each of the first finite element simulation models and second strains along the thermal load directions; Based on the applied thermal load, the temperature change, and the second strain, an equivalent thermal expansion coefficient of each of the first finite element simulation models in the multiple directions is obtained.

7. The design method according to claim 6, characterized in that: The equivalent thermal expansion coefficient of the first finite element simulation model in any direction is obtained according to the following relationship (2): Among them, V m is the volume of the first finite element simulation model, dV m is the integral variable, which refers to the small volume element during integration, ε S2 For a small volume unit dV m The strain generated along the direction of the thermal load when the temperature changes by ΔT.

8. The design method according to claim 6, characterized in that: The shape of the first finite element simulation model includes a cuboid, a surface of the cuboid parallel to the substrate plane includes vertices A, B, C, and D, wherein vertices A and B are adjacent in a straight line, vertices A and C are adjacent diagonally, and vertices B and D are adjacent diagonally, and the direction from vertex A to vertex B is defined as the x-axis direction, the direction from vertex A to vertex D is defined as the y-axis direction, and the direction perpendicular to the x-axis direction and the y-axis direction is defined as the z-axis direction; applying stress and thermal load to the first finite element simulation model along multiple directions respectively, including: Stress and thermal load are applied to the first finite element simulation model along the x-axis direction, the y-axis direction, the z-axis direction, the first direction, the second direction and the third direction respectively; wherein the first direction forms an angle of 45° with the x-axis direction and the y-axis direction; the second direction forms an angle of 45° with the x-axis direction and the z-axis direction; and the third direction forms an angle of 45° with the y-axis direction and the z-axis direction.

9. A design device for a semiconductor structure, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the design method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the design method according to any one of claims 1 to 8 is implemented.

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