Signal processing device and neural signal acquisition system

Abstract

The invention discloses a signal processing device and a neural signal acquisition system.The signal processing device comprises an FPGA processing unit and a single-chip microcomputer processing unit, the FPGA processing unit is suitable for being connected with an analog front-end chip, and the analog front-end chip is an RHD2164 chip; the single-chip microcomputer processing unit is connected with the FPGA processing unit and the upper computer. Wherein the FPGA processing unit is used for realizing interface protocol conversion of transmission signals between the single-chip microcomputer processing unit and the analog front-end chip and realizing signal preprocessing of the transmission signals between the single-chip microcomputer processing unit and the analog front-end chip; the single-chip microcomputer processing unit is used for analyzing and processing signals transmitted between the FPGA processing unit and an upper computer. The signal processing device has the advantages of being short in development period, low in power consumption, small in circuit area, accurate in resource evaluation, good in function reusability, suitable for rapid iteration and the like, is more suitable for implantable equipment, and can achieve neural signal processing with lower power consumption and convenient development.

Description

Technical Field

[0001] The present invention relates to the technical field of neural signal acquisition, and in particular to a signal processing device and a neural signal acquisition system. Background Art

[0002] In the related technology, the traditional neural signal acquisition solution realizes neural signal acquisition and data processing by using FPGA (Field Programmable Gate Array) chip alone. It has problems such as difficult to evaluate logic resources, large circuit area, excessive power consumption, long development cycle, slow iteration, and poor functional reuse. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the first purpose of the present invention is to propose a signal processing device with the characteristics of short development cycle, low overall system power consumption, small circuit area, accurate resource evaluation, good functional reusability, and suitability for rapid iteration, and is more suitable for implantable devices, and can achieve lower power consumption neural signal processing and convenient development.

[0004] The second object of the present invention is to provide a neural signal acquisition system.

[0005] In order to achieve the above-mentioned purpose, the signal processing device proposed in the embodiment of the first aspect of the present invention includes: an FPGA processing unit, the FPGA processing unit is suitable for connecting to an analog front-end chip, wherein the analog front-end chip is an RHD2164 chip; a single-chip microcomputer processing unit, the single-chip microcomputer processing unit is connected to the FPGA processing unit and a host computer; wherein the FPGA processing unit is used to realize interface protocol conversion of signals transmitted between the single-chip microcomputer processing unit and the analog front-end chip, and to realize signal preprocessing of signals transmitted between the single-chip microcomputer processing unit and the analog front-end chip; the single-chip microcomputer processing unit is used to realize signal analysis and processing of signals transmitted between the FPGA processing unit and the host computer.

[0006] According to the signal processing device proposed in the embodiment of the present invention, the FPGA processing unit is connected to the analog front-end chip and the single-chip microcomputer processing unit, and is used to realize the interface protocol conversion of the signal transmitted between the single-chip microcomputer processing unit and the analog front-end chip, and realize the signal preprocessing of the signal transmitted between the single-chip microcomputer processing unit and the analog front-end chip, so that the single-chip microcomputer processing unit can communicate with the analog front-end chip, and further use the single-chip microcomputer processing unit to realize the signal analysis and processing of the signal transmitted between the FPGA processing unit and the host computer. Therefore, on the basis of retaining the original signal preprocessing function of the FPGA processing unit, the present application uses the single-chip microcomputer processing unit to realize the signal analysis and processing function, so that the FPGA processing unit and the single-chip microcomputer processing unit cooperate with each other to jointly realize the processing of neural signals. Moreover, compared with only using the FPGA chip to realize the neural signal acquisition and data processing functions, the single-chip microcomputer used in the present application has a short development cycle, lower overall system power consumption, smaller circuit area, and is more suitable for implantable devices, effectively solving the problems of long development cycle and slow iteration caused by using the FPGA processing unit alone for data processing.

[0007] In some embodiments of the present invention, the communication port of the single-chip processing unit adopts an SPI interface, the communication port of the analog front-end chip adopts a DDR interface, and the FPGA processing unit is specifically used to convert the original neural signal sent by the analog front-end chip from a DDR data protocol format to an SPI data protocol format.

[0008] In some embodiments of the present invention, the FPGA processing unit includes: a mode control module, the input end of the mode control module is connected to the single-chip processing unit, and is used to receive a first digital signal sent by the single-chip processing unit, and the first digital signal carries mode processing information; a first receiving module, the input end of the first receiving module is suitable for connecting to the analog front-end chip to receive the original neural signal sent by the analog front-end chip, and perform interface protocol conversion on the original neural signal; a data processing module, the input end of the data processing module is connected to the mode control module and the first receiving module, the output end of the data processing module is connected to the single-chip processing unit, and the data processing module is used to perform signal preprocessing on the converted original neural signal according to the mode processing information, and send the preprocessed original neural signal to the single-chip processing unit.

[0009] In some embodiments of the present invention, the single-chip microcomputer processing unit includes at least one single-chip microcomputer, wherein, when the single-chip microcomputer processing unit includes one single-chip microcomputer, the single-chip microcomputer is used to manage the signal analysis and processing of the transmission signals between all analog front-end chips and the host computer, or, when the single-chip microcomputer processing unit includes multiple single-chip microcomputers, each single-chip microcomputer is used to manage the signal analysis and processing of the transmission signals between the corresponding part of the analog front-end chips and the host computer.

[0010] In some embodiments of the present invention, the single-chip microcomputer includes: an uplink communication port, which is connected to the host computer via a serial bus, and the uplink communication port is used to realize signal transmission between the single-chip microcomputer processing unit and the host computer; a downlink communication port, which is connected to the FPGA processing module, and the downlink communication port is used to realize signal transmission between the single-chip microcomputer processing unit and the FPGA processing unit; a signal processing module, which is connected to the uplink communication port and the downlink communication port, and the signal processing module is used to realize signal analysis and processing of signals transmitted between the FPGA processing unit and the host computer.

[0011] In some embodiments of the present invention, the FPGA processing unit includes a mode control port, an uplink sending port and an uplink receiving port, and the mode control port is connected to the input end of the mode control module; the single-chip microcomputer processing unit includes a single-chip microcomputer, and the downlink communication port of the single-chip microcomputer includes a downlink control port, a downlink sending port and a downlink receiving port, the downlink control port is connected to the mode control port, the downlink sending port is connected to the uplink receiving port of the FPGA processing unit so that the FPGA processing unit forwards the downlink signal of the single-chip microcomputer to the analog front-end chip, and the downlink receiving port is connected to the uplink sending port of the FPGA processing unit.

[0012] In some embodiments of the present invention, the FPGA processing unit includes a mode control port and an upstream sending port, and the mode control port is connected to the input end of the mode control module; the single-chip microcomputer processing unit includes a single-chip microcomputer, and the downstream communication port of the single-chip microcomputer includes a downstream control port, a downstream sending port and a downstream receiving port, the downstream control port is connected to the mode control port, the downstream sending port is connected to the receiving port of the analog front-end chip to send a downstream signal to the analog front-end chip, and the downstream receiving port is connected to the upstream sending port of the FPGA processing unit.

[0013] In some embodiments of the present invention, the FPGA processing unit includes a mode control port, an upstream sending port and an upstream receiving port, the mode control port is connected to the input end of the mode control module, the single-chip microcomputer processing unit includes multiple single-chip microcomputers, and the multiple single-chip microcomputers include: a master single-chip microcomputer, the downstream communication port of the master single-chip microcomputer includes a downstream control port, a downstream sending port and a first downstream receiving port, the downstream control port of the master single-chip microcomputer is connected to the mode control port, the downstream sending port of the master single-chip microcomputer is connected to the upstream receiving port of the FPGA processing unit so that the FPGA processing unit forwards the downstream signal of the single-chip microcomputer to the analog front-end chip, and the first downstream receiving port of the master single-chip microcomputer is connected to the upstream sending port of the FPGA processing unit; at least one slave single-chip microcomputer, the downstream communication port of the slave single-chip microcomputer includes a second downstream receiving port, and the second downstream receiving port of the slave single-chip microcomputer is connected to the upstream sending port of the FPGA processing unit.

[0014] In some embodiments of the present invention, the FPGA processing unit includes a mode control port and an upstream sending port, the mode control port is connected to the input end of the mode control module, the single-chip microcomputer processing unit includes multiple single-chip microcomputers, and the multiple single-chip microcomputers include: a master single-chip microcomputer, the downstream communication port of the master single-chip microcomputer includes a downstream control port, a downstream sending port and a first downstream receiving port, the downstream control port of the master single-chip microcomputer is connected to the mode control port, the downstream sending port of the master single-chip microcomputer is connected to the receiving port of the analog front-end chip to send a downstream signal to the analog front-end chip, and the first downstream receiving port of the master single-chip microcomputer is connected to the upstream sending port of the FPGA processing unit; at least one slave single-chip microcomputer, the downstream communication port of the slave single-chip microcomputer includes a second downstream receiving port, and the second downstream receiving port of the slave single-chip microcomputer is connected to the upstream sending port of the FPGA processing unit.

[0015] In some embodiments of the present invention, the FPGA processing unit also includes: an asynchronous FIFO module, the input end of the asynchronous FIFO module is connected to the upstream receiving port of the FPGA processing unit, the asynchronous FIFO module is connected to the analog front-end chip through the downstream sending port of the FPGA processing unit, and the asynchronous FIFO module is used to asynchronously transmit and cache the downstream signal; wherein, the mode control module is also used to receive a second digital signal sent by the single-chip processing unit, the second digital signal carries at least one or more of data format information and data transmission ID information, and the output end of the mode control module is also connected to the downstream sending port of the FPGA processing unit to send the second digital signal through the downstream sending port, wherein the data format information is a 16-bit data format or an 8-bit data format.

[0016] In order to achieve the above-mentioned purpose, the neural signal acquisition system proposed in the second aspect of the embodiment of the present invention includes: at least one analog front-end chip, which is an RHD2164 chip; and the signal processing device described in any of the above embodiments, which is connected to the analog front-end chip.

[0017] According to the neural signal acquisition system proposed in the embodiment of the present invention, based on the connection between the signal processing device and the analog front-end chip, the signal processing device can perform neural signal acquisition and signal analysis processing on the analog front-end chip. The signal processing device uses a processing unit to realize interface protocol conversion and signal preprocessing of the signal transmitted between the single-chip processing unit and the analog front-end chip, and then uses the single-chip processing unit to perform signal analysis processing. Compared with the use of FPGA chip alone to realize neural signal acquisition and data processing functions, it has the characteristics of short development cycle, low overall system power consumption, small circuit area, accurate resource evaluation, good functional reusability, and suitability for rapid iteration. It is more suitable for implantable devices and can achieve lower power consumption neural signal processing and convenient development.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a block diagram of a signal processing device according to an embodiment of the present invention; Figure 2 A timing diagram of a DDR interface according to an embodiment of the present invention; Figure 3 A timing diagram of a standard SPI interface according to an embodiment of the present invention; Figure 4 A block diagram of an FPGA processing unit according to an embodiment of the present invention; Figure 5 A block diagram of a connection between a single single-chip microcomputer and an FPGA processing unit according to an embodiment of the present invention; Figure 6 A block diagram of a connection between a single single-chip microcomputer and an FPGA processing unit according to another embodiment of the present invention; Figure 7 A block diagram of the connection between multiple single-chip microcomputers and an FPGA processing unit according to an embodiment of the present invention; Figure 8 A block diagram of the connection between multiple single-chip microcomputers and an FPGA processing unit according to another embodiment of the present invention; Fig. 9 A block diagram of an FPGA processing unit according to another embodiment of the present invention; Fig.10 FIG. 4 is a block diagram of a neural signal acquisition system according to an embodiment of the present invention.

[0020] Reference numerals: A signal processing device 100; Neural signal acquisition system 1000; FPGA processing unit 10, single chip processing unit 20, analog front end chip 30, host computer 40; Mode control module 11, first receiving module 12, data processing module 13, asynchronous FIFO module 14, downlink sending port 15 of FPGA processing unit, mode control port 16, uplink receiving port 17, uplink sending port 18; Single chip microcomputer 2, master single chip microcomputer 21, slave single chip microcomputer 22. DETAILED DESCRIPTION

[0021] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0022] In the related technology, FPGA processing units are used alone to realize neural signal acquisition and data processing functions. Specifically, the FPGA chips that meet the requirements are all chips from many years ago. The general processing technology of the chips remains at 130nm, and the low-power performance is poor. The logic units of low-power FPGA chips are insufficient and cannot meet the logical scale of high-throughput neural signal acquisition. In addition, the FPGA system can determine the required logic resource size only after completing all functional designs. Usually, small-packaged chips have insufficient logic resources and require larger chips, resulting in an increase in system design area and power consumption. Secondly, FPGA-based system design requires precise digital logic, a long development cycle, poor functional reuse, and small changes in requirements will also lead to a lot of redesign, which is not suitable for rapid iteration.

[0023] In order to solve the above problems, the first aspect of the embodiment of the present invention proposes a signal processing device, which has the characteristics of short development cycle, low overall system power consumption, small circuit area, accurate resource evaluation, good functional reusability, and suitability for rapid iteration. It is more suitable for implantable devices and can achieve lower power consumption neural signal processing and convenient development.

[0024] Reference below Figure 1A signal processing device according to an embodiment of the present invention is described. The signal processing device 100 includes an FPGA processing unit 10 and a single-chip processing unit 20. The FPGA processing unit 10 is suitable for connecting to an analog front-end chip 30, wherein the analog front-end chip 30 is an RHD2164 chip; the single-chip processing unit 20 is connected to the FPGA processing unit 10 and a host computer 40; wherein the FPGA processing unit 10 is used to realize interface protocol conversion of signals transmitted between the single-chip processing unit 20 and the analog front-end chip 30, and to realize signal preprocessing of signals transmitted between the single-chip processing unit 20 and the analog front-end chip 30; the single-chip processing unit 20 is used to realize signal analysis and processing of signals transmitted between the FPGA processing unit 10 and the host computer 40.

[0025] Among them, the analog front-end chip 30 is used to collect neural signals, and the host computer 40 is used to display or record the neural signals after signal analysis and processing. The host computer 40 can be a PC, a mobile phone, an iPad, etc., which is not specifically limited here. The analog front-end chip 30 can be an Intan RHD2164 chip, the single-chip microcomputer processing unit 20 The single-chip microcomputer can be an STM32U5 series, and the FPGA processing unit 10 can use Lattice ice40LP series, Gaoyun GW1N series chips. Since the communication interface of the single-chip microcomputer processing unit 20 is an SPI interface, and the communication interface of the analog front-end chip 30 is a non-standard SPI interface, the interface protocols are different, so the single-chip microcomputer processing unit 20 and the analog front-end chip 30 cannot communicate directly. The FPGA processing unit 10 can be used to implement the interface protocol conversion of the signal transmitted between the single-chip processing unit 20 and the analog front-end chip 30. Specifically, the FPGA processing unit 10 can be used to write an interface that conforms to the acquisition logic of the analog front-end chip 30 to realize the acquisition of neural signals, thereby realizing the signal transmission between the single-chip processing unit 20 and the analog front-end chip 30, and then realizing the signal analysis and processing of the signal transmitted between the FPGA processing unit 10 and the host computer 40 using the single-chip processing unit 20. In some embodiments, a commonly used serial bus such as UART (Universal Asynchronous Receiver / Transmitter) or SPI (Serial Peripheral Interface) can be selected for data transmission between the host computer 40 and the single-chip processing unit 20.

[0026] Specifically, the prior art only relies on FPGA chips to implement the entire processing process of neural signals, namely signal preprocessing and signal analysis processing. Therefore, the system design based on FPGA requires precise digital logic, has a long development cycle, poor functional reuse, and even small changes in requirements will lead to a large number of redesigns, which is not suitable for rapid iteration. In response to the above problems, the present application designs an FPGA processing unit 10 and a single-chip microcomputer processing unit 20 to cooperate with each other to jointly implement the processing of neural signals, wherein the FPGA processing unit 10 retains a general processing function for signals, namely signal preprocessing. That is to say, signal preprocessing can be understood as some general functions that must be processed for all neural signals, such as basic processing processes such as data filtering, data smoothing, and threshold comparison. That is to say, usually all data must undergo signal preprocessing before subsequent signal analysis processing can be performed. Signal preprocessing is relatively simple and common, so the signal preprocessing function is implemented by the FPGA processing unit 10. This can reduce the subsequent frequent development and iteration of the FPGA processing unit 10 on the one hand, and reduce the logic resources on the FPGA processing unit 10 side on the other hand, and reduce the design area of ​​the FPGA processing unit 10, so that it can be suitable for FPGA chips with low power consumption and small and medium logic resources. At the same time, by utilizing the advantages of the single-chip microcomputer's C language programming development cycle, low overall system power consumption, and smaller circuit area, the more complex and special signal analysis and processing functions are implemented by the single-chip microcomputer processing unit 20, wherein the signal analysis and processing can be understood as a specific function of analyzing, processing, and applying the signal. That is to say, developers usually carry out specific development and design based on the final use requirements or iterative upgrade requirements of the neural signal, and different final use requirements or iterative upgrade requirements will have different signal analysis and processing processes. Therefore, in view of this situation, this application considers that the single-chip microcomputer resources are mainly on-chip RAM and Flash. Before the project starts, it can be evaluated to determine whether the selected chip meets the requirements to ensure that the upper limit of the system power consumption is clear and will not exceed expectations. Therefore, the single-chip microcomputer processing unit 20 is designed to undertake the signal analysis and processing function, thereby utilizing its advantages of fast programming development cycle, good functional reusability, and suitability for rapid iteration to solve the problem of slow iteration of FPGA chips. Therefore, when the requirements change or the functions are upgraded, there is no need to redesign the FPGA processing unit 10. Only the single-chip microcomputer processing unit 20 needs to be designed and developed to achieve rapid iteration of the system, greatly shortening the development cycle and improving functional reusability.

[0027] In some embodiments, the single-chip microcomputer processing unit 20 implements the main data processing functions. Compared with using the FPGA processing unit 10 alone to implement neural signal acquisition and data processing functions, modern low-power single-chip microcomputers use a 40nm process and run at a maximum clock of 160MHz. The performance is sufficient to process neural signals and has excellent low-power performance.

[0028] According to the signal processing device 100 proposed in the embodiment of the present invention, the FPGA processing unit 10 is connected to the analog front-end chip 30 and the single-chip processing unit 20, so as to realize the interface protocol conversion of the signal transmitted between the single-chip processing unit 20 and the analog front-end chip 30, and realize the signal preprocessing of the signal transmitted between the single-chip processing unit 20 and the analog front-end chip 30, so as to enable the single-chip processing unit 20 to communicate with the analog front-end chip 30, and further use the single-chip processing unit 20 to realize the signal analysis and processing of the signal transmitted between the FPGA processing unit 10 and the host computer 40, thereby, In this application, the FPGA processing unit 10 retains the original signal preprocessing function and utilizes the single-chip microcomputer processing unit 20 to realize the signal analysis and processing function, so that the FPGA processing unit 10 and the single-chip microcomputer processing unit 20 cooperate with each other to jointly realize the processing of neural signals. Moreover, compared with only using FPGA chips to realize neural signal acquisition and data processing functions, the single-chip microcomputer used in this application has a short development cycle, lower overall system power consumption, smaller circuit area, and is more suitable for implantable devices, effectively solving the problems of long development cycle and slow iteration caused by using the FPGA processing unit 10 alone for data processing.

[0029] In some embodiments of the present invention, the communication port of the single-chip processing unit 20 adopts an SPI interface, and the communication port of the analog front-end chip 30 adopts a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) interface. The FPGA processing unit 10 is specifically used to convert the original neural signal sent by the analog front-end chip 30 from the DDR data protocol format to the SPI data protocol format.

[0030] Specifically, refer to Figure 2 As shown in Figure 1, the characteristic of DDR timing is that on the 16 SCLK clocks, both the rising and falling edges will output data in MISO, and the first rising edge data is empty, and the last data is latched on the rising edge of CS; while the reference Figure 3 As shown, the characteristic of the standard SPI timing is that 16 clocks transmit 16 bits of data. Among them, when the DDR interface transmits data, group A data and group B data appear alternately by bit. Therefore, the data transmission timing of the DDR interface is different from the data transmission timing of the SPI interface. Therefore, the original neural signal sent by the analog front-end chip 30 is not convenient to be processed by the single-chip processing unit 20. Therefore, in this application, the original neural signal sent by the analog front-end chip 30 is converted from the DDR data protocol format to the SPI data protocol format through the FPGA processing unit 10, for example, referring to Figure 2 and Figure 3As shown, the original neural signal is converted from the DDR data protocol format of A0 B0 A1 B1...A15 B15 to the SPI data protocol format of A0 A1 A2...A15, B0B1 B2...B15, and then the original neural signal after protocol conversion is sent to the single-chip processing unit 20 to realize the signal transmission between the single-chip processing unit 20 and the analog front-end chip 30. Among them, when transmitting data, the MSB (Maxsignificant bit) is in front and the LSB (least significant bit) is in the back.

[0031] In some embodiments of the present invention, Figure 4 As shown, the FPGA processing unit 10 includes a mode control module 11, a first receiving module 12 and a data processing module 13. The input end of the mode control module 11 is connected to the single-chip processing unit 20, and is used to receive a first digital signal sent by the single-chip processing unit 20, and the first digital signal carries mode processing information; the input end of the first receiving module 12 is suitable for connecting to the analog front-end chip 30 to receive the original neural signal sent by the analog front-end chip 30, and to perform interface protocol conversion on the original neural signal; the input end of the data processing module 13 is connected to the mode control module 11 and the first receiving module 12, and the output end of the data processing module 13 is connected to the single-chip processing unit 20. The data processing module 13 is used to perform signal preprocessing on the converted original neural signal according to the mode processing information, and send the preprocessed original neural signal to the single-chip processing unit 20.

[0032] The mode processing information is the control signal sent by the single-chip processing unit 20. The data processing module 13 can perform signal preprocessing on the original neural signal according to the mode processing information, including selecting the data receiving format and selecting the data processing mode, wherein the data processing mode includes filtering, threshold comparison, original data mode, etc. Preprocessing is the signal processing process performed according to the mode processing information.

[0033] Exemplarily, the filtering mode is to filter the original neural signal as needed; the threshold comparison mode is to perform threshold comparison on the original neural signal, that is, first set the threshold range, and then compare the original neural signal with the threshold; the raw data mode is to directly output the original neural signal without processing the original neural signal.

[0034] In addition, the first receiving module 12 receives the original neural signal collected by the analog front-end chip 30, and performs interface protocol conversion on the original neural signal, for example, converting the non-standard SPI interface protocol (such as DDR interface) of the analog front-end chip 30 into an interface protocol recognizable by the single-chip microcomputer processing unit 20, such as the standard SPI interface protocol, so as to realize signal transmission between the analog front-end chip 30 and the single-chip microcomputer processing unit 20.

[0035] Specifically, the SPI protocol can be used for signal transmission between the single-chip microcomputer and the FPGA processing unit 10. The SPI protocol is suitable for a one-master-multiple-slave scenario, including four signal lines: SCLK, CS, MISO, and MOSI, where SCLK is a clock signal, CS is a chip select signal, MISO is a signal input by the host and output by the slave, and MOSI is a signal output by the host and input by the slave. When the single-chip microcomputer sends a signal to the FPGA processing unit 10, the single-chip microcomputer is in the master mode and the FPGA processing unit 10 is in the slave mode. When the single-chip microcomputer is in the master mode of SPI communication, the FPGA processing unit 10 and each analog front-end chip 30 share the SPI clock signal (SCLK) and the independent SPI chip select signal (CS) of each analog front-end chip 30; when the FPGA processing unit 10 sends a signal to the single-chip microcomputer, the FPGA processing unit 10 is in the master mode and the single-chip microcomputer is in the slave mode. The number of SPIs required is the same as the number of single-chip microcomputers, that is, each single-chip microcomputer requires an independent SPI interface.

[0036] In some embodiments of the present invention, the single-chip microcomputer processing unit 20 includes at least one single-chip microcomputer, wherein, when the single-chip microcomputer processing unit 20 includes one single-chip microcomputer, the single-chip microcomputer is used to manage the signal analysis and processing of the signals transmitted between all analog front-end chips 30 and the host computer 40, or, when the single-chip microcomputer processing unit 20 includes multiple single-chip microcomputers, each single-chip microcomputer is used to manage the signal analysis and processing of the signals transmitted between the corresponding part of the analog front-end chip 30 and the host computer 40.

[0037] Specifically, the FPGA processing unit 10 can be connected to one or more analog front-end chips 30, and can provide flexible expansion. In this regard, if a single single-chip microcomputer can independently assume the signal analysis and processing functions of multiple analog front-end chips 30, the single-chip microcomputer processing unit 20 can include a single-chip microcomputer, which manages the signal analysis and processing of signals transmitted between all analog front-end chips 30 and the host computer 40; or, if a single single-chip microcomputer cannot independently assume the signal analysis and processing functions of multiple analog front-end chips 30, the single-chip microcomputer processing unit 20 can include multiple single-chip microcomputers, and the multiple single-chip microcomputers can include a master single-chip microcomputer and a slave single-chip microcomputer, each of which can correspond to one or part of the analog front-end chip 30, that is, each single-chip microcomputer is used to manage the signal analysis and processing of signals transmitted between the corresponding part of the analog front-end chip 30 and the host computer 40, which can reduce the amount of signal analysis and processing required by each single-chip microcomputer and greatly improve the signal analysis and processing speed.

[0038] In some embodiments of the present invention, the single-chip microcomputer includes an uplink communication port, a downlink communication port and a signal processing module. The uplink communication port is connected to the host computer 40 via a serial bus, and the uplink communication port is used to realize signal transmission between the single-chip microcomputer processing unit 20 and the host computer 40; the downlink communication port is connected to the FPGA processing module, and the downlink communication port is used to realize signal transmission between the single-chip microcomputer processing unit 20 and the FPGA processing unit 10; the signal processing module is connected to the uplink communication port and the downlink communication port, and the signal processing module is used to realize signal analysis and processing of the signal transmitted between the FPGA processing unit 10 and the host computer 40.

[0039] Based on the above, the single-chip microcomputer can realize signal transmission between the single-chip microcomputer processing unit 20 and the host computer 40 through the uplink communication port, realize signal transmission between the single-chip microcomputer processing unit 20 and the FPGA processing unit 10 through the downlink communication port, and realize signal analysis and processing of the signal transmitted between the FPGA processing unit 10 and the host computer 40 by the signal processing module, and can send the neural signal after signal analysis and processing to the host computer 40 for subsequent analysis and use.

[0040] In some embodiments of the present invention, the FPGA processing unit 10 includes a mode control port, an uplink sending port and an uplink receiving port, and the mode control port is connected to the input end of the mode control module 11; the single-chip microcomputer processing unit 20 includes a single-chip microcomputer, and the downlink communication port of the single-chip microcomputer includes a downlink control port, a downlink sending port and a downlink receiving port, the downlink control port is connected to the mode control port, the downlink sending port is connected to the uplink receiving port of the FPGA processing unit 10 so that the FPGA processing unit 10 forwards the downlink signal of the single-chip microcomputer to the analog front-end chip 30, and the downlink receiving port is connected to the uplink sending port of the FPGA processing unit 10.

[0041] The mode control port may be a GPIO (General Purpose Input Output) port, or an additional SPI interface may be used to read and write registers to implement control of the internal mode of the FPGA processing unit 10 .

[0042] In some embodiments, since the port type used by the single-chip microcomputer is different from the interface type used by the analog front-end chip 30, there will be a problem of different interface data transmission timing. For example, taking the analog front-end chip 30 using a DDR interface and the single-chip microcomputer using an SPI interface as an example, the DDR interface sends data at the rising edge and the falling edge of the CLK clock at the same time, while the SPI interface usually sends data at the rising edge or the falling edge of the CLK clock, so the data transmission rate of the DDR interface is twice the data transmission rate of the ordinary SPI interface, so the CLK rate of the converted SPI interface must be at least 2 times that of the original DDR interface to ensure the real-time data transmission. Therefore, in order to be applicable to the situation where the SPI transmission timing of the single-chip microcomputer does not meet the timing requirements of the analog front-end chip 30, the present application sets the downlink communication port of the single-chip microcomputer to be directly connected to the port of the FPGA processing unit 10 in a one-to-one correspondence, that is, the FPGA processing unit 10 isolates the single-chip microcomputer from the analog front-end chip 30 in the middle. Specifically, the data acquisition of the analog front-end chip 30 includes two parts, namely, a sending part and a receiving part. When the sending timing of the single-chip microcomputer does not meet the timing requirements of the analog front-end chip 30, for example, when the single-chip microcomputer interface is a standard SPI interface and the analog front-end chip 30 is a DDR interface, the single-chip microcomputer and the analog front-end chip 30 cannot be directly connected, and the FPGA processing unit 10 is required to isolate the single-chip microcomputer processing unit 20 and the analog front-end chip 30 in the middle to realize the interface protocol conversion of the signal transmitted between the single-chip microcomputer processing unit 20 and the analog front-end chip 30. Further, the FPGA processing unit 10 can receive the signal that the single-chip microcomputer wants to send to the analog front-end chip 30 by setting the uplink receiving port.

[0043] It is understandable that when the number of analog front-end chips 30 is small or the amount of signal analysis and processing required is small, one single-chip microcomputer can realize all signal analysis and processing functions. In this case, one single-chip microcomputer can be used for signal analysis and processing, such as Figure 5As shown, for the case where the single-chip microcomputer processing unit 20 includes a single-chip microcomputer, signal transmission is performed between the single-chip microcomputer 2 and the analog front-end chip 30 through the FPGA processing unit 10, and the mode control port of the FPGA processing unit 10 is connected to the downlink control port of the single-chip microcomputer 2, so as to transmit the first digital signal sent by the single-chip microcomputer processing unit 20 to the mode control module 11; the uplink sending port of the FPGA processing unit 10 is connected to the downlink receiving port of the single-chip microcomputer 2, so as to transmit the original neural signal preprocessed by the data processing module 13 to the single-chip microcomputer 2 for subsequent signal processing and signal analysis; the uplink receiving port of the FPGA processing unit 10 is connected to the downlink sending port of the single-chip microcomputer 2, so as to forward the data from the single-chip microcomputer 2 directly to the analog front-end chip 30.

[0044] In some embodiments of the present invention, the FPGA processing unit 10 includes a mode control port and an upstream sending port, and the mode control port is connected to the input end of the mode control module 11; the single-chip microcomputer processing unit 20 includes a single-chip microcomputer, and the downstream communication port of the single-chip microcomputer includes a downstream control port, a downstream sending port and a downstream receiving port, the downstream control port is connected to the mode control port, the downstream sending port is connected to the receiving port of the analog front-end chip 30 to send a downstream signal to the analog front-end chip 30, and the downstream receiving port is connected to the upstream sending port of the FPGA processing unit 10.

[0045] Specifically, in the case where the data transmission timing of the single-chip microcomputer meets the data reception timing requirements of the analog front-end chip 30, the present application sets the downlink transmission port of the single-chip microcomputer to be directly connected to the analog front-end chip 30, so that the single-chip microcomputer can directly send a signal to the analog front-end chip 30 without the need for the FPGA processing unit 10 to receive and forward the data sent by the single-chip microcomputer. Figure 6 As shown, the downlink transmission port of the single chip computer 2 is connected to the receiving port of the analog front end chip 30 to send the downlink signal to the analog front end chip 30 .

[0046] In some embodiments of the present invention, the FPGA processing unit 10 includes a mode control port, an upstream sending port and an upstream receiving port, the mode control port is connected to the input end of the mode control module 11, the single-chip microcomputer processing unit 20 includes multiple single-chip microcomputers, and the multiple single-chip microcomputers include: a master single-chip microcomputer, the downstream communication port of the master single-chip microcomputer includes a downstream control port, a downstream sending port and a first downstream receiving port, the downstream control port of the master single-chip microcomputer is connected to the mode control port, the downstream sending port of the master single-chip microcomputer is connected to the upstream receiving port of the FPGA processing unit 10 so that the FPGA processing unit 10 forwards the downstream signal of the single-chip microcomputer to the analog front-end chip 30, and the first downstream receiving port of the master single-chip microcomputer is connected to the upstream sending port of the FPGA processing unit 10; at least one slave single-chip microcomputer, the downstream communication port of the slave single-chip microcomputer includes a second downstream receiving port, and the second downstream receiving port of the slave single-chip microcomputer is connected to the upstream sending port of the FPGA processing unit 10.

[0047] Among them, if the number of analog front-end chips 30 is large, more than one microcontroller may be needed to perform signal analysis and processing, one of which needs to be used as the master microcontroller, and the master microcontroller needs to be equipped with a sending module and a receiving module, and the remaining microcontrollers are slave microcontrollers, and the slave microcontrollers only need to be equipped with a receiving module.

[0048] In some embodiments, in order to be applicable to the situation where the SPI sending timing of the single-chip microcomputer does not meet the timing requirements of the analog front-end chip 30, the present application sets the downlink communication port of each single-chip microcomputer to be directly connected to the port of the FPGA processing unit 10 in a one-to-one correspondence, that is, the FPGA processing unit 10 isolates each single-chip microcomputer from the analog front-end chip 30 in the middle. Specifically, the signal transmission between the single-chip microcomputer processing unit 20 and the analog front-end chip 30 is performed through the FPGA processing unit 10, such as Figure 7 As shown, in the case where the single-chip microcomputer processing unit 20 includes multiple single-chip microcomputers, the main single-chip microcomputer 21 is used to manage the signal analysis and processing of the transmission signal between the analog front-end chip 30 and the host computer 40 and the sending of the control signal, while the slave single-chip microcomputer 22 is only used to manage the signal analysis and processing of the transmission signal between the corresponding analog front-end chip 30 and the host computer 40.

[0049] Furthermore, the mode control port of the FPGA processing unit 10 is internally connected to the input end of the mode control module 11 and externally connected to the downlink control port of the main single-chip microcomputer 21, so that the FPGA processing unit 10 receives the first digital signal sent by the main single-chip microcomputer 21 of the single-chip microcomputer processing unit 20; the uplink sending port of the FPGA processing unit 10 is connected to the first downlink receiving port of the main single-chip microcomputer 21 and the second downlink receiving port of the slave single-chip microcomputer 22, so as to forward the original neural signal from the analog front-end chip 30 to the corresponding single-chip microcomputer, thereby realizing the signal analysis and processing of the transmission signal between each single-chip microcomputer managing the corresponding analog front-end chip 30 and the host computer 40; the uplink receiving port of the FPGA processing unit 10 is connected to the downlink sending port of the main single-chip microcomputer 21, so as to receive the downlink signal of the main single-chip microcomputer 21 and transmit it to the asynchronous FIFO module, thereby realizing the forwarding of the downlink signal of the main single-chip microcomputer 21 to the analog front-end chip 30.

[0050] In some embodiments of the present invention, Figure 4 As shown, the FPGA processing unit 10 includes a mode control port 16 and an uplink sending port 18, the mode control port 16 is connected to the input end of the mode control module 11, the single-chip processing unit 20 includes multiple single-chips, and the multiple single-chips include: a master single-chip 21, the downlink communication port of the master single-chip 21 includes a downlink control port, a downlink sending port and a first downlink receiving port, the downlink control port of the master single-chip 21 is connected to the mode control port 16, the downlink sending port of the master single-chip 21 is connected to the receiving port of the analog front-end chip 30 to send a downlink signal to the analog front-end chip 30, and the first downlink receiving port of the master single-chip 21 is connected to the uplink sending port 18 of the FPGA processing unit 10; at least one slave single-chip 22, the downlink communication port of the slave single-chip 22 includes a second downlink receiving port, and the second downlink receiving port of the slave single-chip 22 is connected to the uplink sending port 18 of the FPGA processing unit 10.

[0051] Specifically, in the case where the data transmission timing of the single-chip microcomputer meets the data reception timing requirements of the analog front-end chip 30, the present application sets a downlink transmission port of the main single-chip microcomputer 21 and the analog front-end chip 30 so that signals can be directly transmitted. When the single-chip microcomputer processing unit 20 includes multiple single-chip microcomputers, reference Figure 8As shown, the mode control port 16 is connected to the downstream control port of the main single-chip microcomputer 21, and is used to receive the first digital signal sent by the main single-chip microcomputer 21; the upstream sending port 18 of the FPGA processing unit 10 is connected to the first downstream receiving port of the main single-chip microcomputer 21 and the second downstream receiving port of the slave single-chip microcomputer 22, and is used to forward the original neural signal from the analog front-end chip 30 to the corresponding single-chip microcomputer, thereby realizing the signal analysis and processing of the transmission signal between each single-chip microcomputer managing the corresponding analog front-end chip 30 and the host computer 40; the downstream sending port of the main single-chip microcomputer 21 is directly connected to the analog front-end chip 30, which can realize the signal transmission from the main single-chip microcomputer 21 to the analog front-end chip 30.

[0052] In some embodiments of the present invention, the FPGA processing unit 10 further includes an asynchronous FIFO (First in First out) module, such as Fig. 9 As shown, the input end of the asynchronous FIFO module 14 is connected to the uplink receiving port 17 of the FPGA processing unit 10, and the asynchronous FIFO module 14 is connected to the analog front-end chip 30 through the downlink sending port 15 of the FPGA processing unit. The asynchronous FIFO module 14 is used to asynchronously transmit and cache the downlink signal; wherein, the mode control module 11 is also used to receive a second digital signal sent by the single-chip processing unit 20, and the second digital signal carries at least one or more of data format information and data transmission ID (Identity document) information, and the output end of the mode control module 11 is also connected to the downlink sending port 15 of the FPGA processing unit to send the second digital signal through the downlink sending port 15, wherein the data format information is a 16-bit data format or an 8-bit data format.

[0053] Among them, the data format information is the data format input to the single-chip processing unit 20, which can be 16 bits or 8 bits. The data format of the original neural signal of the analog front-end chip 30 is 16 bits, and the data format can be selected through the mode control port 16, and then the data processing module 13 realizes the processing of the original neural signal according to the data format information. For example, the same 16-bit data format as the original neural signal can be selected, or the data format of the original neural signal can be converted into 8 bits through the data processing module 13. The data transmission ID information is the ID information of the analog front-end chip. Each analog front-end chip 30 has a unique ID information corresponding to it. The FPGA processing unit 10 can send data to all or specified analog front-end chips 30 according to the data transmission ID information. The output end of the mode control module 11 is also connected to the downstream sending port 15 of the FPGA processing unit, which can be used to forward the second digital signal to the analog front-end chip 30 to realize data transmission for all or specified analog front-end chips 30.

[0054] Specifically, when the FPGA processing unit 10 includes a mode control port 16, an uplink sending port 18 and an uplink receiving port 17, the asynchronous FIFO module 14 receives data sent by the single-chip processing unit 20 through the uplink receiving port 17 of the FPGA processing unit 10, and asynchronously transmits and caches the downlink signal, i.e., the signal sent by the single-chip processing unit 20, to achieve rate matching.

[0055] In addition, the FPGA processing unit independently controls the sending and receiving ports of each analog front-end chip, including a clock signal (SCLK) shared by multiple chips, a shared data sending signal (MOSI), an independent chip select signal (CS) for each chip, and an independent receiving signal (MISO) for each chip.

[0056] The second embodiment of the present invention provides a neural signal acquisition system, such as Fig.10 As shown, the neural signal acquisition system 1000 includes at least one analog front-end chip 30 and the signal processing device 100 described in any of the above embodiments, wherein the analog front-end chip 30 is an RHD2164 chip, and the signal processing device 100 is connected to the analog front-end chip 30.

[0057] According to the neural signal acquisition system 1000 proposed in the embodiment of the present invention, based on the connection between the signal processing device 100 and the analog front-end chip 30, the signal processing device 100 can perform neural signal acquisition and signal analysis processing on the analog front-end chip 30. The signal processing device 100 uses the FPGA processing unit 10 to realize the interface protocol conversion and signal preprocessing of the signal transmitted between the single-chip processing unit 20 and the analog front-end chip 30, and then uses the single-chip processing unit 20 to perform signal analysis processing. Compared with using the FPGA chip alone to realize the neural signal acquisition and data processing functions, it has the characteristics of short development cycle, low overall system power consumption, small circuit area, accurate resource evaluation, good functional reusability, and suitability for rapid iteration. It is more suitable for implantable devices and can achieve lower power consumption neural signal processing and convenient development.

[0058] In the description of the present invention, "plurality" means two or more.

[0059] Other structures and operations of the signal processing device 100 and the neural signal acquisition system 1000 according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0060] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0061] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A signal processing device, characterized in that: include: An FPGA processing unit, wherein the FPGA processing unit is suitable for connecting to an analog front-end chip, wherein the analog front-end chip is a RHD2164 chip; A single-chip microcomputer processing unit, the single-chip microcomputer processing unit is connected to the FPGA processing unit and the host computer; The FPGA processing unit is used to implement the interface protocol conversion of the signal transmitted between the single-chip processing unit and the analog front-end chip, and to implement the signal preprocessing of the signal transmitted between the single-chip processing unit and the analog front-end chip; The single chip processing unit is used to implement signal analysis and processing of signals transmitted between the FPGA processing unit and the host computer.

2. The signal processing device according to claim 1, characterized in that The communication port of the single-chip processing unit adopts an SPI interface, the communication port of the analog front-end chip adopts a DDR interface, and the FPGA processing unit is specifically used to convert the original neural signal sent by the analog front-end chip from a DDR data protocol format to an SPI data protocol format.

3. The signal processing device according to claim 1 or 2, characterized in that: The FPGA processing unit comprises: A mode control module, wherein an input end of the mode control module is connected to the single-chip processing unit and is used to receive a first digital signal sent by the single-chip processing unit, wherein the first digital signal carries mode processing information; A first receiving module, wherein an input end of the first receiving module is suitable for connecting to the analog front-end chip to receive the original neural signal sent by the analog front-end chip and perform interface protocol conversion on the original neural signal; A data processing module, wherein the input end of the data processing module is connected to the mode control module and the first receiving module, and the output end of the data processing module is connected to the single-chip processing unit. The data processing module is used to perform signal preprocessing on the converted original neural signal according to the mode processing information, and send the preprocessed original neural signal to the single-chip processing unit.

4. The signal processing device according to claim 3, characterized in that: The single-chip microcomputer processing unit includes at least one single-chip microcomputer, wherein, when the single-chip microcomputer processing unit includes one single-chip microcomputer, the single-chip microcomputer is used to manage the signal analysis and processing of the transmission signals between all analog front-end chips and the host computer, or, when the single-chip microcomputer processing unit includes multiple single-chip microcomputers, each single-chip microcomputer is used to manage the signal analysis and processing of the transmission signals between the corresponding part of the analog front-end chips and the host computer.

5. The signal processing device according to claim 4, characterized in that: The single chip microcomputer comprises: An uplink communication port, which is connected to the host computer via a serial bus and is used to realize signal transmission between the single-chip processing unit and the host computer; A downlink communication port, the downlink communication port is connected to the FPGA processing module, and the downlink communication port is used to realize signal transmission between the single-chip processing unit and the FPGA processing unit; A signal processing module, wherein the signal processing module is connected to the uplink communication port and the downlink communication port, and the signal processing module is used to implement signal analysis and processing of the signal transmitted between the FPGA processing unit and the host computer.

6. The signal processing device according to claim 5, characterized in that: The FPGA processing unit includes a mode control port, an uplink sending port and an uplink receiving port, and the mode control port is connected to the input end of the mode control module; The single-chip microcomputer processing unit includes a single-chip microcomputer, and the downlink communication port of the single-chip microcomputer includes a downlink control port, a downlink sending port and a downlink receiving port. The downlink control port is connected to the mode control port, and the downlink sending port is connected to the uplink receiving port of the FPGA processing unit so that the FPGA processing unit forwards the downlink signal of the single-chip microcomputer to the analog front-end chip, and the downlink receiving port is connected to the uplink sending port of the FPGA processing unit.

7. The signal processing device according to claim 5, characterized in that: The FPGA processing unit includes a mode control port and an uplink transmission port, and the mode control port is connected to the input end of the mode control module; The single-chip microcomputer processing unit includes a single-chip microcomputer, and the downlink communication port of the single-chip microcomputer includes a downlink control port, a downlink sending port and a downlink receiving port. The downlink control port is connected to the mode control port, the downlink sending port is connected to the receiving port of the analog front-end chip to send a downlink signal to the analog front-end chip, and the downlink receiving port is connected to the uplink sending port of the FPGA processing unit.

8. The signal processing device according to claim 5, characterized in that: The FPGA processing unit includes a mode control port, an uplink transmission port and an uplink reception port, wherein the mode control port is connected to an input end of the mode control module, and the single-chip processing unit includes a plurality of single-chip microcomputers, wherein the plurality of single-chip microcomputers include: A main single-chip microcomputer, wherein the downlink communication port of the main single-chip microcomputer comprises a downlink control port, a downlink sending port and a first downlink receiving port, the downlink control port of the main single-chip microcomputer is connected to the mode control port, the downlink sending port of the main single-chip microcomputer is connected to the uplink receiving port of the FPGA processing unit so that the FPGA processing unit forwards the downlink signal of the single-chip microcomputer to the analog front-end chip, and the first downlink receiving port of the main single-chip microcomputer is connected to the uplink sending port of the FPGA processing unit; At least one slave single-chip microcomputer, the downlink communication port of the slave single-chip microcomputer includes a second downlink receiving port, and the second downlink receiving port of the slave single-chip microcomputer is connected to the uplink sending port of the FPGA processing unit.

9. The signal processing device according to claim 5, characterized in that: The FPGA processing unit includes a mode control port and an uplink transmission port, the mode control port is connected to the input end of the mode control module, the single-chip processing unit includes a plurality of single-chip microcomputers, and the plurality of single-chip microcomputers include: A main single-chip microcomputer, wherein the downlink communication port of the main single-chip microcomputer comprises a downlink control port, a downlink transmission port and a first downlink receiving port, the downlink control port of the main single-chip microcomputer is connected to the mode control port, the downlink transmission port of the main single-chip microcomputer is connected to the receiving port of the analog front-end chip to send a downlink signal to the analog front-end chip, and the first downlink receiving port of the main single-chip microcomputer is connected to the uplink transmission port of the FPGA processing unit; At least one slave single-chip microcomputer, the downlink communication port of the slave single-chip microcomputer includes a second downlink receiving port, and the second downlink receiving port of the slave single-chip microcomputer is connected to the uplink sending port of the FPGA processing unit.

10. The signal processing device according to claim 6 or 8, characterized in that: The FPGA processing unit also includes: An asynchronous FIFO module, wherein the input end of the asynchronous FIFO module is connected to the uplink receiving port of the FPGA processing unit, the asynchronous FIFO module is connected to the analog front-end chip through the downlink sending port of the FPGA processing unit, and the asynchronous FIFO module is used to asynchronously transmit and cache the downlink signal; Among them, the mode control module is also used to receive a second digital signal sent by the single-chip processing unit, and the second digital signal carries at least one or more of data format information and data transmission ID information. The output end of the mode control module is also connected to the downstream sending port of the FPGA processing unit to send the second digital signal through the downstream sending port, wherein the data format information is a 16-bit data format or an 8-bit data format.

11. A neural signal acquisition system, characterized in that: include: At least one analog front-end chip, wherein the analog front-end chip is a RHD2164 chip; The signal processing device according to any one of claims 1 to 10, wherein the signal processing device is connected to the analog front-end chip.

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