Method for reducing leakage current of small memory chip

Abstract

The application provides a method for reducing leakage of a small storage chip, and belongs to the technical field of semiconductor chips. The method comprises the following steps: obtaining current leakage data, original leakage data and functional test data corresponding to a chip to be detected; determining whether a leakage point of the chip to be detected is a polysilicon spacing according to the original leakage data, the current leakage data, a pre-established leakage analysis model and the functional test data; if yes, determining whether a current growth interval of a metal silicide in the chip to be detected exceeds a calibrated growth interval according to a profile measurement result of the chip to be detected; if yes, performing sidewall thickening on a second nitride silicon grown outside a first nitride silicon on a control tube of the chip to be detected, adjusting an etching amount of the second nitride silicon, and performing a tape-out verification on an adjustment result of the chip to be detected to obtain a target adjustment result. The application can achieve the effect of inhibiting the lateral penetration of the metal silicide between the two polysilicon in the storage chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip technology, and more specifically, to a method for reducing leakage current in small memory chips. Background Technology

[0002] With advancements in semiconductor manufacturing processes, chip miniaturization has become the mainstream trend in chip production. Memory chips, as integrated circuit chips for storing data, are also known as memory chips. Memory chips are a crucial component of computer systems, primarily used for temporary or permanent storage of data and instructions. They are used to store and retrieve data in computer systems, enabling fast access and data processing, and supporting the normal operation of the computer system. Smaller memory chips allow for more chips to be cut from each wafer, thus reducing production costs. Smaller memory chips also shorten current paths and reduce resistance, resulting in lower power consumption and heat generation. However, reducing the area of ​​memory chips can lead to leakage current in stored bits, causing the small memory chips to fail. Therefore, it is urgent to solve the problem of leakage current in stored bits caused by the reduction in memory chip area to improve the production yield of small memory chips.

[0003] In related technologies, a layer of metal silicide is typically grown between the two polysilicon strands of a memory chip to control the source, drain, and gate currents. However, when manufacturing small memory chips based on these technologies, the spacing between the two polysilicon strands can be too small, causing the metal silicide grown between them to penetrate and resulting in leakage current in the memory chips. Summary of the Invention

[0004] The purpose of this application is to provide a method for reducing leakage current in small memory chips, which can suppress the side penetration of metal silicide between two polysilicon strands in the memory chip.

[0005] The embodiments of this application are implemented as follows:

[0006] A first aspect of this application provides a method for reducing leakage current in a small memory chip, the method comprising:

[0007] Acquire the current leakage current data, raw leakage current data, and functional test data corresponding to the chip under test;

[0008] Based on the original leakage current data, the current leakage current data, the pre-established leakage current analysis model, and the functional test data, determine whether the leakage current point of the chip under test is a polysilicon pitch.

[0009] If so, then based on the cross-sectional measurement results of the chip under test, determine whether the current growth range of the metal silicide in the chip under test exceeds the calibrated growth range;

[0010] If so, the sidewall of the second silicon nitride layer grown in addition to the original first silicon nitride layer on the control transistor of the chip to be tested is thickened, and the etching amount of the second silicon nitride layer is adjusted to obtain the target adjustment result. The target adjustment result includes: silicon nitride thickness parameters and silicon nitride etching amount parameters.

[0011] As one possible implementation, before obtaining the target adjustment result, the following steps are included:

[0012] Based on the preset sidewall thickening step size and preset silicon nitride morphology, the second silicon nitride layer grown in addition to the original first silicon nitride layer on the control transistor of the chip under test is subjected to multiple sidewall thickening and etching amount adjustments, and the leakage current data, polysilicon spacing and functional test data of the chip under test are obtained after each adjustment.

[0013] Based on the leakage current data, functional test data, and polysilicon spacing of each chip to be verified, the verification results corresponding to each chip to be verified are determined.

[0014] Based on the verification results of each chip to be verified, the target adjustment results are determined.

[0015] As one possible implementation, the sidewalls of the second silicon nitride layer grown outside the native first silicon nitride layer on the control transistor of the chip to be detected are thickened, and the etching amount of the second silicon nitride layer is adjusted, including:

[0016] The thickness of the second silicon nitride layer on the control transistor of the chip under test is adjusted based on the preset sidewall thickening step size.

[0017] The etching amount of the second silicon nitride layer after the sidewall adjustment is adjusted based on the preset silicon nitride morphology.

[0018] As one possible implementation, the target adjustment result is determined based on the verification results corresponding to each chip to be verified, including:

[0019] If the polysilicon spacing of the target chip to be verified reaches the preset value, the leakage current in the leakage current data of the target chip to be verified reaches the preset threshold, and all test items in the functional test data of the target chip to be verified are qualified, then the target chip to be verified is determined to be the target adjustment result.

[0020] As one possible implementation, the process of obtaining functional test data includes:

[0021] Perform conformity testing on the chip under test to obtain functional test data for the chip.

[0022] As one possible implementation, based on the original leakage current data, current leakage current data, a pre-established leakage current analysis model, and functional test data, it is determined whether the leakage point of the chip under test is a polysilicon pitch, including:

[0023] Based on the comparison between the original leakage current data and the current leakage current data, the leakage direction of the chip under test is determined.

[0024] Based on the current leakage current data and the pre-established leakage current analysis model, the source of leakage current in the chip under test is determined.

[0025] Based on the functional test data, determine the leakage point of the chip under test;

[0026] Determine whether the leakage point of the chip under test is a polysilicon pitch.

[0027] As one possible implementation, the leakage direction of the chip under test is determined based on a comparison between the original leakage data and the current leakage data, including:

[0028] The gate-to-drain leakage current data in the original leakage current data is compared with the gate-to-drain leakage current data in the current leakage current data to obtain the first comparison result;

[0029] The channel leakage current data in the original leakage current data is compared with the channel leakage current data in the current leakage current data to obtain a second comparison result;

[0030] The junction leakage current data in the original leakage current data is compared with the junction leakage current data in the current leakage current data to obtain the third comparison result;

[0031] The leakage direction of the chip under test is determined based on the maximum value among the first comparison result, the second comparison result, and the third comparison result.

[0032] As one possible implementation, based on current leakage current data and a pre-built leakage current analysis model, the source of leakage current in the chip under test is determined, including:

[0033] The current leakage data is input into a pre-built leakage analysis model to obtain the leakage source of the chip under test. The pre-built leakage analysis model includes: gate-to-drain leakage analysis item, channel leakage analysis item, and junction leakage analysis item.

[0034] As one possible implementation, based on functional test data, the leakage points of the chip under test are determined, including:

[0035] Based on the pass rate of each test item in the functional test data, the leakage point of the chip under test is determined and marked on the wafer where the chip under test is located.

[0036] As one possible implementation, based on the cross-sectional measurement results of the chip under test, it is determined whether the current growth range of the metal silicide in the chip under test exceeds the calibrated growth range, including:

[0037] Based on the cross-sectional measurement results of the chip under test, the polysilicon spacing and the current growth range of the metal silicide in the chip under test are determined.

[0038] Based on the comparison between the current growth range and the calibrated growth range, it is determined whether the current growth range of the metal silicide in the chip under test exceeds the calibrated growth range.

[0039] The beneficial effects of the embodiments of this application include:

[0040] This application provides a method for reducing leakage current in small memory chips. The method involves acquiring the original leakage current data of the chip under test before area reduction and the current leakage current data after area reduction using a data test structure deployed on the wafer, and pre-constructing a leakage current analysis model. Functional tests are then performed on each chip under test after area reduction to obtain functional test data for each chip. Based on the original and current leakage current data of the chip under test before and after area reduction, the pre-constructed leakage current analysis model, and the functional test data, it is determined whether the leakage point of the chip under test is a polysilicon spacing point. If the leakage point of the chip under test is determined to be a polysilicon spacing point, further data acquisition of the chip under test is required. Based on the physical cross-sectional diagram of the chip under test, and the measurement results of the cross-section, it is determined whether the polysilicon spacing of the chip under test is too close, and whether the current growth range of the metal silicide with a uniform polysilicon spacing exceeds the calibrated growth range. When the polysilicon spacing of the chip under test is too close, causing the current growth range of the metal silicide with a uniform polysilicon spacing to exceed the calibrated growth range, the sidewall of the second silicon nitride layer growing outside the original first silicon nitride layer on the control transistor of the chip under test is thickened, and the etching amount of the second silicon nitride layer is adjusted. The memory chip obtained after each optimization is fabricated and verified to obtain the target adjustment result. The target adjustment result is further tested and verified to obtain the optimal optimization result. In this way, the effect of suppressing the lateral penetration of the metal silicide with a uniform polysilicon spacing between two polysilicon strands in the memory chip can be achieved. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1A flowchart illustrating a first method for reducing leakage current in a small memory chip, as provided in this application embodiment;

[0043] Figure 2 A flowchart illustrating a second method for reducing leakage current in small memory chips provided in this application embodiment;

[0044] Figure 3 A flowchart illustrating a third method for reducing leakage current in small memory chips provided in this application embodiment;

[0045] Figure 4 This application provides a schematic diagram of the structure of a memory chip before process optimization.

[0046] Figure 5 A schematic diagram of the structure of a memory chip with optimized process according to an embodiment of this application;

[0047] Figure 6 This is a schematic diagram of the structure of a memory chip with optimized process technology provided in an embodiment of this application;

[0048] Figure 7 A comparison diagram of leakage current of a memory chip with optimized process provided for an embodiment of this application;

[0049] Figure 8 This is a schematic diagram illustrating the result of a memory chip consistency test provided in an embodiment of this application;

[0050] Figure 9 This is a schematic diagram illustrating the result of another memory chip consistency test provided in an embodiment of this application;

[0051] Figure 10 A flowchart illustrating the fourth method for reducing leakage current in small memory chips provided in this application embodiment;

[0052] Figure 11 A comparison chart of leakage current data of the memory chip before and after the area reduction, provided for embodiments of this application;

[0053] Figure 12 A flowchart illustrating the fifth method for reducing leakage current in small memory chips provided in this application embodiment;

[0054] Figure 13 A schematic diagram of the leakage current analysis model of the memory chip provided in the embodiments of this application;

[0055] Figure 14 A flowchart illustrating the sixth method for reducing leakage current in small memory chips provided in this application embodiment;

[0056] Figure 15 A cross-sectional view of a memory chip provided in an embodiment of this application;

[0057] Figure 16 A cross-sectional view of another memory chip provided in an embodiment of this application;

[0058] Figure 17 A schematic diagram of wafer consistency test results after process optimization provided in an embodiment of this application;

[0059] Figure 18 This application provides a complete process flow diagram for reducing leakage current in small memory chips. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and listed herein can typically be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0062] Currently, miniaturized memory chips allow for the cutting of more chips from a single wafer, thus reducing production costs. Miniaturized chips also shorten the current path of internal integrated circuits and reduce resistance, resulting in lower power consumption and heat generation. A layer of metal silicide is typically grown between the two polysilicon strands of the memory chip to align the source, drain, and gate, enhancing their conductivity. However, this approach often suffers from insufficient spacing between the two polysilicon strands, leading to lateral penetration of the metal silicide grown between them. This can result in excessive conductivity and leakage of stored bits.

[0063] To address this, this application provides a method for reducing leakage current in small memory chips. The method involves acquiring the original and current leakage current data of each chip under test deployed on the wafer using a data test structure laid out on the wafer, and pre-constructing a leakage current analysis model. Functional tests are performed on each chip under test to obtain functional test data. Based on the original leakage current data, current leakage current data, functional test data, and the pre-constructed leakage current analysis model, it is determined whether the leakage point of the chip under test is a polysilicon spacing. If so, the chip under test is physically sectioned, and the cross-sectional measurement results of the chip under test determine whether the long metal silicide between the two polysilicon strands of the memory chip is laterally penetrating. If so, the sidewall of the second silicon nitride layer grown outside the original first silicon nitride layer on the control transistor of the chip under test is thickened, and the etching amount of the second silicon nitride layer is adjusted. The adjustment result of the chip under test is verified to obtain the target adjustment result, and the target adjustment result is further tested to ensure the stable and reliable performance of the target photomask modification result. In this way, the lateral penetration of metal silicide between two polysilicon strands in the memory chip can be suppressed.

[0064] The method for reducing leakage current in small memory chips provided in this application will be explained in detail below with reference to the accompanying drawings.

[0065] Figure 1 A flowchart of a method for reducing leakage current in small memory chips provided in this application is shown below. Figure 1 This application provides a method for reducing leakage current in small memory chips, including:

[0066] S101. Obtain the current leakage current data, raw leakage current data, and functional test data corresponding to the chip under test.

[0067] Optionally, each wafer can be diced into multiple memory chips. When the area of ​​the memory chips is reduced, each wafer can be diced into more memory chips than before. By deploying data test structures on the wafer, leakage current data of each chip under test on the wafer can be collected through the data test structures. The number of data test structures deployed on the wafer is much smaller than the number of memory chips diced from the wafer; that is, one data test structure can collect leakage current data from multiple memory chips. This application does not specifically limit the number of data test structures.

[0068] Optionally, the original leakage current data of the original chip corresponding to the chip under test and the current leakage current data of the chip under test are obtained through a data test structure deployed on the wafer. The original leakage current data is used to indicate the leakage current data generated by the memory chip initially diced on the wafer under various detection voltages. The original leakage current data includes leakage current, leakage resistance, and other leakage data of the original chip. The current leakage current data is used to indicate the leakage current data generated by the original chip after area reduction under various detection voltages. It is worth noting that this application uses multiple detection voltages to detect the leakage current data of the memory chip before and after area reduction, which can be used to investigate the leakage voltage range of the memory chip to ensure the reliability of mass-produced small memory chips.

[0069] Optionally, a leakage analysis model is constructed based on a large amount of original leakage data of memory chips obtained from raw cutting and a large amount of leakage data of memory chips obtained after area reduction. The leakage analysis model includes a variety of leakage analysis items. By inputting the current leakage data and original leakage data of the chip under test into the leakage analysis model, the leakage direction and leakage source of the chip under test can be obtained.

[0070] Optionally, the functional test can be a CP test, whereby each chip under test is subjected to a CP test, and the test points of the chip under test are marked on the wafer based on the functional test data. The functional tests of the chip under test include voltage testing, current testing, timing testing, and memory function testing. If the test result corresponding to the functional test data of the chip under test is qualified, the chip is marked as qualified on the wafer; if the test result corresponding to the functional test data of the chip under test is failed or unqualified, the chip is marked as unqualified on the wafer. It is worth noting that different colors can be used to mark qualified and unqualified memory chips, such as marking unqualified memory chips in red and qualified memory chips in blue, etc. This application does not specifically limit this.

[0071] S102. Based on the original leakage current data, the current leakage current data, the pre-established leakage current analysis model, and the functional test data, determine whether the leakage current point of the chip to be tested is a polysilicon pitch.

[0072] Optionally, a leakage analysis model is constructed based on a large amount of original leakage data of memory chips obtained from raw cutting and a large amount of leakage data of memory chips obtained after area reduction. The leakage analysis model includes a variety of leakage analysis items. By inputting the current leakage data and original leakage data of the chip under test into the leakage analysis model, the leakage direction and leakage source of the chip under test can be obtained.

[0073] Optionally, based on the original leakage current data and current leakage current data of each chip under test before and after area reduction, the pre-built leakage current analysis model, and functional test data, the leakage points of each chip under test and whether the leakage source is the polysilicon spacing are determined. The polysilicon spacing indicates the distance between two polysilicon strands in the memory chip. These two polysilicon strands indicate the two control transistors of the memory chip. When the polysilicon spacing is too close, the long metal silicide between the two polysilicon strands may penetrate laterally, leading to a sudden increase in the conductivity of the memory chip and increasing the risk of leakage of stored bits.

[0074] In addition, based on the functional test data of each chip under test on the wafer, the production yield of the memory chip after the wafer is reduced in area is determined. According to the ratio of the number of qualified chips under test to the number of unqualified chips under test on the wafer, the failure rate of this wafer is determined. When the failure rate of the wafer is large and the calibration points of unqualified chips under test on the wafer are clustered together, the chips under test on the wafer need to be optimized.

[0075] S103. If so, then based on the cross-sectional measurement results of the chip under test, determine whether the current growth range of the metal silicide in the chip under test exceeds the calibrated growth range.

[0076] Optionally, the chip to be tested is physically cut to obtain a cross-sectional schematic diagram of each chip. The growth area of ​​the metal silicide in the cross-sectional schematic diagram is measured, that is, the length, width, and other information of the metal silicide are measured, and the spacing between the two polysilicon strands of each chip to be tested is measured to obtain the cross-sectional measurement results of the chip to be tested. The cross-sectional measurement results of the chip to be tested are used to indicate the spacing measurement results between the two transistors of the chip to be tested and the growth area of ​​the metal silicide in the chip to be tested.

[0077] Optionally, the location of the growing silicon oxide between two transistors in the chip under test can be determined by PFA positioning, and the length of the silicon oxide in the polysilicon spacing can be measured using a measuring tool to obtain the current growth range of the silicon oxide.

[0078] Optionally, the current growth range is used to indicate the actual growth range of the metal silicide between the two transistors of the chip under test at the current moment, that is, the length, width and other information of the metal silicide between the two transistors of the chip under test at the current moment; the calibrated growth range is used to indicate the safe growth range of the metal silicide between the two transistors of the chip under test that will not cause leakage current in the channel of the chip under test, that is, if the actual growth range of the metal silicide between the two transistors of the chip under test at the current moment is within the calibrated growth range, it is determined that the metal silicide has not laterally penetrated.

[0079] Optionally, based on the cross-sectional measurement results of the chip under test and the comparison results of the calibrated growth range, it can be determined whether the actual growth range of the metal silicide between the two transistors of the chip under test at the current moment exceeds the limit of the calibrated growth range.

[0080] S104. If so, the sidewall of the second silicon nitride layer grown in addition to the original first silicon nitride layer on the control transistor of the chip to be detected is thickened, and the etching amount of the second silicon nitride layer is adjusted to obtain the target adjustment result. The target adjustment result includes: silicon nitride thickness parameter and silicon nitride etching amount parameter.

[0081] Optionally, when the polysilicon spacing in the chip under test is too close, causing lateral penetration of the metal silicide between the two transistors and resulting in leakage, the sidewall of the second silicon nitride layer grown outside the original first silicon nitride layer on the control transistor of the chip under test is thickened, and the etching amount of the second silicon nitride layer is adjusted to obtain an adjusted chip under test. The memory chip produced after each adjustment is used as the chip to be verified, and the chip to be verified after each adjustment is fabricated to obtain the target adjustment result. The target adjustment result is used to indicate that the chip under test optimized by processes such as thickening the sidewall of the second silicon nitride layer and adjusting the etching amount has no leakage data, and the functional test data of the adjusted chip under test is qualified.

[0082] Optionally, the first silicon nitride layer is used to indicate a layer of silicon nitride in the memory chip near the control transistor, and the second silicon nitride layer is used to indicate a layer of silicon nitride growing outside the first silicon nitride layer. The first silicon nitride layer and the second silicon nitride layer can be considered to be separated by a spacer.

[0083] Optionally, the etching amount is used to indicate the parameter for adjusting the morphology of the second silicon nitride, the sidewall thickening is used to indicate the increase in the thickness of the second silicon nitride, the silicon nitride thickness parameter in the target adjustment result is used to indicate the optimal increase in thickness of the second silicon nitride, and the silicon nitride etching amount parameter in the target adjustment result is used to indicate the optimal morphology parameter of the second silicon nitride.

[0084] Optionally, the target adjustment results are tested and verified to verify whether the optimized chip under test has leakage current under the action of various detection voltages, and to verify the function of the target adjustment results. Only when the adjusted chip under test has no leakage data and all functional test data are qualified can small memory chips be mass-produced according to the silicon nitride thickness parameters and silicon nitride etching amount parameters in the target adjustment results.

[0085] In this embodiment, the original leakage current data of the chip under test before area reduction and the current leakage current data after area reduction are obtained through a data test structure deployed on the wafer, and a leakage current analysis model is pre-built; functional tests are performed on each chip under test after area reduction to obtain functional test data for each chip under test; based on the original leakage current data and current leakage current data of the chip under test before and after area reduction, the pre-built leakage current analysis model, and the functional test data, it is determined whether the leakage point of the chip under test is a polysilicon spacing; when it is determined that the leakage point of the chip under test is a polysilicon spacing, it is necessary to further obtain a physical cross-sectional view of the chip under test, based on... Based on the cross-sectional measurement results of the chip under test, it is determined whether the polysilicon spacing of the chip under test is too close and whether the current growth range of the metal silicide with a uniform polysilicon spacing exceeds the calibrated growth range. When the polysilicon spacing of the chip under test is too close, causing the current growth range of the metal silicide with a uniform polysilicon spacing to exceed the calibrated growth range, the sidewall of the second silicon nitride layer growing outside the original first silicon nitride layer on the control transistor of the chip under test is thickened, and the etching amount of the second silicon nitride layer is adjusted. The memory chip obtained after each optimization is fabricated and verified to obtain the target adjustment result. The target adjustment result is further tested and verified to obtain the optimal optimization result. In this way, the effect of suppressing the lateral penetration of the metal silicide with a uniform polysilicon spacing between two polysilicon layers in the memory chip can be achieved.

[0086] In one alternative implementation, see [link to implementation details]. Figure 2 Before obtaining the target adjustment result in step S104, the following steps are also included:

[0087] S201. Based on the preset sidewall thickening step size and preset silicon nitride morphology, the second silicon nitride layer grown in addition to the original first silicon nitride layer on the control transistor of the chip under test is thickened and the etching amount is adjusted multiple times, and the leakage current data, polysilicon spacing and functional test data of the chip under test are obtained after each adjustment.

[0088] Optionally, the preset sidewall thickening step size is a preset thickness parameter for thickening the sidewall of the second silicon nitride layer in addition to the original first silicon nitride layer on the control transistor of the memory chip in a single operation. For example, if the preset sidewall thickening step size is 0.01mm, it means that the thickness is increased by 0.01mm on the original thickness of the second silicon nitride layer in a single operation.

[0089] Optionally, the preset silicon nitride morphology is the morphology that the user pre-sets for the second silicon nitride etching process. The preset silicon nitride morphology can be arc-shaped, bow-shaped, etc., and this application does not specifically limit it.

[0090] Optionally, based on a preset sidewall thickening step size, the second silicon nitride layer outside the original first silicon nitride layer on the control transistor of the chip under test is thickened multiple times, and the morphology of the second silicon nitride layer is adjusted multiple times based on a preset silicon nitride morphology. Each sidewall thickening and morphology adjustment results in a corresponding memory chip, which is also the chip to be verified. One chip under test corresponds to at least one chip to be verified. For example, the thickness of the second silicon nitride layer grown outside the original first silicon nitride layer on the control transistor of the chip under test A after area reduction is 0.3 cm, the current growth range of the metal silicide between the two transistors in the chip under test A is 1.2 cm, and the distance between the two transistors in the chip under test A is 1 cm. After the first sidewall thickening and morphology adjustment, the chip under test... The thickness of the second silicon nitride layer growing outside the original first silicon nitride layer on the control transistor is 0.35 cm, and the growth range of the metal silicide between the two transistors is 1.1 cm, resulting in a chip a to be verified with a second silicon nitride layer thickness of 0.35 cm and a metal silicide growth range of 1.1 cm between the two transistors; the thickness of the second silicon nitride layer growing outside the original first silicon nitride layer on the control transistor of the chip to be tested after the second sidewall thickening and morphology adjustment is 0.50 cm, and the growth range of the metal silicide between the two transistors is 1.0 cm, resulting in a chip b to be verified with a second silicon nitride layer thickness of 0.50 cm and a metal silicide growth range of 1.0 cm between the two transistors, etc.

[0091] Optionally, leakage current data of the chip under test after each sidewall thickening and topology adjustment is obtained through a data test structure deployed on the wafer. At the same time, consistency tests are performed on the chip under test after each sidewall thickening and topology adjustment to obtain functional test data of the chip under test after each sidewall thickening and topology adjustment.

[0092] Optionally, the polysilicon pitch is used to indicate the distance between two control transistors in the memory chip, and the polysilicon pitch of the chip under test after each adjustment is obtained through a data test structure deployed on the wafer.

[0093] S202. Based on the leakage current data, functional test data, and polysilicon spacing of each chip to be verified, determine the verification results corresponding to each chip to be verified.

[0094] Optionally, the leakage current data of each chip to be verified is input into a pre-built leakage current analysis model for leakage current analysis. The performance of each chip to be verified is determined based on the functional test data of each chip to be verified. The polysilicon spacing is determined based on the cross-sectional measurement results of each chip to be verified, thereby determining whether the metal silicide between the two transistors has lateral penetration. Based on the leakage current data analysis results and the functional test data analysis results of each chip to be verified, the verification results corresponding to each chip to be verified are obtained.

[0095] S203. Determine the target adjustment result based on the verification results of each chip to be verified.

[0096] Optionally, from the multiple tape-out verification results of the chip under test obtained after multiple sidewall thickenings and etch adjustments, the chip with the best optimization effect is selected as the target adjustment result for that chip under test. The target adjustment result indicates that the optimized chip under test does not have a long metal silicide cross-section between two transistors, which could cause problems such as memory bit leakage and functional impairment in the memory chip.

[0097] In one possible implementation, see [link to relevant documentation]. Figure 3 In step S104, the specific operation of thickening the sidewall of the second silicon nitride layer grown outside the original first silicon nitride layer on the control transistor of the chip to be tested, and adjusting the etching amount of the second silicon nitride layer, can be as follows:

[0098] S301. Adjust the thickness of the second silicon nitride layer on the control transistor of the chip under test based on the preset sidewall thickening step size.

[0099] Optionally, the thickness of the second silicon nitride layer outside the original first silicon nitride layer on the control transistor of the chip under test is adjusted based on a preset sidewall thickening step size. The thickness of the second silicon nitride layer is adjusted iteratively in sequence so that the memory chip will no longer have the problem of metal silicide side penetration even when the spacing between the two polysilicon strands is too small.

[0100] S302. Based on the preset silicon nitride morphology, the etching amount of the second silicon nitride after the sidewall adjustment is adjusted.

[0101] Optionally, the etching amount of the second silicon nitride layer after adjusting its thickness is adjusted based on the preset silicon nitride morphology, so that the second silicon nitride layer maintains a certain aesthetic appearance while preventing metal silicide lateral penetration.

[0102] Figure 4 A schematic diagram of the structure of a memory chip before process optimization is provided in this application. See [link / reference]. Figure 4 In the embodiments of this application, a layer of metal silicide is grown between the two polysilicon gaps of the memory chip.

[0103] Figure 5 For a schematic diagram of the structure of the first process-optimized memory chip provided in this application, see [link / reference]. Figure 5 In this embodiment of the application, the growth range of the metal silicide is narrowed by adjusting the thickness and etching pattern of the second silicon nitride.

[0104] Figure 6For a schematic diagram of the structure of the memory chip with the second optimized process provided in this application, see [link to schematic diagram]. Figure 6 In this embodiment of the application, by adjusting the thickness of the second silicon nitride layer to a certain extent, the growth of metal silicide between the two silicon crystals can be completely suppressed.

[0105] In one optional implementation, step S203 may specifically be as follows:

[0106] If the polysilicon spacing of the target chip to be verified reaches the preset value, the leakage current in the leakage current data of the target chip to be verified reaches the preset threshold, and all test items in the functional test data of the target chip to be verified are qualified, then the target chip to be verified is determined to be the target adjustment result.

[0107] Optionally, the preset threshold is a current threshold set by the user. The preset threshold is used to indicate the leakage current limit of the chip under test. When the leakage current in the leakage data of the chip under test reaches the preset threshold, it is assumed that there is no leakage current in the chip under test. The preset threshold can be 0A, 0.01mA, etc., and this application does not make specific limitations on it.

[0108] Optionally, the preset value is a crystal silicon spacing limit set by the user. When the second silicon nitride sidewall, which grows in addition to the original first silicon nitride on the control transistor of the chip under test, is thickened and adjusted, the spacing between the two transistors in the chip under test reaches the preset value. Then, by default, the metal oxide between the two transistors of the chip under test will not laterally penetrate, thus preventing leakage. The preset value can be 0.5 mm, etc., and this application does not make specific limitations on it.

[0109] Optionally, the target chip to be verified is used to indicate the chip to be verified with the best leakage current control effect among multiple chips to be verified obtained by multiple sidewall thickening and multiple morphology adjustment optimizations on the second silicon nitride grown on the first silicon nitride native to the control tube of the chip to be tested. One chip to be tested corresponds to at least one chip to be verified. Similarly, one chip to be verified has at least one target chip to be verified with the best leakage current control effect.

[0110] Optionally, when the leakage current in the leakage current data of the target chip reaches a preset threshold among the multiple chips to be verified obtained by the chip under test through multiple sidewall thickening and multiple morphology adjustment optimizations, and the polysilicon spacing of the target chip under test meets the preset value, and all test items in the functional test data of the target chip under test are qualified, that is, the target chip under test has no leakage current, and the voltage detection result, current detection result, timing detection result and functional detection result of the target chip under test are all qualified, and there is no long metal silicide side penetration in the polysilicon spacing of the target chip under test, then the target chip under test is taken as the target adjustment result of the chip under test.

[0111] Figure 7 A leakage current comparison diagram of a memory chip with optimized process technology provided in this application is shown in the attached image. Figure 7 The leakage current data of the memory chip before and after photomask optimization provided in this application embodiment is significantly reduced.

[0112] In one optional implementation, the process of acquiring functional test data includes:

[0113] Perform conformity testing on the chip under test to obtain functional test data for the chip.

[0114] Optionally, a consistency test is performed on the chip under test on the wafer to obtain functional test data such as current detection results, voltage detection results, timing detection results, and various functional test data of the chip under test.

[0115] Figure 8 This is a schematic diagram illustrating the results of a memory chip consistency test provided in this application. (See attached diagram) Figure 8 The pass rate of the chips to be tested located at the edge of the wafer is relatively low.

[0116] Figure 9 For another schematic diagram of the consistency test results of the memory chip provided in this application, please refer to... Figure 9 The pass rate of the chips to be tested located in the lower right middle area of ​​the wafer is relatively low.

[0117] In one alternative implementation, see [link to implementation details]. Figure 10 The specific operation of step S102 above can be as follows:

[0118] S1001. Determine the leakage direction of the chip under test based on the comparison between the original leakage data and the current leakage data.

[0119] Optionally, based on the comparison between the leakage current in the original leakage current data and the leakage current in the current leakage current data, the leakage direction of the chip under test can be determined. That is, the leakage current that is significantly larger than the original leakage current is taken as the leakage direction of the chip under test, that is, the leakage of the chip under test has become more serious.

[0120] It is worth noting that the current leakage current data of each detection chip is compared with the original leakage current data of that detection chip, and the comparison of leakage current data is based on the comparison of leakage current data under the same detection voltage.

[0121] S1002. Based on the current leakage current data and the pre-established leakage current analysis model, determine the source of leakage current in the chip under test.

[0122] Optionally, the current leakage current data of the chip under test can be input into a pre-built leakage current analysis model to determine the leakage source of the chip under test. The leakage source of the chip under test can be gate-to-drain leakage, channel leakage caused by metal silicide side-through, or junction leakage; this application does not specifically limit this. It is worth noting that the leakage source is used to indicate the factors or triggers that cause leakage in the scaled-down chip under test.

[0123] S1003. Based on the functional test data, determine the leakage point of the chip to be tested.

[0124] Optionally, the leakage point is used to indicate the physical location of the chip under test on the wafer. Based on the functional test data of each chip under test, the test pass or fail of each chip under test is marked on the wafer. Based on the calibration results of each chip under test on the wafer, the leakage point of the chip under test is determined.

[0125] S1004. Determine whether the leakage point of the chip under test is a polysilicon pitch.

[0126] Optionally, based on the leakage points of each chip under test marked on the wafer, it can be determined whether the leakage points of each chip under test are polysilicon spacing.

[0127] Figure 11 For a comparison chart of leakage current data of the memory chip before and after the area reduction provided in this application, please refer to [link / reference]. Figure 11 By comparing the leakage current data of the memory chip before and after the area was reduced, it can be determined that the current leakage current data of the chip under test is significantly increased compared with the original leakage current data.

[0128] In one alternative implementation, see [link to implementation details]. Figure 12 The specific operation of step S1001 can be as follows:

[0129] S1201. Compare the gate-to-drain leakage current data in the original leakage current data with the gate-to-drain leakage current data in the current leakage current data to obtain the first comparison result.

[0130] Optionally, the gate-to-drain leakage data is used to indicate the leakage data generated by the gate causing the drain to leak in the chip under test. The gate-to-drain leakage data in the current leakage data of the chip under test is compared with the gate-to-drain leakage data in the original leakage data of the original chip corresponding to the chip under test to determine whether the gate-to-drain leakage data in the current leakage data of the chip under test after the area reduction has increased.

[0131] S1202. Compare the channel leakage current data in the original leakage current data with the channel leakage current data in the current leakage current data to obtain a second comparison result.

[0132] Optionally, the channel leakage data is used to indicate the leakage data generated by the metal silicide penetrating the polysilicon in the chip under test. The channel leakage data in the current leakage data of the chip under test is compared with the channel leakage data in the original leakage data of the original chip corresponding to the chip under test to determine whether the channel leakage data in the current leakage data of the chip under test after the area reduction has increased.

[0133] S1203. Compare the junction leakage data in the original leakage data with the junction leakage data in the current leakage data to obtain the third comparison result.

[0134] Optionally, the junction leakage data is used to indicate the leakage data generated by the PN junction leakage in the chip under test. The junction leakage data in the current leakage data of the chip under test is compared with the junction leakage data in the original leakage data of the original chip corresponding to the chip under test to determine whether the junction leakage data in the current leakage data of the chip under test after the area reduction has increased.

[0135] S1204. Determine the leakage direction of the chip under test based on the maximum value among the first comparison result, the second comparison result, and the third comparison result.

[0136] In one optional implementation, step S1002 may specifically be performed as follows:

[0137] The current leakage data is input into a pre-built leakage analysis model to obtain the leakage source of the chip under test. The pre-built leakage analysis model includes: gate-to-drain leakage analysis item, channel leakage analysis item, and junction leakage analysis item.

[0138] Optionally, by inputting the current leakage current data of the chip under test into a pre-built leakage current analysis model, the specific cause of the leakage current data in the chip under test can be determined. The pre-built leakage current analysis model includes: a gate-to-drain leakage current analysis item, a channel leakage current analysis item, and a junction leakage current analysis item. The gate-to-drain leakage current analysis item is used to analyze the gate-to-drain leakage current data of the chip under test; the channel leakage current analysis item is used to analyze the channel leakage current data of the chip under test; the junction leakage current analysis item is used to analyze the junction leakage current data of the chip under test; the gate-to-drain leakage current analysis item also incorporates the characteristics of gate-induced drain leakage in memory chips; the channel leakage current analysis item also incorporates the characteristics of metal silicide side-penetration-induced leakage in memory chips; and the junction leakage current analysis item also incorporates the characteristics of PN junction-induced leakage in memory chips.

[0139] In one optional implementation, step S1003 may specifically be as follows:

[0140] Based on the pass rate of each test item in the functional test data, the leakage point of the chip under test is determined and marked on the wafer where the chip under test is located.

[0141] Optionally, each chip under test is marked on the wafer based on the test results of each test item in the functional test data of the chip under test. Only when all test items in the functional test data of the chip under test are qualified can the chip under test be marked as a qualified memory chip on the wafer.

[0142] Optionally, the chip under test can be calibrated on the wafer containing the chip under test based on the functional test data or CP test results.

[0143] Figure 13 For a schematic diagram of the leakage current analysis model of the memory chip provided in this application, please refer to [reference needed]. Figure 13 Based on the leakage current between transistors SG and CG, it was determined that the polysilicon spacing of the chip under test was too close, and the metal silicide in the polysilicon spacing was laterally penetrated, causing the chip under test to generate leakage data.

[0144] In one alternative implementation, see [link to implementation details]. Figure 14 The specific operation of step S103 can be as follows:

[0145] S1401. Based on the cross-sectional measurement results of the chip under test, determine the polysilicon spacing and the current growth range of the metal silicide in the chip under test.

[0146] Optionally, a cross-sectional view of the chip to be tested can be measured using a measuring tool to obtain the spacing between two transistors in the chip and the current growth range of the metal silicide between the two transistors in the chip.

[0147] S1402. Based on the comparison between the current growth range and the calibrated growth range, determine whether the current growth range of the metal silicide in the chip to be tested exceeds the calibrated growth range.

[0148] Optionally, based on the size comparison and positional region comparison between the current growth range and the calibrated growth range, it can be determined whether the current growth range of the metal silicide between the two transistors in the chip under test exceeds the calibrated growth range, that is, whether the metal silicide between the two transistors has lateral penetration.

[0149] Figure 15 A cross-sectional view of a memory chip provided in this application is shown below. Figure 15 In the memory chip provided in this application embodiment, the current growth range of the metal silicide in the two polysilicon spacings of the memory chip does not exceed the calibrated growth range. That is, although the polysilicon spacing of the memory chip after the area reduction is too close, the metal silicide does not penetrate to the side.

[0150] Figure 16See also the cross-sectional view of another memory chip provided in this application. Figure 16 In the embodiment of this application, the current growth range of the metal silicide in the two polysilicon spacings of the memory chip exceeds the calibrated growth range. That is, the polysilicon spacing of the memory chip after the area reduction is too close, and the metal silicide in the polysilicon spacing penetrates to the side.

[0151] Figure 17 A schematic diagram of wafer conformity test results after process optimization provided in this application is shown below. Figure 17 In this embodiment of the application, by optimizing the second silicon nitride layer on the control transistor of the chip under test on the wafer, in addition to the original first silicon nitride layer, the defect rate of the chip under test on the wafer is significantly reduced.

[0152] Figure 18 This application provides a complete process flow diagram for reducing leakage current in small memory chips. The specific manufacturing process for reducing leakage current in small memory chips provided in this application is as follows: A leakage current analysis model is constructed based on a large amount of leakage current data before and after the area of ​​memory chips is reduced; CP testing is performed on the reduced-area memory chips to obtain the consistency test results; the wafer yield is determined based on the functional test data of each reduced-area memory chip on the wafer; the reduced-area memory chips are physically sliced ​​to obtain a cross-sectional structure diagram; the cross-sectional diagram of the memory chips is measured using measuring tools to obtain the polysilicon spacing and the current growth range of the metal silicide in the polysilicon spacing; based on the leakage current data of the memory chips before and after area reduction, the pre-constructed leakage current analysis model, the cross-sectional measurement results, and the functional test data, it is determined whether the reduced-area memory chips meet the conditions for sidewall thickening optimization; and after meeting the conditions, the chip to be tested is optimized using the SACER process, and the optimized wafer is tested and verified to obtain the target adjustment result.

[0153] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0154] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for reducing leakage current in small memory chips, characterized in that, The method includes: Acquire the current leakage current data, original leakage current data, and functional test data corresponding to the chip under test. The original leakage current data refers to the leakage current data of the chip under test before the area was reduced. Based on the original leakage current data, the current leakage current data, the pre-established leakage current analysis model, and the functional test data, determine whether the leakage current point of the chip under test is a polysilicon pitch. If so, then based on the cross-sectional measurement results of the chip under test, determine whether the current growth range of the metal silicide in the chip under test exceeds the calibrated growth range; If so, the sidewall of the second silicon nitride layer grown outside the original first silicon nitride layer on the control transistor of the chip under test is thickened, and the etching amount of the second silicon nitride layer is adjusted to obtain the target adjustment result. The target adjustment result includes: silicon nitride thickness parameters and silicon nitride etching amount parameters.

2. The method for reducing leakage current in small memory chips according to claim 1, characterized in that, Before obtaining the target adjustment result, the following are included: Based on the preset sidewall thickening step size and preset silicon nitride morphology, the second silicon nitride layer grown in addition to the original first silicon nitride layer on the control transistor of the chip under test is subjected to multiple sidewall thickening and etching amount adjustments, and the leakage current data, polysilicon spacing and functional test data of the chip under test are obtained after each adjustment. Based on the leakage current data, functional test data, and polysilicon spacing of each chip to be verified, the verification result corresponding to each chip to be verified is determined. Based on the verification results corresponding to each of the chips to be verified, the target adjustment result is determined.

3. The method for reducing leakage current in small memory chips according to claim 1, characterized in that, The process of thickening the sidewalls of the second silicon nitride layer grown outside the original first silicon nitride layer on the control transistor of the chip under test, and adjusting the etching amount of the second silicon nitride layer, includes: The thickness of the second silicon nitride layer on the control transistor of the chip under test is adjusted based on the preset sidewall thickening step size. The etching amount of the second silicon nitride layer after the sidewall adjustment is adjusted based on the preset silicon nitride morphology.

4. The method for reducing leakage current in small memory chips according to claim 2, characterized in that, The step of determining the target adjustment result based on the verification results corresponding to each of the chips to be verified includes: If the polysilicon spacing of the target chip to be verified reaches a preset value, the leakage current in the leakage data of the target chip to be verified reaches a preset threshold, and all test items in the functional test data of the target chip to be verified are qualified, then the target chip to be verified is determined to be the target adjustment result.

5. The method for reducing leakage current in small memory chips according to claim 1, characterized in that, The process of obtaining the functional test data includes: A consistency test is performed on the chip under test to obtain the functional test data of the chip under test.

6. The method for reducing leakage current in small memory chips according to claim 1, characterized in that, The step of determining whether the leakage point of the chip under test is a polysilicon pitch based on the original leakage data, the current leakage data, the pre-established leakage analysis model, and the functional test data includes: Based on the comparison between the original leakage current data and the current leakage current data, the leakage direction of the chip under test is determined. Based on the current leakage current data and the pre-established leakage current analysis model, the source of leakage current in the chip under test is determined. Based on the functional test data, determine the leakage point of the chip under test; Determine whether the leakage point of the chip under test is a polysilicon pitch.

7. The method for reducing leakage current in small memory chips according to claim 6, characterized in that, Determining the leakage direction of the chip under test based on the comparison result between the original leakage data and the current leakage data includes: The gate-to-drain leakage current data in the original leakage current data is compared with the gate-to-drain leakage current data in the current leakage current data to obtain a first comparison result; The channel leakage current data in the original leakage current data is compared with the channel leakage current data in the current leakage current data to obtain a second comparison result; The junction leakage current data in the original leakage current data is compared with the junction leakage current data in the current leakage current data to obtain a third comparison result; The leakage direction of the chip under test is determined based on the maximum value among the first comparison result, the second comparison result, and the third comparison result.

8. The method for reducing leakage current in small memory chips according to claim 6, characterized in that, The step of determining the leakage source of the chip under test based on the current leakage data and the pre-built leakage analysis model includes: The current leakage data is input into a pre-built leakage analysis model to obtain the leakage source of the chip under test. The pre-built leakage analysis model includes: gate-induced drain leakage analysis item, channel leakage analysis item, and junction leakage analysis item.

9. The method for reducing leakage current in small memory chips according to claim 6, characterized in that, The step of determining the leakage point of the chip under test based on the functional test data includes: Based on the pass rate of each test item in the functional test data, the leakage point of the chip under test is determined, and the leakage point is marked on the wafer where the chip under test is located.

10. The method for reducing leakage current in small memory chips according to claim 1, characterized in that, The step of determining whether the current growth range of the metal silicide in the chip under test exceeds the calibrated growth range based on the cross-sectional measurement results of the chip under test includes: Based on the cross-sectional measurement results of the chip under test, the polysilicon spacing and the current growth range of the metal silicide in the chip under test are determined. Based on the comparison between the current growth range and the calibrated growth range, it is determined whether the current growth range of the metal silicide in the chip under test exceeds the calibrated growth range.

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