Chip sealing ring protection method and chip processing equipment
By forming multiple exposure areas on the wafer substrate during the chip cutting process, forming multiple chip body and passivation layer, and forming a thickened layer on the outside of the passivation layer, the problem of cracks, layering or peeling of the chip during the cutting process is solved, and the chip resistance to corrosion and cutability are improved.
Patent Information
- Application Number
- CN202411961945.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-04
AI Technical Summary
During the chip cutting process, the mechanical compressive stress generated by the blade can easily lead to cracks, delamination or peeling of the chip, especially in the metal connecting layer and passivation layer. At the same time, thinning or removal of the passivation layer in the pretreatment method will cause damage to the seal ring structure, which will in turn lead to more serious delamination or lobes.
By forming a plurality of first exposure regions and a second exposure regions on the wafer substrate, a plurality of chip bodies and a passivation layer are formed. The second exposure region includes a body region and a thickening region, the passivation thickening layer is formed outside the passivation body layer, and a cutting gap is formed between adjacent passivation thickening layers to expose the cutting path.
This method can increase the chip's corrosion resistance, maintain the integrity of the passivation layer, avoid the chip's erosion in the latter process, thereby ensuring the stability of the chip's internal structure, improving cutability, and is suitable for a variety of packaging methods.
Smart Images
Figure CN119764192A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of wafer preparation technology, and in particular to a chip sealing ring protection method and chip processing equipment. Background Art
[0002] At present, as the size of chips and their cutting paths are getting smaller and smaller, the mechanical compressive stress generated by the blade during the cutting process can easily cause cracks, delamination or peeling of the chip, which is particularly obvious in the metal wiring layer and passivation layer. Of course, there are also pre-treatment methods to thin or even completely remove the passivation layer in the cutting path before mechanical cutting of the chip.
[0003] However, during the pretreatment process, the passivation layer will also be affected by the erosion of subsequent processes and become incomplete, exposing the side wall and metal of the sealing ring. The exposed metal layer is easily corroded by the packaging and patch processing environment, especially the process section involving wet cleaning, which will eventually damage the sealing ring structure and cause more serious delamination and cracking, causing fatal damage to the chip. Summary of the invention
[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a chip sealing ring protection method and chip processing equipment.
[0005] A first aspect of the present application provides a chip sealing ring protection method, comprising the following steps:
[0006] S1. Preset multiple points;
[0007] S2, sequentially moving the first photomask corresponding to the plurality of points, and forming a plurality of first exposure areas on the wafer substrate, molding a plurality of chip bodies corresponding to the plurality of first exposure areas, and forming cutting paths between the chip bodies corresponding to the adjacent points;
[0008] S3, sequentially moving the second photomask corresponding to the plurality of points, and forming a plurality of second exposure areas on the wafer substrate, wherein the second exposure area includes a body area and a thickened area arranged on the outer circle of the body area;
[0009] S4, forming a passivation body layer on the outside of the chip body according to the body area, and forming a passivation thickening layer on the outside of the passivation body layer according to the thickening area, and forming a cutting gap between the passivation thickening layers corresponding to adjacent points to expose part of the cutting path.
[0010] Optionally, the following steps are further included between step S2 and step S3:
[0011] A sealing ring is arranged on the outer side of the side wall of the chip body, and the passivation body layer is wrapped around the outer side of the sealing ring.
[0012] Optionally, the step S4 specifically includes:
[0013] The passivation body layer and the passivation thickening layer are both formed as transparent layers.
[0014] Optionally, the step S4 specifically includes:
[0015] At adjacent points, the second exposure areas formed by the second photomask on the wafer substrate are separated from each other to form the cutting gap between the passivation thickening layers at the periphery of adjacent chip bodies.
[0016] Optionally, the thickness of the passivation thickening layer is greater than or equal to 1 um and less than or equal to 3 um.
[0017] Optionally, the step S4 specifically includes:
[0018] Applying photoresist on the wafer substrate and filling the cutting path with the photoresist;
[0019] By exposing, the photoresist in the second exposure area forms the passivation body layer and the passivation thickening layer at the same time, and the passivation body layer and the passivation thickening layer together constitute a passivation layer;
[0020] The photoresist outside the second exposure area is etched.
[0021] Optionally, after step S4, the following steps may be further performed:
[0022] S5. Thinning the passivation layer outside the side wall of the chip body.
[0023] Optionally, the thickness of the passivation layer on the outer side wall of the chip body is greater than or equal to 0 um and less than or equal to 2 um.
[0024] A second aspect of the present application provides a chip processing device, which performs chip processing according to any of the chip sealing ring protection methods described above, wherein the chip processing device includes a first photomask and a second photomask;
[0025] The first photomask can form a plurality of first exposure areas on the wafer substrate for forming a chip body;
[0026] The second photomask can form a plurality of second exposure areas on the wafer substrate, wherein the second exposure area includes a body area and a thickened area arranged at an outer circle of the body area;
[0027] The contour of the first exposure area is within the range of the contour of the main area, and the contour of the main area is within the range of the contour of the thickened area.
[0028] Optionally, the width of the thickened area is greater than or equal to 1 um and less than or equal to 3 um.
[0029] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages:
[0030] The chip sealing ring protection method provided in the present application can form multiple chip bodies on a wafer substrate by moving the first mask corresponding to multiple points. The multiple chip bodies are arranged corresponding to multiple first exposure areas, and cutting paths can be formed between the chip bodies to facilitate mechanical cutting of the chip in the later stage. By moving the second mask corresponding to multiple points, a passivation body layer can be formed on the periphery of the chip body, and a passivation thickening layer can also be formed on the periphery of the passivation body layer. At the same time, there is a cutting gap between the passivation thickening layers on adjacent chip bodies, and the cutting path can be exposed through the cutting gap. That is to say, the passivation body layer and the passivation thickening layer have a certain thickness. By setting the passivation thickening layer, the ability of the chip to resist corrosion can be increased. In this way, the passivation body layer can be completely retained to avoid the chip body being exposed due to corrosion in the later stage process, thereby ensuring the stability of the internal structure of the chip, and the cutting operation can be directly performed from the cutting gap between the passivation thickening layers of adjacent chip bodies, which can avoid direct cutting of the passivation layer, thereby solving the problems of cracks, delamination or peeling, improving the cuttability, being suitable for a variety of packaging methods, and ensuring the service life of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0033] Figure 1 A schematic diagram of the structure of a chip without cutting path pretreatment;
[0034] Figure 2 Schematic diagram of structural splitting of a chip without dicing street pretreatment;
[0035] Figure 3 It is a schematic diagram of the structure of the chip after adding the cutting road pretreatment;
[0036] Figure 4 A schematic diagram of structural erosion of a chip after adding dicing street pretreatment;
[0037] Figure 5 Schematic diagram of the chip processing after adding cutting path pretreatment Figure 1 ;
[0038] Figure 6 Schematic diagram of the chip processing after adding cutting path pretreatment Figure 2 ;
[0039] Figure 7 FIG. 1 is a schematic diagram of a chip processing process according to an embodiment of the present invention. Figure 1 ;
[0040] Figure 8 FIG. 1 is a schematic diagram of a chip processing process according to an embodiment of the present invention. Figure 2 ;
[0041] Fig. 9 FIG. 1 is a schematic diagram of a chip processing process according to an embodiment of the present invention. Figure 3 .
[0042] In the figure: 01, first exposure area; 02, second exposure area; 021, body area; 022, thickening area;
[0043] 10. Wafer substrate; 20. Dielectric layer; 30. Metal connection hole; 40. Metal layer; 50. Passivation body layer; 60. Passivation thickening layer; 70. Second photomask; 80. Photoresist. DETAILED DESCRIPTION
[0044] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
[0045] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.
[0046] At present, as the size of chips and their cutting paths are getting smaller and smaller, the mechanical compressive stress generated by the blade during the cutting process can easily cause cracks, delamination or peeling of the chip, which is particularly obvious in the metal wiring layer and passivation layer. Of course, there are also pre-treatment methods that thin the passivation layer in the cutting path or even completely remove it before mechanical cutting of the chip.
[0047] Reference Figure 1 As shown, without adding the cutting road pretreatment, the passivation layer mask, that is, the second mask, completely covers the chip boundary and the cutting road position, that is, the passivation layer is retained after etching. Figure 2As shown, during the cutting process, the cutting stress may cause damage and cracks to the dielectric layer between the main layers of the chip, and the cutting stress will also be transmitted to other layer structures connected to the interlayer dielectric layer, causing other layer structures to split, affecting the chip reduction yield and reliability.
[0048] However, this method does not take into account the protection of the chip sealing ring, resulting in the exposure of the sealing ring side wall and metal. The exposed metal layer is easily corroded by the packaging and chip processing environment, especially the process section involving wet cleaning, which ultimately causes damage to the sealing ring structure and leads to more serious delamination and cracking, causing fatal damage to the chip.
[0049] Reference Figure 3 As shown in FIG. 1 , the passivation layer mask only covers the chip boundary, and the passivation layer and dielectric layer on the cutting path will be etched away. In this way, the edge damage or delamination of the interlayer dielectric layer caused by the cutting stress can be improved. However, referring to FIG. Figure 4 As shown in the figure, the sidewall metal of the chip body and the sealing ring is directly exposed to the air. This feature will cause the metal to be corroded by the wet environment during subsequent processing. Especially during WLCSP packaging, the sidewall may be continuously exposed and corroded for a long time, which can easily damage the sealing ring structure, become a stress concentration point, and even cause delamination.
[0050] Based on the above process risks, the present application provides a chip sealing ring protection method and chip processing equipment, which can optimize the above chip structure.
[0051] The chip sealing ring protection method and chip processing equipment are described in detail below through specific embodiments:
[0052] Reference Figures 7 to 9 As shown, some embodiments of the present invention provide a chip sealing ring protection method, comprising the following steps:
[0053] S1. Preset multiple points.
[0054] S2. Move the first photomask in sequence corresponding to multiple points, and form multiple first exposure areas 01 on the wafer substrate 10. According to the multiple first exposure areas 01, multiple chip bodies are formed correspondingly, and cutting lanes are formed between the chip bodies corresponding to adjacent points. In other words, by moving the first photomask in correspondence with multiple points, multiple chip bodies can be formed on the wafer substrate 10, and multiple chip bodies are set corresponding to multiple first exposure areas 01. Cutting lanes can be formed between the chip bodies, which is convenient for mechanical cutting of the chips later. In specific implementation, the contour of the first exposure area 01 is adapted to the outer contour of the chip body, which can make full use of the space on the wafer substrate 10 and ensure the number and size of the chips finally formed.
[0055] S3, sequentially moving the second mask 70 corresponding to the plurality of points, and forming a plurality of second exposure areas 02 on the wafer substrate 10, wherein the second exposure area 02 includes a body area 021 and a thickened area 022 arranged on the outer ring of the body area.
[0056] S4, forming a passivation body layer 50 on the outside of the chip body according to the body area 021, and forming a passivation thickening layer 60 on the outside of the passivation body layer 50 according to the thickening area 022, and forming a cutting gap between the passivation thickening layers 60 at adjacent points to expose part of the cutting path. Specifically, there is a cutting gap between the passivation thickening layers 60 on adjacent chip bodies, and the cutting path can be exposed through the cutting gap, without additional pretreatment, and the cutting path can be exposed through the cutting gap, so that physical cutting can be performed through the cutting gap.
[0057] In specific implementation, by moving the second mask 70 to corresponding multiple points, a passivation body layer 50 can be formed on the periphery of the chip body, and a passivation thickening layer 60 can also be formed on the periphery of the passivation body layer 50. The passivation thickening layer 60 can protect the passivation body layer 50 to improve the protection performance of each chip body.
[0058] It can be understood that the passivation body layer 50 and the passivation thickening layer 60 have a certain thickness. By setting the passivation thickening layer 60, the ability of the chip to resist corrosion can be increased. In this way, the passivation body layer 50 can be completely retained to avoid the chip body being exposed to corrosion in the later process, thereby ensuring the stability of the internal structure of the chip. It can also be directly cut from the cutting gap between the passivation thickening layers 60 of adjacent chip bodies, which can avoid direct cutting of the passivation layer, thereby solving the problems of cracks, delamination or peeling, improving cuttability, being suitable for a variety of packaging methods, and ensuring the service life of the chip.
[0059] It should be noted that the photomask is made of quartz glass as a substrate, on which a layer of metal chromium and photosensitive resin are plated to become a photosensitive material. The designed circuit pattern is exposed on the photosensitive resin or photoresist through an electronic laser device, and the exposed area will be developed, and then a circuit pattern can be formed on the metal chromium, that is, the first photomask can correspond to form a first exposure area 01 on the wafer substrate 10, and the second photomask 70 can correspond to form a second exposure area 02 on the wafer substrate 10. The projected circuit can be photo-etched by an integrated circuit lithography machine, that is, the photomask can use exposure and development to depict a geometric structure on the photoresist, and then the pattern on the photomask is transferred to the substrate through an etching process.
[0060] In some embodiments, between step S2 and step S3, the following step is further included: a sealing ring is provided on the outer side of the side wall of the chip body, and the internal structure of the chip body can be sealed and protected by the sealing ring. Specifically, the sealing ring can prevent unwanted stress expansion and cracking from the cutting path to the chip caused by the above-mentioned cutting process, and the sealing ring also has the ability to resist gas and liquid erosion, and can prevent the penetration and damage of water vapor or other chemical pollution sources.
[0061] The passivation body layer 50 is wrapped around the outside of the sealing ring to protect the chip body and the sealing ring at the same time, thereby preventing the chip body and the sealing ring from being exposed or damaged by erosion in the later stage process and stabilizing the internal structure of the chip.
[0062] Specifically, the chip body includes multiple dielectric layers 20, in which metal layers 40 and metal connection holes 30 are embedded. The metal layers 40 in adjacent dielectric layers 20 are electrically connected through the metal connection holes 30, and the sealing ring can be sealed on the outside of multiple dielectric layers 20 at the same time to achieve an interlayer sealing effect of adjacent dielectric layers 20.
[0063] When implementing it, refer to Figures 5 to 8 As shown, the second mask 70 can directly utilize the existing mask structure for improvement so as to expand the size of the second exposure area 02. Thus, under the action of the second mask 70, a passivation thickened layer 60 with a certain thickness can be formed. During the etching process, the passivation body layer 50 can be completely retained, thereby providing protection for the side wall of the sealing ring through the passivation body layer 50 to prevent the metal of the sealing ring from being corroded by the wet environment during the post-processing of packaging and chip mounting. In particular, during WLCSP packaging, the side wall of the chip may be continuously exposed and corroded for a long time. The chip sealing ring protection method of the present application can ensure the structural integrity of the sealing ring and provide continuous protection for the chip.
[0064] In some embodiments, step S4 specifically includes: forming both the passivation body layer 50 and the passivation thickening layer 60 into transparent layers. In this way, even if the passivation body layer 50 and the passivation thickening layer 60 are arranged on the cutting path, the visibility of the cutting path can be ensured without affecting the cutting operation.
[0065] Furthermore, the thickness of the passivation body layer 50 and the passivation thickening layer 60 is relatively thin, and will not occupy too much cutting path space. There is no need to reserve additional space for the passivation thickening layer 60, and the number of chips on the wafer substrate 10 will not be reduced. In other words, while ensuring the number and size of the final formed chips, the chip performance can be improved and the internal structure of the chip can be kept stable.
[0066] In some embodiments, step S4 specifically includes: at adjacent points, the second exposure areas 02 formed by the second photomask 70 on the wafer substrate 10 are separated from each other to form a cutting gap between the passivation thickening layers 60 at the periphery of the adjacent chip bodies. In other words, the passivation thickening layers 60 at the periphery of the adjacent chip bodies are also separated from each other, and a cutting gap is formed between two adjacent passivation thickening layers 60, and a portion of the cutting path can also be exposed through the cutting gap, so that the wafer substrate 10 can be physically cut through the cutting gap.
[0067] Specifically, the thickness of the passivation thickening layer 60 is d1, and d1 is greater than or equal to 1um and less than or equal to 3um. It is understandable that the thickness of the passivation thickening layer 60 should be greater than or equal to 1um to ensure that in the back-end process, the passivation thickening layer 60 has sufficient thickness to resist various corrosions to avoid the passivation body layer 50 from being damaged and affecting the internal structure of the chip; of course, the thickness of the passivation thickening layer 60 cannot be too large, that is, the thickness of the passivation thickening layer 60 should be less than or equal to 3um, so that the number and size of the chips on the wafer substrate 10 can be guaranteed, and the production and processing efficiency can be guaranteed, while avoiding the retained passivation layer from being too thick and affecting the subsequent cutting operation. In specific implementation, by expanding the size of the second exposure area 02 on the second mask 70 in the original process, the passivation body layer 50 and the passivation thickening layer 60 can be directly obtained during the processing without the need to add additional masks or processes.
[0068] In some embodiments, step S4 specifically includes: applying photoresist on the wafer substrate 10 and filling the cutting path with the photoresist; through exposure, the photoresist within the second exposure area 02 simultaneously forms a passivation body layer 50 and a passivation thickening layer 60, and the passivation body layer 50 and the passivation thickening layer 60 together constitute a passivation layer; and etching the photoresist outside the second exposure area 02.
[0069] That is to say, when processing, refer to Figure 7 As shown, first, the wafer substrate 10 is filled with photoresist, and the photoresist fills the gaps between the chip bodies or fills the cutting paths. Under the action of the second photomask 70, the photoresist within the contour of the second exposure area 02 can be retained, and the rest of the photoresist is removed. Figure 8 As shown, the passivation body layer 50 and the passivation thickening layer 60 corresponding to the size of the second mask 70 can be finally obtained, and the contour of the second exposure area 02 corresponds to the outermost contour of the passivation thickening layer 60 .
[0070] Specifically, refer to Figure 8As shown, during the completion of the back-end process, the passivation thickening layer 60 is provided to increase the chip's ability to resist corrosion, thereby allowing the passivation body layer 50 to be completely retained. Under the action of the complete passivation body layer 50, the chip has a good protection effect and is suitable for various packaging methods, and can avoid the corrosion of the sealing ring or the chip body by the wet environment.
[0071] That is to say, the final chip structure includes a chip body, a sealing ring arranged on the outside of the side wall of the chip body, and a passivation layer wrapped around the outside of the sealing ring and preserved intact. The internal structure of the chip is stable and can ensure product performance.
[0072] Furthermore, after step S4, the following step is further included: S5, thinning the passivation layer on the outer side of the side wall of the chip body. In this way, the size of the cutting gap can be further expanded under the premise that the passivation layer is intact and has good protection performance, so as to avoid directly cutting the passivation layer, avoid cracks, delamination or peeling problems, and improve the cuttability of the wafer substrate 10.
[0073] Reference Fig. 9 As shown, the thickness of the passivation layer on the outer side wall of the chip body is d2, and d2 is greater than or equal to 0um and less than or equal to 2um. It can be understood that for different packaging methods, different passivation layer thicknesses can be set accordingly to improve cuttability while having sufficient protection performance.
[0074] That is to say, when the passivation layer is greater than 0um, it is suitable for WLCSP packaging, and when the passivation layer is equal to 0um, it is suitable for full package packaging. Of course, the thickness of the passivation layer on the outer side of the chip body should also be less than or equal to 2um to ensure that the cutting gap between the passivation layers on adjacent chip bodies has a sufficient size to facilitate subsequent cutting processing.
[0075] Some other embodiments of the present application provide a chip processing device, which processes a chip according to a chip sealing ring protection method as described in any of the above embodiments. The chip processing device includes a first photomask and a second photomask 70 .
[0076] Among them, the first mask can form multiple first exposure areas 01 on the wafer substrate 10, which are used to form the chip body on the wafer substrate 10; the second mask 70 can form multiple second exposure areas 02 on the wafer substrate 10, and the second exposure area 02 includes a main body area 021 and a thickened area 022 arranged on the outer circle of the main body area 021.
[0077] The contour of the first exposure area 01 is within the range of the contour of the main area 021, and the contour of the main area 021 is within the range of the contour of the thickened area 022. Through the second mask 70, a passivation main layer 50 and a passivation thickening layer 60 can be directly formed on the outside of the chip body during the processing process, so that the passivation main layer 50 can be protected by the passivation thickening layer 60 during the chip processing process, so that the passivation main layer 50 can be completely retained, thereby being able to physically protect the chip body.
[0078] In some embodiments, the width of the thickened area 022 is greater than or equal to 1um and less than or equal to 3um. In this way, the thickness of the finally formed passivation thickened layer 60 is greater than or equal to 1um and less than or equal to 3um. The passivation thickened layer 60 has sufficient thickness to resist various corrosions and can avoid occupying too much space on the wafer substrate 10. It can protect the passivation body layer 50 while ensuring the number and size of the chips on the wafer substrate 10.
[0079] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0080] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A chip sealing ring protection method, characterized in that: The following steps are involved: S1. Preset multiple points; S2, sequentially moving the first photomask corresponding to the plurality of points, and forming a plurality of first exposure areas on the wafer substrate, molding a plurality of chip bodies corresponding to the plurality of first exposure areas, and forming cutting paths between the chip bodies corresponding to the adjacent points; S3, sequentially moving the second photomask corresponding to the plurality of points, and forming a plurality of second exposure areas on the wafer substrate, wherein the second exposure area includes a body area and a thickened area arranged on the outer circle of the body area; S4, forming a passivation body layer on the outside of the chip body according to the body area, and forming a passivation thickening layer on the outside of the passivation body layer according to the thickening area, and forming a cutting gap between the passivation thickening layers corresponding to adjacent points to expose part of the cutting path.
2. The chip sealing ring protection method according to claim 1, characterized in that: The step S2 and the step S3 also include: A sealing ring is arranged on the outer side of the side wall of the chip body, and the passivation body layer is wrapped around the outer side of the sealing ring.
3. The chip sealing ring protection method according to claim 1, characterized in that: The step S4 specifically includes: The passivation body layer and the passivation thickening layer are both formed as transparent layers.
4. The chip sealing ring protection method according to claim 1, characterized in that: The step S4 specifically includes: At adjacent points, the second exposure areas formed by the second photomask on the wafer substrate are separated from each other to form the cutting gap between the passivation thickening layers at the periphery of adjacent chip bodies.
5. The chip sealing ring protection method according to claim 1, characterized in that: The thickness of the passivation thickening layer is greater than or equal to 1 um and less than or equal to 3 um.
6. The chip sealing ring protection method according to any one of claims 1 to 5, characterized in that: The step S4 specifically includes: Applying photoresist on the wafer substrate and filling the cutting path with the photoresist; By exposing, the photoresist in the second exposure area forms the passivation body layer and the passivation thickening layer at the same time, and the passivation body layer and the passivation thickening layer together constitute a passivation layer; The photoresist outside the second exposure area is etched.
7. The chip sealing ring protection method according to claim 6, characterized in that: After step S4, the following steps are also included: S5. Thinning the passivation layer outside the side wall of the chip body.
8. The chip sealing ring protection method according to claim 7, characterized in that: The thickness of the passivation layer outside the side wall of the chip body is greater than or equal to 0 um and less than or equal to 2 um.
9. A chip processing device, characterized in that: Processing a chip according to the chip sealing ring protection method according to any one of claims 1 to 8, wherein the chip processing equipment comprises a first photomask and a second photomask; The first photomask can form a plurality of first exposure areas on the wafer substrate for forming a chip body; The second photomask can form a plurality of second exposure areas on the wafer substrate, wherein the second exposure area includes a body area and a thickened area arranged at an outer circle of the body area; The contour of the first exposure area is within the range of the contour of the main area, and the contour of the main area is within the range of the contour of the thickened area.
10. The chip processing equipment according to claim 9, characterized in that: The width of the thickened area is greater than or equal to 1 um and less than or equal to 3 um.