Package substrate and method of manufacturing the same

Abstract

The present application provides a packaging substrate and a manufacturing method thereof. The packaging substrate includes a circuit structure formed on one side of a core board body having a core layer, so that the other side of the core board body is used as a ball mounting side. Thus, the number of layers of the packaging substrate is reduced, and the total thickness of the packaging substrate is advantageously reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor packaging technology, and more particularly to a packaging substrate that can meet the requirement of thinning and a manufacturing method thereof. BACKGROUND

[0002] With the vigorous development of the electronic industry, electronic products tend to be light, thin, short and small in shape, and high performance, high function and high speed in function. Therefore, to meet the requirements of high integration and miniaturization of semiconductor devices, packaging substrates with thinning, low warping, high-density wiring and other designs are often used in packaging processes.

[0003] However, in the manufacturing method of the existing packaging substrate, the existing equipment has a risk of damage to the board thickness condition, thereby limiting its processing capacity for thinner substrates. Therefore, when producing packaging substrates that meet the design requirements of thinning and low warping, special equipment with special specifications needs to be set up, which makes it difficult to reduce production costs.

[0004] Therefore, how to overcome the problems of the above-mentioned prior art has become a pressing issue to be solved. SUMMARY

[0005] The present application aims to provide a packaging substrate and a manufacturing method thereof to solve at least one of the above problems.

[0006] In view of the defects of the above-mentioned prior art, the present application provides a packaging substrate, comprising: a core board body, including a core layer having opposite first and second sides, a plurality of through holes communicating the first and second sides, dielectric layers formed on the opposite sides of the core layer and in the through holes, a plurality of vias formed in the dielectric layers of the through holes and corresponding to each of the through holes, a plurality of hollow conductive columns each formed in the corresponding via, a plug material formed in the hollow conductive column, and a first wiring layer and a second wiring layer formed on the dielectric layers of the first and second sides and electrically connected to the hollow conductive column, wherein the first wiring layer formed on the dielectric layer of the first side has a plurality of ball pads; an insulating layer formed on the dielectric layer of the first side of the core layer, so that the first wiring layer of the first side of the core board body is embedded in the insulating layer; and a wiring structure provided on the dielectric layer of the second side of the core layer and electrically connected to the second wiring layer of the second side of the core board body.

[0007] The present application also provides a method for manufacturing a package substrate, comprising: providing a plurality of core board bodies, wherein each of the core board bodies comprises a core layer having opposite first and second sides, a plurality of through holes communicating the first and second sides of the core layer, dielectric layers formed on the opposite sides of the core layer and the through hole walls, a via hole formed in the dielectric layer of the through hole and corresponding to each of the through holes, a hollow conductive column formed in each of the via holes, a plug material formed in the hollow conductive column, and a first wiring layer and a second wiring layer formed on the dielectric layers of the first and second sides, respectively, and electrically connected to the hollow conductive column, wherein the first wiring layer formed on the dielectric layer of the first side has a plurality of ball pads; laminating the core board bodies on the opposite sides of a carrier by an insulating layer, so that the first wiring layer of the first side of the core board body is embedded in the insulating layer; forming a circuit structure on the dielectric layer of the second side of the core layer, and electrically connecting the circuit structure to the second wiring layer of the second side of the core board body; and removing the carrier to expose the insulating layer.

[0008] In an embodiment of the package substrate and the method for manufacturing the same, the material of the dielectric layer is different from that of the plug material.

[0009] In an embodiment of the package substrate and the method for manufacturing the same, the dielectric layer comprises an ABF film (Ajinomoto build-up film).

[0010] In an embodiment of the package substrate and the method for manufacturing the same, the thickness of the dielectric layer formed on the opposite sides of the core layer and the through hole walls is ≥ 50 µm.

[0011] In an embodiment of the package substrate and the method for manufacturing the same, the circuit structure comprises at least one dielectric layer formed on the core board body and at least one circuit layer formed on the dielectric layer.

[0012] In an embodiment of the package substrate and the method for manufacturing the same, the material of the dielectric layer is the same as that of the dielectric layer.

[0013] In an embodiment of the package substrate, the insulating layer is formed with a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads of the first side of the core board body. Accordingly, in an embodiment of the method for manufacturing the package substrate, after removing the carrier, a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads of the first side of the core board body are formed, so that the insulating layer serves as a solder mask.

[0014] In an embodiment of the package substrate and the method for manufacturing the same, a first solder mask layer is further formed on the circuit structure.

[0015] In one embodiment of the foregoing package substrate, the insulating layer is formed with a plurality of insulating layer openings exposing the ball pads on the first side of the core board body, and the package substrate further comprises a second anti-soldering layer formed on the insulating layer and having openings corresponding to the insulating layer openings, so that the ball pads are exposed in the insulating layer openings and the openings. Accordingly, in one embodiment of the foregoing package substrate manufacturing method, after the carrier is removed, a plurality of insulating layer openings exposing the ball pads on the first side of the core board body are formed; and a second anti-soldering layer having openings corresponding to the insulating layer openings is formed on the insulating layer, so that the ball pads are exposed in the insulating layer openings and the openings.

[0016] In one embodiment of the foregoing package substrate and manufacturing method, the core board body further comprises a bonding layer formed on the surfaces of the first and second sides of the core layer and the through holes, between the core layer and the dielectric layer.

[0017] In one embodiment of the foregoing package substrate and manufacturing method, the bonding layer is an organic coating or an inorganic coating.

[0018] In one embodiment of the foregoing package substrate and manufacturing method, the material forming the organic coating is a polymer.

[0019] In one embodiment of the foregoing package substrate and manufacturing method, the polymer is selected from at least one of the group consisting of polyoxylene, polyamide, and poly-p-xylylene.

[0020] In one embodiment of the foregoing package substrate and manufacturing method, the material forming the inorganic coating comprises silica sand with a diameter of 20-50 microns and a roughness Ra of 1-200 microns.

[0021] As can be seen from the above, in the package substrate and manufacturing method of the present application, the first side of the core layer is used as the ball grid array side to reduce the number of layers of the package substrate, so that the total thickness of the package substrate is advantageously reduced compared to the prior art.

[0022] Furthermore, by using the ball grid array design of the first side of the core layer, the core board body has a conventional ball pad size, a conductive pillar pitch, and a diameter of the through holes, so that the substrate with the through holes can be made into the core board body for use in a BGA specification package substrate regardless of the design of the wiring structure, thereby saving process time.

[0023] In addition, since the cracks on the perforated surface of the core layer are covered by the dielectric layer, the dielectric layer can provide a barrier and protection function to prevent metal ions from diffusing into the core layer during subsequent electroplating processes and to prevent crack expansion. Moreover, the dielectric layer is filled in the perforation first, and then the dielectric layer is drilled to form a through hole, which is beneficial to the metal of the conductive layer adhering to the dielectric layer as a seed layer.

[0024] In addition, the first side of the core layer is used as a ball planting side to directly contact the circuit board with solder balls, thereby shortening the conductive path and reducing signal loss. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figures 1A-1H A cross-sectional schematic view of a first embodiment of a manufacturing method of a packaging substrate of the present application.

[0026] Figure 1H-1 A cross-sectional schematic view of a packaging substrate with a bonding layer of the first embodiment of the present application.

[0027] Figures 2A-2D A cross-sectional schematic view of a second embodiment of a manufacturing method of a packaging substrate of the present application.

[0028] Figure 2D-1 A cross-sectional schematic view of a packaging substrate with a bonding layer of the second embodiment of the present application.

[0029] The reference signs are as follows:

[0030] 1, 2 packaging substrate

[0031] 1a core board body

[0032] 10 core layer

[0033] 10a first side

[0034] 10b second side

[0035] 100 perforation

[0036] 101 crack

[0037] 11 dielectric layer

[0038] 110 through hole

[0039] 12 conductive layer

[0040] 13 plug material

[0041] 14a first wiring layer

[0042] 14b second wiring layer

[0043] 140 ball planting pad

[0044] 15 hollow conductive pillar

[0045] 16 wiring structure

[0046] 160 dielectric layer

[0047] 161 wiring layer

[0048] 17 first anti-wiring layer

[0049] 27 second anti-wiring layer

[0050] 170 anti-wiring layer opening

[0051] 720 insulating layer opening

[0052] 270 opening

[0053] 22 bonding layer

[0054] 7 carrier

[0055] 70 board body

[0056] 71 copper foil

[0057] 72 insulating layer

[0058] 8 base material DETAILED DESCRIPTION

[0059] Other advantages and effects of the present application can be easily understood by those skilled in the art from the content disclosed in the present specification.

[0060] It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of the present specification are merely used to facilitate the understanding and reading of the content disclosed in the present specification by those skilled in the art, and do not have technical substantive significance in defining the conditions for implementing the present application, so any modification of the structures, change of the proportional relationship, or adjustment of the size, without affecting the effects that can be produced by the present application and the purposes that can be achieved, should still fall within the scope of the technology disclosed by the present application. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in the present specification are merely for the convenience of clear description, and not for defining the scope of implementation of the present application, and the change or adjustment of the relative relationship without substantial change of the technical content should also be considered as the scope of implementation of the present application.

[0061] Figures 1A-1H Cross-sectional schematic view of a first embodiment of a method for manufacturing the package substrate 1 of the present application.

[0062] As Figure 1AAs shown, a core layer 10 is provided, having opposing first sides 10a and second sides 10b. A plurality of through holes 100 are formed in the core layer 10, connecting the first sides 10a and the second sides 10b, and dielectric layers 11 are formed on the opposing sides of the core layer 10 and in the through holes 100.

[0063] In this embodiment, the core layer 10 is made of a high-hardness dielectric material, such as glass, ceramic, silicon carbide (SiC), AlO2, or a high-rigidity composite material with a modulus of 50 to 100 GPa, to avoid the problem of warping of the encapsulation substrate 1.

[0064] Furthermore, multiple perforations 100 can be formed by means of laser ablation, hydrofluoric acid (HF) etching, plasma etching, mechanical drilling, etc., penetrating the first side 10a and the second side 10b of the core layer 10.

[0065] In addition, the dielectric layer 11 can be an ABF film (Ajinomoto build-up film), prepreg (PP), polybenzoxazole (PBO), polyimide (PI), or other dielectric materials. It can be formed on the first side 10a and the second side 10b of the core layer 10 by lamination or molding and filled into the perforation 100.

[0066] like Figure 1B As shown, multiple through holes 110 corresponding to each of the through holes 100 are formed in the dielectric layer 11 of each through hole 100 by means such as laser or mechanical drilling, and conductive layers 12 are formed on the dielectric layer 11 on both sides of the core layer 10 and in each through hole 110. The conductive layer 12 can be a metal layer such as copper, and can be used as a seed layer.

[0067] In this embodiment, the perforation 100 is cylindrical, and the through-hole 110 is, for example, a biconical shape resembling an hourglass. It should be understood that the perforation 100 and the through-hole 110 can also be other hole shapes. In addition, the dielectric layer 11 covers the core layer 10, so the depth of the through-hole 110 is greater than that of the perforation 100, and the diameter of the through-hole 110 is smaller than that of the perforation 100.

[0068] Furthermore, the thickness of the dielectric layer 11 on both sides of the core layer 10 should be ≥50 µm, and after the via 110 is formed, the thickness of the dielectric layer 11 on the wall of the through hole 100 should also be maintained at ≥50 µm.

[0069] like Figure 1CAs shown, the via material 13 is formed in the via hole 110 to make a substrate 8. By filling the via hole 110 with the via material 13, the cost of process and material can be reduced.

[0070] In this embodiment, the via material 13 can be an ink material formed by filling methods such as injection, plugging or coating. For example, the paste ink material is injected into the via hole 110 and heated for several hours to cross-link the molecules in the ink material and evaporate the solvent. After the ink is solidified, a ceramic roller is used to polish and flatten the surface of the conductive layer 12 on the opposite sides of the core layer 10 and the excess ink of the conductive layer 12 protruding in the via hole 110, so that the ink only fills the via hole 110 without covering the surface of the conductive layer 12.

[0071] Furthermore, the ink material is mainly composed of epoxy ink composites, which have physical properties such as viscosity of 25 to 55 Pa.s, glass transition temperature (Tg) of 145 to 180°C and / or Young's modulus ≥ 3 GPa. Further, the epoxy ink composites can be cured to form the via material 13 by heating at 180°C for 2 hours.

[0072] As shown, the conductive layer 12 on the dielectric layer 11 is patterned by a wiring process to form a first wiring layer 14a and a second wiring layer 14b on the dielectric layer 11 of the first side 10a and the second side 10b of the core layer 10, respectively, and the conductive layer 12 in the via hole 110 is a hollow conductive pillar 15 to form a core board body 1a. Figure 1D As shown, the core board body 1a is combined on the opposite sides of a carrier 7, respectively, wherein the core board body 1a is combined with the carrier 7 by its first side 10a.

[0073] Figure 1E As shown, the core board body 1a is combined on the opposite sides of a carrier 7, respectively, wherein the core board body 1a is combined with the carrier 7 by its first side 10a.

[0074] In this embodiment, the carrier 7 is a double capacity bonding material such as a copper clad laminate (CCL), so that the core board body 1a is pressed on the copper foils 71 on both sides of the board body 70 of the carrier 7 by the insulating layer 72, so that the first wiring layer 14a of the first side 10a of the core board body 1a is embedded in the insulating layer 72. For example, the insulating layer 72 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) with glass fiber or other dielectric materials.

[0075] ​Therefore, in the production process of the package substrate 1 of the present embodiment, by the design of the carrier 7, it is helpful to improve the yield of fine line width / line space (L / S) in subsequent patterned line build-up operation in a symmetrical manner.

[0076] Furthermore, if a thinner substrate 8 is used, by the arrangement of the carrier 7, not only is it beneficial for handling or transportation in the process, but also the yield can be doubled.

[0077] As shown in Figure 1F , a patterned line build-up operation in a symmetrical manner is performed to form a line structure 16 electrically connected to the second wiring layer 14b on the second side 10b of each core board body 1a. Then, a first anti-solder layer 17 is formed on the line structure 16.

[0078] In the present embodiment, the line structure 16 includes at least one dielectric layer 160 formed on the core board body 1a and at least one line layer 161 formed on the dielectric layer 160 and electrically connected to the second wiring layer 14b. For example, a build-up process is used to electroplate metal (such as copper material) or other means to manufacture the line structure 16 of two layers of dielectric layer 160 and two layers of line layer 161 of the present embodiment.

[0079] Furthermore, the dielectric layer 160 can be the same material as the dielectric layer 11, such as ABF film (Ajinomoto build-up film) or other dielectric material, and the line layer 161 is copper material, such as using Redistribution layer (RDL) specifications.

[0080] In addition, part of the surface of the line layer 161 is exposed outside the first anti-solder layer 17 as an electrical contact pad. For example, a plurality of anti-solder layer openings 170 are formed on the first anti-solder layer 17, which expose the line layer 161.

[0081] In addition, the line structure 16 and the core board body 1a share four layers of wiring, and the line width / line space (L / S) of the three layers from the outermost line layer 161 to the second wiring layer 14b on the second side 10b are sequentially, for example, 5 / 5, 8 / 10 and 15 / 15 microns (um), and the first wiring layer 14a on the first side 10a includes a plurality of ball pads 140. It should be understood that the number of wiring layers of the line structure 16 can be determined as needed, and is not limited to the above two layers.

[0082] As shown in Figure 1G , the board body 70 of the carrier 7 is removed to retain the copper foil 71 on the insulating layer 72.

[0083] In this embodiment, the first side 10a of the core plate 1a serves as the ball-planting side, while its second side 10b serves as the layer-addition side. For example, the width of the first wiring layer 14a (ball-planting pad 140) of the first side 10a is greater than, less than, or equal to the width of the perforation 100.

[0084] like Figure 1H As shown, the copper foil 71 is first removed to expose the insulating layer 72, and then a plurality of insulating layer openings 720 are formed on the insulating layer 72 to expose the first wiring layer 14a (ball pad 140).

[0085] In this embodiment, the insulating layer 72 can be used as a solder resist, thus eliminating the need to form another solder resist layer.

[0086] Therefore, the packaging substrate 1 and its manufacturing method in this embodiment mainly reduce the number of layers of the packaging substrate 1 by using the first side 10a of the core layer 10 as the ball-planting side. Thus, compared with the prior art, the total thickness of the packaging substrate 1 is advantageous for thinning.

[0087] Furthermore, thanks to the ball grid array design of the first side 10a of the core layer 10, the core board 1a has conventional ball-side pad size, hollow conductive pillar spacing 15, and through-hole diameter 100. Therefore, regardless of the wiring design of the circuit structure 16, the substrate 8 with through-hole 100 and via 110 can be made into the core board 1a for use in BGA-specification packaging substrates, thus saving process time.

[0088] In addition, since the cracks on the surface of the perforation 100 of the core layer 10 have been covered by the dielectric layer 11, the dielectric layer 11 can provide a barrier and protection function to prevent metal ions from diffusing into the core layer 10 during subsequent electroplating processes and to avoid crack expansion. Furthermore, the present invention first fills the perforation 100 with the dielectric layer 11 and then drills the dielectric layer 11 to form a through hole 110, which is beneficial for the metal of the conductive layer 12 to adhere to the dielectric layer 11 and be used as a seed layer.

[0089] In addition, by using the first side 10a of the core layer 10 as the ball-mounting side, solder balls (not shown) can be used to directly contact the circuit board, thereby shortening the conductive path and reducing signal loss.

[0090] Figures 2A-2D This is a cross-sectional schematic diagram of a second embodiment of the manufacturing method of the packaging substrate 2 of the present invention. The difference between this embodiment and the first embodiment lies in the configuration of the solder resist layer, so the similarities will not be described again below.

[0091] like Figure 2A As shown, at Figure 1F In the process shown, only the circuit structure 16 is fabricated, but the first solder resist layer 17 is not formed on the circuit structure 16.

[0092] As shown in Figure 2B the plate body 70 of the carrier 7 is removed to leave the copper foil 71 on the insulating layer 72.

[0093] As shown in Figure 2C the copper foil 71 is removed to expose the insulating layer 72, and a plurality of insulating layer openings 720 are formed on the insulating layer 72 to expose the first wiring layer 14a (solder ball pad 140).

[0094] As shown in Figure 2D a first solder resist layer 17 and a second solder resist layer 27 are formed on the circuit structure 16 and the insulating layer 72, respectively.

[0095] In the present embodiment, part of the surface of the circuit layer 161 is exposed to the first solder resist layer 17, and the first wiring layer 14a (solder ball pad 140) is exposed to the second solder resist layer 27. For example, a plurality of openings 270 are formed on the second solder resist layer 27 to expose the first wiring layer 14a (solder ball pad 140), and the openings 270 correspond to the insulating layer openings 720 of the insulating layer 72 as shown in Figure 2C and a plurality of solder resist openings 170 are formed on the first solder resist layer 17 to expose the circuit layer 161, so that the exposed surface of the circuit layer 161 serves as an electrical contact pad.

[0096] In some embodiments, according to the above two embodiments, in order to improve the adhesion of the surface of the core layer 10 and the wall surface of the through hole 100, a bonding layer 22 can be formed on the opposite sides of the core layer 10 and the wall surface of the through hole 100 as needed, and then the dielectric layer 11 is bonded by the bonding layer 22.

[0097] Furthermore, the bonding layer 22 can be an organic coating layer formed by a chemical process, for example, deposition of an organic polymer such as polyphenylene oxide (PPO), polyamide, or poly-dimethylbenzene (PD). Further, a thin organic coating layer can be formed by a chemical vapor deposition (CVD) method to improve isolation, corrosion resistance, and protection of the surface of the high-stiffness core layer 10, with a thickness of, for example, 1 nanometer to 100 micrometers, and the organic coating layer can penetrate into the crack 101 to limit the expansion of the crack 101, as shown in Figure 1H-1 and Figure 2D-1 the bonding layer 22 of the organic coating layer penetrates into the crack 101 of the core layer 10 and reduces the dielectric constant (Dk) of the core layer 10 to 2.5 to 5 (1 GHz), for example, 2.5, 2.65, 2.7, 2.8, 2.9, 3.0, 3.2, 3.5, 3.7, 4.0, 4.2, 4.5, 4.7, and 5.0 (1 GHz).

[0098] In another aspect, the bonding layer 22 can also be an inorganic coating layer formed by a physical process to form Van der waals force. For example, sandblasting using silica sand with a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns can not only remove the oxides and impurities on the core layer 10, but also increase the surface area of the core layer 10, thus helping to improve the adhesion of the dielectric layer 11 formed on the core layer 10 of high hardness material. Therefore, in a specific embodiment, the bonding layer 22 is formed by silica sand containing a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

[0099] The present application also provides a packaging substrate 1, 2, comprising a core board body 1a, an insulating layer 72 and a circuit structure 16.

[0100] The core board body 1a comprises a core layer 10, a plurality of through holes 100, a dielectric layer 11, a plurality of through holes 110, a plurality of hollow conductive columns 15, a plug material 13 and a first wiring layer 14a and a second wiring layer 14b.

[0101] The core layer 10 has opposite first and second sides 10a and 10b.

[0102] The through holes 100 are formed in the core layer 10 and communicate the first and second sides 10a and 10b.

[0103] The dielectric layer 11 is formed on the opposite sides and the walls of the through holes 100 of the core layer 10.

[0104] The through holes 110 are formed in the dielectric layer 11 of the walls of the through holes 100 and correspond to each of the through holes 100.

[0105] The hollow conductive columns 15 are each formed in the corresponding through holes 110.

[0106] The plug material 13 is formed in the hollow conductive columns 15.

[0107] The first and second wiring layers 14a and 14b are respectively formed on the dielectric layer 11 of the first and second sides 10a and 10b and electrically connected to the hollow conductive columns 15, wherein the first wiring layer 14a on the dielectric layer 11 of the first side 10a has a plurality of ball pads 140.

[0108] The insulating layer 72 is formed on the dielectric layer 11 of the first side 10a of the core layer 10, so that the first wiring layer 14a of the first side 10a of the core board body 1a is embedded in the insulating layer 72.

[0109] The circuit structure 16 is disposed on the dielectric layer 11 of the second side 10b of the core layer 10 and electrically connected to the second wiring layer 14b of the second side 10b of the core board body 1a.

[0110] In an embodiment, the material of the dielectric layer 11 is different from the material of the via 13.

[0111] In an embodiment, the dielectric layer 11 comprises an ABF film (Ajinomoto build-up film).

[0112] In an embodiment, the thickness of the dielectric layer 11 formed on the opposite sides of the core layer 10 and the wall surface of the through hole 100 is ≥ 50 µm.

[0113] In an embodiment, the circuit structure 16 comprises at least one dielectric layer 160 formed on the core board body 1a and at least one circuit layer 161 formed on the dielectric layer 160.

[0114] In an embodiment, the material of the dielectric layer 160 is the same as the material of the dielectric layer 11.

[0115] In an embodiment, the insulating layer 72 is formed with a plurality of insulating layer openings 720 penetrating the insulating layer 72 to expose the solder ball pads 140 of the first side 10a of the core board body 1a, so that the insulating layer 72 serves as a solder mask.

[0116] In an embodiment, the package substrate 1, 2 further comprises a first solder mask layer 17 formed on the circuit structure 16.

[0117] In an embodiment, the insulating layer 72 is formed with a plurality of insulating layer openings 720 penetrating the insulating layer 72 to expose the solder ball pads 140 of the first side 10a of the core board body 1a; and the package substrate 1, 2 further comprises a second solder mask layer 27 formed on the insulating layer 72 and having openings 270 corresponding to the insulating layer openings 720, so that the solder ball pads 140 are exposed in the insulating layer openings 720 and the openings 270.

[0118] In an embodiment, the core board body 1a further comprises a bonding layer 22 formed on the surfaces of the opposite first side 10a and second side 10b of the core layer 10 and the surface of the through hole 100, so as to be located between the core layer 10 and the dielectric layer 11.

[0119] In an embodiment, the bonding layer 22 is an organic coating or an inorganic coating.

[0120] In an embodiment, the material of the organic coating is a polymer, and the thickness of the organic coating is, for example, 1 nanometer to 100 micrometers.

[0121] In one embodiment, the polymer is selected from at least one of the group consisting of polyoxymethylene, polyamide, and parylene.

[0122] In one embodiment, the material forming the inorganic coating layer includes silica sand having a diameter of 20-50 microns and a roughness Ra of 1-200 microns.

[0123] In summary, the package substrate and the manufacturing method thereof of the present application mainly use the first side of the core layer as the ball grid array side to reduce the number of layers of the package substrate, so that the total thickness of the package substrate is beneficial to be thinned.

[0124] Furthermore, by the ball grid array design of the first side of the core layer, the core board body has the conventional ball grid array side pad size, the conductive pillar pitch, and the diameter of the through hole, so that the substrate with the through hole and the via can be made into the core board body for the package substrate of the BGA specification, so that the process time can be saved.

[0125] In addition, the present application covers the cracks on the surface of the through hole of the core layer with the dielectric layer, which can act as a barrier between the core layer and the conductive layer to prevent the diffusion of metal ions into the core layer during the electroplating process. The dielectric layer can also provide a protection function to prevent the package substrate from breaking due to crack expansion. Moreover, the present application fills the dielectric layer in the through hole first, and then drills the dielectric layer to form the via, which is beneficial to the metal of the conductive layer adhering to the dielectric layer as a seed layer.

[0126] In addition, the present application uses the first side of the core layer as the ball grid array side to directly contact the circuit board with the solder balls thereon, so that the conductive path can be shortened to reduce signal loss.

[0127] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the claims.

Claims

1. A method of fabricating a package substrate, the method comprising: The method comprises: providing a core layer having opposite first and second sides; forming a plurality of through holes in the core layer, the through holes being in communication with the first and second sides, and forming a dielectric layer on the first and second sides of the core layer and in each of the through holes; forming a plurality of vias in the dielectric layer of each of the through holes, and forming a conductive layer on the dielectric layer of the first and second sides of the core layer and in each of the vias; forming a plug material on the conductive layer in each of the vias; performing a patterning process on the conductive layer on the dielectric layer to form a first wiring layer and a second wiring layer on the dielectric layer of the first and second sides of the core layer, respectively, and the conductive layer in each of the vias serving as a hollow conductive pillar electrically connecting the first wiring layer and the second wiring layer to form a core board body, wherein the first wiring layer formed on the dielectric layer of the first side has a plurality of ball pads; bonding the core board body on opposite sides of a carrier by an insulating layer, such that the first wiring layer of the first side of the core board body is embedded in the insulating layer; forming a circuit structure on the dielectric layer of the second side of the core layer, and electrically connecting the circuit structure to the second wiring layer of the second side of the core board body; and removing the carrier to expose the insulating layer.

2. The method of claim 1, wherein The material of the dielectric layer is different from that of the plug material.

3. The method of claim 2, wherein The dielectric layer comprises an ABF film.

4. The method of claim 1, wherein The circuit structure comprises at least one dielectric layer formed on the core board body and at least one circuit layer formed on the dielectric layer.

5. The method of claim 4, wherein The material of the dielectric layer is the same as that of the dielectric layer.

6. The method of claim 1, wherein The method further comprises, after removing the carrier, forming a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads of the first side of the core board body, such that the insulating layer serves as a solder mask.

7. The method of claim 1, wherein The method further comprises forming a first solder mask layer on the circuit structure.

8. The method of claim 1, wherein The method further comprises, after removing the carrier, forming a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads of the first side of the core board body; and forming a second solder mask layer on the insulating layer having openings corresponding to the insulating layer openings, such that the ball pads are exposed in the insulating layer openings and openings.

9. The method of claim 1, wherein The core board body further comprises a bonding layer formed on the surfaces of the opposite first and second sides of the core layer and the surfaces of the through holes, between the core layer and the dielectric layer.

10. The method of claim 9, wherein the encapsulation substrate is formed by a method comprising: The bonding layer is an organic coating or an inorganic coating, wherein the material forming the organic coating is selected from at least one of the group consisting of polyoxylene, polyamide and poly-p-xylylene, and the material forming the inorganic coating comprises silica sand having a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

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