A New High-voltage, High-gain, Wide-range Operational Amplifier

Abstract

A novel high-voltage, high-gain, wide-range operational amplifier relates to the technical field of integrated circuits, and includes an input stage circuit, a gain bootstrap circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a third-stage amplifier circuit, and a Miller capacitor connected in sequence, wherein: the single-ended output terminal of the first-stage amplifier circuit is connected to the input terminal of the second-stage amplifier circuit; the second-stage amplifier circuit is a common-source amplifier circuit, and its output terminal is connected to the input terminal of the third-stage amplifier circuit, and the output terminal of the second-stage amplifier circuit is also used as the output terminal of the operational amplifier; the third-stage amplifier circuit is a common-drain amplifier circuit, and the Miller capacitor is connected between the output terminal of the third-stage amplifier circuit and the single-ended output terminal of the first-stage amplifier circuit. The present invention adopts gain bootstrap to increase the circuit gain, utilizes negative feedback to stabilize the voltage of each node, and introduces a structure for flexibly adjusting the zero pole of the operational amplifier, so that the overall operational amplifier meets the use requirements under high voltage.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a novel high-voltage, high-gain, wide-range operational amplifier. Background Art

[0002] To achieve high gain, traditional operational amplifiers often have multiple stages of op amps cascaded. The more stages of op amps there are, the higher the gain, but the more poles are introduced, the faster the gain drops, and the lower the bandwidth. This is why the gain and bandwidth are negatively correlated.

[0003] In the prior art, there are various op amp structures, some of which increase the input amplitude, some increase the gain, and some reduce the noise. For example, patent CN104079246B "A fully differential operational amplifier with low power consumption, high slew rate, and high gain-bandwidth product" provides an op amp with low power consumption, high slew rate, and high gain-bandwidth product. The patent uses an input stage current extraction current structure to reduce the effective resistance, and adds a slew rate enhancement circuit to increase the slew rate of the op amp and reduce power consumption. This structure is more suitable for scenarios where the gain requirement is not high and the device operating voltage is relatively low, but it is not suitable for scenarios with high gain requirements.

[0004] Another example is patent CN107301308B "A constant transconductance full-swing operational amplifier", whose circuit structure is aimed at two-stage amplification, and the Miller compensation capacitor therein still adopts the traditional method of being connected between the output end of the subsequent stage amplifier circuit and the output end of the previous stage amplifier circuit. Summary of the invention

[0005] The purpose of the present invention is to propose an operational amplifier with high gain and wide input range according to high voltage application scenarios, adopt gain bootstrapping to increase circuit gain, use negative feedback to stabilize the voltage of each node, and introduce a structure that flexibly adjusts the zero and pole points of the operational amplifier, so that the overall operational amplifier can meet the use requirements under high voltage.

[0006] In order to achieve the above objectives, the technical solution adopted by the present invention is: a new type of high-voltage, high-gain, wide-range operational amplifier, including an input stage circuit, a gain bootstrap circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a third-stage amplifier circuit, and a Miller capacitor connected in sequence, wherein:

[0007] The single-ended output terminal of the first-stage amplifier circuit is connected to the input terminal of the second-stage amplifier circuit;

[0008] The second-stage amplifier circuit is a common-source amplifier circuit, whose output terminal is connected to the input terminal of the third-stage amplifier circuit, and the output terminal of the second-stage amplifier circuit also serves as the output terminal of the operational amplifier;

[0009] The third-stage amplifier circuit is a common-drain amplifier circuit, and the Miller capacitor is connected between the output end of the third-stage amplifier circuit and the single-ended output end of the first-stage amplifier circuit.

[0010] Furthermore, the input stage circuit includes a first PMOS tube and a second PMOS tube connected with a common source, wherein the gate of the first PMOS tube serves as the non-inverting input terminal of the operational amplifier, the gate of the second PMOS tube serves as the inverting input terminal of the operational amplifier, and the sources of the first PMOS tube and the second PMOS tube are connected to a current source.

[0011] Furthermore, the gain bootstrap circuit includes a third NMOS tube and a fourth NMOS tube, and the first-stage amplifier circuit includes a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube, wherein:

[0012] The gate of the third NMOS tube is connected to the drain of the sixth NMOS tube and the drain of the first PMOS tube, the drain of the third NMOS tube is connected to the current source and the gate of the eighth NMOS tube, and the source of the third NMOS tube is grounded;

[0013] The gate of the fourth NMOS tube is connected to the drain of the fifth NMOS tube and the drain of the second PMOS tube, the drain of the fourth NMOS tube is connected to the current source and the gate of the seventh NMOS tube, and the source of the fourth NMOS tube is grounded;

[0014] The gate of the fifth NMOS tube is connected to the gate of the sixth NMOS tube and the drain of the seventh NMOS tube, the drain is connected to the source of the seventh NMOS tube, and the source is grounded;

[0015] The drain of the sixth NMOS tube is connected to the source of the eighth NMOS tube, and the source thereof is grounded;

[0016] The drain of the seventh NMOS tube is connected to the current source;

[0017] The drain of the eighth NMOS tube is connected to the current source, and the drain of the eighth NMOS tube also serves as the single-ended output end of the first-stage amplifier circuit.

[0018] Furthermore, the specific structure of the second-stage amplifier circuit is: the gate of the ninth NMOS tube serves as its input terminal, its drain is connected to the current source, and the source is grounded; the drain of the ninth NMOS tube serves as the output terminal of the second-stage amplifier circuit and also as the output terminal of the operational amplifier.

[0019] Furthermore, the specific structure of the third-stage amplifier circuit is as follows: the gate of the tenth PMOS tube serves as the input end of the third-stage amplifier circuit, its source serves as the output end of the third-stage amplifier circuit and is connected to the current source, and its drain is grounded.

[0020] The beneficial effects of the present invention are:

[0021] (1) Introducing a gain bootstrap circuit to improve the disadvantage of insufficient gain of the operational amplifier;

[0022] (ii) Due to the introduction of a gain bootstrap circuit and the folded cascode structure, it is often used as a differential operational amplifier. The operational amplifier in the present invention is used as a single-ended output operational amplifier, and a differential-to-single-ended structure is required internally. The negative feedback loop is changed compared to the traditional operational amplifier, that is, the nodes that are most affected by PVT are placed in the negative feedback network, so that the operating point of the operational amplifier is more stable.

[0023] (iii) A new structure is introduced to adjust the phase margin without affecting the gain of the op amp, so that the zero-pole adjustment of the op amp is more flexible. The zero point position can be flexibly adjusted without affecting the low-frequency gain, thereby compensating the secondary point and improving the phase margin of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the circuit structure of an embodiment of the present invention;

[0025] Figure 2 It is a partial circuit structure diagram of embodiments M3 and M8 of the present invention;

[0026] Figure 3 It is a simplified model diagram of the circuits of M3 and M8 of the embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the input, amplification and feedback parts of the traditional differential op amp structure;

[0028] Figure 5 It is a schematic diagram of the traditional Miller compensation structure;

[0029] Figure 6 It is a simplified schematic diagram of the Miller compensation structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] Figure 1 A specific embodiment of the present invention is a novel high-voltage, high-gain, wide-range operational amplifier, comprising an input stage circuit, a gain bootstrap circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a third-stage amplifier circuit, and a Miller capacitor C1 connected in sequence, wherein:

[0032] The input stage circuit includes a first PMOS tube M1 and a second PMOS tube M2 connected with a common source, wherein the gate of the first PMOS tube M1 serves as the in-phase input terminal V of the operational amplifier. IN1The gate of the second PMOS tube M2 is used as the inverting input terminal V of the operational amplifier. IN2 , the source electrodes of the first PMOS tube M1 and the second PMOS tube M2 are connected to a current source;

[0033] The gain bootstrap circuit includes a third NMOS tube M3 and a fourth NMOS tube M4, and the first-stage amplifier circuit includes a fifth NMOS tube M5, a sixth NMOS tube M6, a seventh NMOS tube M7 and an eighth NMOS tube M8, wherein:

[0034] The gate of the third NMOS tube M3 is connected to the drain of the sixth NMOS tube M6 and the drain of the first PMOS tube M1, the drain of the third NMOS tube M3 is connected to the current source and the gate of the eighth NMOS tube M8, and the source of the third NMOS tube M3 is grounded;

[0035] The gate of the fourth NMOS tube M4 is connected to the drain of the fifth NMOS tube M5 and the drain of the second PMOS tube M2, the drain thereof is connected to the current source and the gate of the seventh NMOS tube M7, and the source thereof is grounded;

[0036] The gate of the fifth NMOS tube M5 is connected to the gate of the sixth NMOS tube M6 and the drain of the seventh NMOS tube M7, the drain is connected to the source of the seventh NMOS tube M7, and the source is grounded;

[0037] The drain of the sixth NMOS tube M6 is connected to the source of the eighth NMOS tube M8, and the source thereof is grounded;

[0038] The drain of the seventh NMOS tube M7 is connected to the current source;

[0039] The drain of the eighth NMOS transistor M8 is connected to the current source, and the drain of the eighth NMOS transistor M8 is also connected to the input end of the second stage amplifier circuit as the single-ended output end of the first stage amplifier circuit;

[0040] The second-stage amplifier circuit is a common-source amplifier circuit, and has the following specific structure: the gate of the ninth NMOS tube M9 is used as its input terminal, the drain is connected to the current source, and the source is grounded; the drain of the ninth NMOS tube M9 is used as the output terminal of the second-stage amplifier circuit and connected to the input terminal of the third-stage amplifier circuit, and the drain of the ninth NMOS tube M9 is also used as the output terminal of the operational amplifier;

[0041] The third-stage amplifier circuit is a common-drain amplifier circuit, that is, a source follower, and has a specific structure as follows: the gate of the tenth PMOS tube M10 serves as the input end of the third-stage amplifier circuit, its source serves as the output end of the third-stage amplifier circuit and is connected to a current source, and its drain is grounded;

[0042] The Miller capacitor C1 is connected between the output end of the third-stage amplifier circuit, namely the source of the tenth PMOS transistor M10, and the single-ended output end of the first-stage amplifier circuit, namely the drain of the eighth NMOS transistor M8.

[0043] The working principle and beneficial effects of the embodiments of the present invention are specifically analyzed below:

[0044] This embodiment adopts a folded cascode structure. In order to have a wider input voltage range, M3 and M4 are used as MOS tubes for gain bootstrapping to improve the overall gain of the operational amplifier. The main structure of the first-stage amplifier circuit is composed of M7, M8, M5, and M6, where M5 and M6 are used for differential to single-ended conversion, and M7 and M8 are common-gate tubes. M9 is the second-stage amplifier circuit, M10 is the third-stage amplifier circuit, i.e., the source follower, and C1 is the Miller capacitor.

[0045] (I) Analysis of the principle of increasing gain:

[0046] like Figure 1 As shown, in this embodiment, M3 and M4 are gain-bootstrapped MOS tubes. Now, the simplified model of M3 and M8 is derived. The structure of the circuit of M3 and M8 is shown in FIG. Figure 2 As shown, the simplified model of the M3 and M8 circuits is as follows Figure 3 shown.

[0047] First, a small signal model analysis is performed, such as Figure 3 As shown, according to Figure 3 Take the KCL equation in the middle column:

[0048]

[0049] According to the above formula, the gain A can be calculated V =V OUT / V IN

[0050]

[0051] Simplify the above formula and use r 3 、r 8 >>R 0 , then we can get:

[0052]

[0053] It can be seen that by using gain bootstrapping, the circuit gain can be magnified by about g m3 R 0 times, greatly improving the gain.

[0054] (II) Negative feedback network analysis:

[0055] In this embodiment, the function of M5 and M6 in the first stage amplifier circuit is to convert differential to single-ended. Figure 3 The traditional structure shown is the common source and common gate. Figure 3The traditional structure is a standard differential op amp structure, an op amp composed of a folded cascode and a gain bootstrap. IN2 The end is the negative feedback end of the op amp. According to the application of traditional differential op amps, the drains of M7 and M8 should be used as the output end of the op amp V OUTP 、V OUTN However, in actual applications, the op amp has only single-ended output. One side of M8 is used as the output port of the first-stage amplifier circuit and connected to the second-stage amplifier circuit to further increase the gain. If this structure is used for single-ended output, because V IN2 The end is the negative feedback end. It can be seen that M4 and M7 form a negative feedback network, but with V OUT The port does not form negative feedback. Therefore, in the PVT simulation, the voltage on the M7 side changes greatly and is more sensitive to temperature changes, resulting in inconsistent voltages on both sides of M7 and M8, making V IN2 With V IN1 The voltage difference between them becomes larger, and the offset voltage is larger. To solve this problem, this embodiment introduces Figure 1 The structure of M5 and M6 is used as a differential to single-ended structure. IN2 As the negative feedback network end, V IN2 With the op amp V OUT A negative feedback path is formed between them, and the negative feedback node is connected to the drain of M7 instead of the source. If the negative feedback node is connected to the drain of M5, that is, the source of M7, although the overall operational amplifier can also form a negative feedback network, in the PVT bias simulation, the drain of M7 directly determines the voltage difference between M7 and M8. The change of the drain voltage of M7 will affect V IN2 With V IN1 Therefore, the drain of M7 is included in the negative feedback path, making the drain voltage of M7 relatively stable, and the working state of the op amp is more stable in the PVT bias simulation.

[0056] (III) Structural analysis of adjusting phase margin:

[0057] like Figure 6 As shown, Figure 6 The circuit is not the actual circuit of this embodiment, but in order to simplify the analysis process and highlight the advantages of this structure, the first stage amplifier circuit in this embodiment is simplified and modified into a traditional common source stage circuit. Figure 6 , the second and third stage amplifier circuits remain unchanged, but Figure 6 Renumber the MOS tubes. Figure 6 M11 and M12 in the circuit both use a common source amplifier circuit, and M13 uses a common drain amplifier circuit, that is, a source follower. Figure 5 This is a schematic diagram of a traditional Miller compensation structure.

[0058] For the sake of simplicity, the following analysis method uses Miller approximation and introduces a general formula for op amp gain, as follows:

[0059]

[0060] In the above formula, z represents the zero point, ω represents the pole, and AV0 represents the low-frequency gain. According to this formula, we can write Figure 5 The gain expression of the traditional Miller compensation structure is:

[0061] Without considering parasitic capacitance, Figure 5 The main pole of the circuit is:

[0062]

[0063] The sub-point is:

[0064]

[0065] The solution of the zero point is as follows. According to the definition of the zero point, when s = s z When V OUT (s z )=0, we can get:

[0066] V G1 s z C 3 =g m15 V G15

[0067] The zero point is found to be:

[0068]

[0069] The final gain formula is:

[0070]

[0071] Among them A V14 , A V15 They represent the low-frequency gain of the first-stage amplifier circuit and the second-stage amplifier circuit respectively. According to the effect of Miller capacitance, the primary and secondary poles are separated. While the primary pole is moved to the low frequency, a zero point is introduced at the second stage. The zero point can compensate the secondary pole by adjusting the position, thereby improving the phase margin of the circuit. According to the above formula, the way to adjust the zero point is to directly adjust C 3 , you can also adjust g m15 In actual circuits, if you want to move the zero point to a low frequency and compensate for the secondary pole, you can increase C 3 However, the capacitance cannot be increased continuously. Increasing the capacitance will lead to the disadvantages of decreased slew rate and reduced op amp speed. m15If the zero point is located, the gain of the second-stage op amp will decrease, thus affecting the overall circuit gain.

[0072] To solve the above problems, we introduce Figure 6 The circuit structure shown in the figure can be written using the same method. Figure 6 The gain expression of .

[0073] Figure 6 The poles of are as follows, the main poles:

[0074]

[0075] There are two sub-peaks, namely:

[0076]

[0077] and:

[0078]

[0079] The zero point solution is as follows:

[0080] V G12 s z C 2 =g m13 V G13

[0081] V G12 A 12 =V G1

[0082] We can get:

[0083]

[0084] according to Figure 6 The formula can be obtained:

[0085]

[0086] It can be seen that the low-frequency gain of the above formula is mainly affected by A V11 , A V12 Influence, according to the zero point formula, the zero point position is affected by A V12 , g m13 , C 2 Impact, compared to Figure 5 The zero point formula can be obtained by adjusting g m13 With C 2 Adjusting the zero position improves phase margin without changing low frequency gain.

Claims

1. A novel high-voltage, high-gain, wide-range operational amplifier, characterized in that: It includes an input stage circuit, a gain bootstrap circuit, a first stage amplifier circuit, a second stage amplifier circuit, a third stage amplifier circuit, and a Miller capacitor (C1) connected in sequence, wherein: The single-ended output terminal of the first-stage amplifier circuit is connected to the input terminal of the second-stage amplifier circuit; The second-stage amplifier circuit is a common-source amplifier circuit, whose output terminal is connected to the input terminal of the third-stage amplifier circuit, and the output terminal of the second-stage amplifier circuit also serves as the output terminal of the operational amplifier; The third-stage amplifier circuit is a common-drain amplifier circuit, and the Miller capacitor (C1) is connected between the output end of the third-stage amplifier circuit and the single-ended output end of the first-stage amplifier circuit.

2. A novel high-voltage, high-gain, wide-range operational amplifier according to claim 1, characterized in that: The input stage circuit comprises a first PMOS tube (M1) and a second PMOS tube (M2) connected with a common source, wherein the gate of the first PMOS tube (M1) serves as the in-phase input terminal (V IN1 ), the gate of the second PMOS tube (M2) serves as the inverting input terminal (V IN2 ), the source electrodes of the first PMOS tube (M1) and the second PMOS tube (M2) are connected to a current source.

3. A novel high-voltage, high-gain, wide-range operational amplifier according to claim 2, characterized in that: The gain bootstrap circuit includes a third NMOS tube (M3) and a fourth NMOS tube (M4), and the first-stage amplification circuit includes a fifth NMOS tube (M5), a sixth NMOS tube (M6), a seventh NMOS tube (M7) and an eighth NMOS tube (M8), wherein: The gate of the third NMOS tube (M3) is connected to the drain of the sixth NMOS tube (M6) and the drain of the first PMOS tube (M1), the drain of the third NMOS tube (M3) is connected to the current source and the gate of the eighth NMOS tube (M8), and the source of the third NMOS tube (M3) is grounded; The gate of the fourth NMOS tube (M4) is connected to the drain of the fifth NMOS tube (M5) and the drain of the second PMOS tube (M2), the drain of the fourth NMOS tube (M4) is connected to the current source and the gate of the seventh NMOS tube (M7), and the source of the fourth NMOS tube (M4) is grounded; The gate of the fifth NMOS tube (M5) is connected to the gate of the sixth NMOS tube (M6) and the drain of the seventh NMOS tube (M7), the drain is connected to the source of the seventh NMOS tube (M7), and the source is grounded; The drain of the sixth NMOS tube (M6) is connected to the source of the eighth NMOS tube (M8), and the source thereof is grounded; The drain of the seventh NMOS tube (M7) is connected to the current source; The drain of the eighth NMOS tube (M8) is connected to a current source, and the drain of the eighth NMOS tube (M8) also serves as a single-ended output end of the first-stage amplifier circuit.

4. A novel high-voltage, high-gain, wide-range operational amplifier according to claim 1, characterized in that: The specific structure of the second-stage amplifier circuit is: The gate of the ninth NMOS tube (M9) serves as its input terminal, its drain is connected to the current source, and its source is grounded. The drain of the ninth NMOS tube (M9) serves as the output terminal of the second stage amplifier circuit and also as the output terminal of the operational amplifier.

5. A novel high-voltage, high-gain, wide-range operational amplifier according to claim 1, characterized in that: The specific structure of the third-stage amplifier circuit is: The gate of the tenth PMOS transistor (M10) serves as the input terminal of the third-stage amplifier circuit, the source of the tenth PMOS transistor (M10) serves as the output terminal of the third-stage amplifier circuit and is connected to the current source, and the drain of the tenth PMOS transistor (M10) is grounded.

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