A method for reducing the packet loss rate of a gigabit ethernet network based on clock homology design

Abstract

The application relates to a method for reducing the packet loss rate of a gigabit Ethernet network based on clock homologous design and belongs to the field of computer networks. The clock input sources of an E2000D chip, a KD5886 chip and other load devices are designed as homologous clocks, so that the network packet loss rate of an SGMII gigabit Ethernet interface between an E2000 series processor platform and other terminal processors is greatly reduced, the transmission rate of effective data is greatly improved, double-avoidance strategies are adopted at the firmware layer and the application layer, and the network communication packet loss rate of the SGMII interface between different processor platforms is reduced to 0%. The design adopted by the application can realize 100% localization, has self-controllability and referenceability, can be applied to all processor platforms of the E2000 series, and greatly improves the stability of network data communication between the SGMII interface and other loads.

Description

Technical Field

[0001] The present invention belongs to the field of computer networks, and in particular relates to a method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design. Background Art

[0002] With the rapid development of the Internet, when users use the ping command to access a destination, there is a small probability of packet loss during data transmission. After packet loss, the sender needs to wait for retransmission due to timeout (increasing response time), increasing overall data transmission latency and reducing the transmission rate of effective data (reducing throughput).

[0003] Currently, the intelligent machines used in unmanned vehicle systems include a master control device that performs system data exchange and chassis management functions. This device plays a vital role in the informatization and intelligentization of unmanned vehicle systems. The master control device's data exchange functionality is based on the domestically produced KD5886 processor platform, while the chassis management functionality is based on the domestically produced E2000D processor platform. To ensure chassis management while simultaneously monitoring the accuracy of exchanged data, the KD5886 and E2000D implement network communication via the SGMII interface.

[0004] Test data feedback from the debugging phase showed that the SGMII interface between KD5886 and E2000D would experience packet loss when pinging packets, with a network packet loss rate as high as 50%, seriously affecting data integrity and making it impossible to monitor the accuracy of data exchange during chassis management. Summary of the Invention

[0005] (1) Technical issues to be resolved

[0006] The technical problem to be solved by the present invention is how to provide a method for reducing the packet loss rate of a Gigabit Ethernet network based on a clock homology design, so as to solve the problem that the SGMII interface between KD5886 and E2000D will lose packets when pinging packets, resulting in a high network packet loss rate.

[0007] (2) Technical solution

[0008] In order to solve the above technical problems, the present invention proposes a method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design. The method is implemented by a main control device, which includes two major modules: a switching module based on the KD5886 chip and a management module based on the E2000D chip. The SGMII interface of the E2000D communicates with the SGMII interface of the KD5886.

[0009] The KD5886 chip is used for switching functions. The clock type involved is GE_CLK. This clock can configure the interface mode of the KD5886 to SGMII form, and lead to the Gigabit Copper electrical port of the 1000Base-T protocol through the external first PHY chip XPHY0111H form. The clock frequency is 25MHz.

[0010] The clock type involved in the E2000D chip is SGMII_REFCLK, which enables the normal use of the SGMII interface of the E2000D and leads to the Gigabit Copper electrical port through an external second PHY chip. The clock frequency is 100MHz.

[0011] The E2000D chip also includes an RGMII interface. The RGMII interface uses an external PHY chip to connect to the Gigabit Copper electrical port for data exchange with the Gigabit Copper electrical port of other load devices. The clock type involved is XTAL_O, which enables the PHY chip to oscillate and work at a clock frequency of 25MHz.

[0012] (3) Beneficial effects

[0013] The present invention proposes a method for reducing the packet loss rate of a Gigabit Ethernet network based on a clock homology design. By designing the clock input sources of the E2000D chip, the KD5886 chip, and other load devices as homology clocks, the present invention significantly reduces the network packet loss rate of the SGMII Gigabit Ethernet interface between the E2000 series processor platform and other terminal processors, greatly improving the transmission rate of effective data. At the same time, a dual avoidance strategy is adopted at the firmware layer and the application layer, reducing the packet loss rate of the SGMII interface network communication between different processor platforms to 0%.

[0014] The present invention designs the clock input sources of all load devices with data communication in the master device to be homologous clocks, so that the MAC layer receiving-end logic and SerDes recovery logic inside the load's SGMII controller are based on homologous design. This greatly avoids the data sampling errors caused by the frequency deviation difference between the receiving-end clock and the reply clock caused by non-homologous board-level design, and further avoids the error reporting at the driver layer of the processor platform.

[0015] The design adopted by the present invention can achieve 100% localization, has independent controllability and reference value, and is applicable to all processor platforms of the E2000 series, greatly improving the stability of network data communication between its SGMII interface and other loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a functional principle block diagram of the method for reducing the packet loss rate of a gigabit network based on clock homology design of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below with reference to the accompanying drawings and examples.

[0018] The purpose of this patent is to propose a method for reducing the packet loss rate of gigabit networks based on the Feiteng E2000D processor platform. This method targets the SGMII interface of the Feiteng E2000 series processors and uses a homogenous clock input source for the load devices that interact with data on the board. This significantly reduces the packet loss rate of gigabit networks. This method is applied to the main control device of the unmanned vehicle intelligent machine, improving the stability of system data synchronization.

[0019] like Figure 1 As shown, the present invention provides a method for reducing the packet loss rate of a Gigabit Ethernet network based on a clock homology design. The method is implemented by a master control device, which mainly includes two modules: a switching module based on a KD5886 chip and a management module based on an E2000D chip. In order for the management module to monitor the data stability of the switching module in real time, the SGMII interface of the E2000D and the SGMII interface of the KD5886 need to communicate.

[0020] The KD5886 chip is used for switching functions. The main clock type involved is GE_CLK. This clock can configure the interface mode of the KD5886 to SGMII form, and lead to the Gigabit Copper electrical port (hereinafter referred to as Gigabit Copper electrical port) of the 1000Base-T protocol through the external first PHY chip XPHY0111H (hereinafter referred to as PHY chip). The clock frequency is 25MHz (KD5886 performs internal frequency multiplication processing);

[0021] The main clock type involved in the E2000D chip is SGMII_REFCLK, which ensures the normal use of the SGMII interface of the E2000D and leads to the Gigabit Copper electrical port through an external second PHY chip. The clock frequency is 100MHz.

[0022] The E2000D chip also includes an RGMII interface. The RGMII interface uses an external PHY chip to connect to the Gigabit Copper electrical port for data exchange with the Gigabit Copper electrical port of other load devices. The main clock type involved is XTAL_O, which enables the PHY chip to oscillate and work at a clock frequency of 25MHz.

[0023] Furthermore, the KD5886 chip communicates with the second PHY chip of the E2000D chip through the first PHY chip using the Gigabit Copper electrical port.

[0024] Furthermore, the E2000D chip can be connected to a third PHY chip via the RGMII interface, and the third PHY chip can be connected to a fourth PHY chip via the Gigabit Copper electrical port. The fourth PHY chip is connected to other load devices via the RGMII interface.

[0025] Furthermore, the third PHY chip and the fourth PHY chip are provided with XTAL_O clock by a clock generator.

[0026] The clock generator used in the present invention is a domestic clock chip - TGEN631BHQFIGR of Chengdu Dianke Xingtuo Technology Co., Ltd. The chip is driven by a domestic passive crystal - SMD3225 of Wuhan Haichuang Electronics Co., Ltd. The passive crystal provides 48.000MHz drive for the clock generator.

[0027] The clock generator chip can be internally configured through firmware, with its clock output modes set to 100MHz differential and 25MHz single-ended. This design ensures that the KD5886 chip's GE_CLK clock, the E2000D chip's SGMII_REFCLK clock, and the PHY chip's XTAL_O clock are all generated by the same clock generator chip. This improves communication efficiency between the E2000D's SGMII interface and the KD5886's SGMII interface, avoiding data sampling errors caused by chip clock frequency differences. This design significantly reduces the SGMII interface's gigabit network packet loss rate, with measured data showing a drop from 50% to less than 2%, a significant improvement.

[0028] Based on the hardware, it has been verified that there is no packet loss when the SGMII interface of the KD5886 chip communicates with the SGMII interfaces of other domestic chips. Therefore, the network packet loss rate of the SGMII interface communication between the KD5886 chip and the E2000D chip is caused by the E2000D. According to feedback from the manufacturer, the domestic process design of the E2000D chip, due to cross-process differences, leads to large variations in the junction temperature within the chip. When the temperature drift of the SerDes receiving clock on the SGMII interface exceeds the constraint range, resulting in a 2% probability of data transmission errors, which manifests as network ping packet loss.

[0029] To address this issue, a digital loopback diagnostic test from the MAC layer to the local PHY is added to the E2000D chip's firmware layer, before the MAC driver is loaded in uboot / UEFI. This verifies messages on the loopback path, enabling a retraining and locking process for the relevant on-chip clock phases. After training is complete, normal operation resumes, further reducing network packet loss.

[0030] Furthermore, a monitoring thread for error packets and on-chip PHY / PCS link status is created at the E2000D chip's application layer. When the number of error packets exceeds a certain threshold or the PCS link fails, the monitoring thread triggers a reset of the E2000D chip's SerDes (SerDes) and relocks the KD5886 chip's SerDes phase. These firmware and application layer operations further reduce the SGMII interface network data loss rate to 0%.

[0031] The present invention greatly reduces the network packet loss rate of the SGMII Gigabit Ethernet interface between the E2000 series processor platform and other terminal processors by designing the clock input sources of the E2000D chip, the KD5886 chip and other load devices to be the same clock, greatly improves the transmission rate of effective data, and simultaneously adopts a dual avoidance strategy at the firmware layer and the application layer, reducing the SGMII interface network communication packet loss rate between different processor platforms to 0%.

[0032] The present invention designs the clock input sources of all load devices with data communication in the master device to be homologous clocks, so that the MAC layer receiving-end logic and SerDes recovery logic inside the load's SGMII controller are based on homologous design. This greatly avoids the data sampling errors caused by the frequency deviation difference between the receiving-end clock and the reply clock caused by non-homologous board-level design, and further avoids the error reporting at the driver layer of the processor platform.

[0033] The design adopted by the present invention can achieve 100% localization, has independent controllability and reference value, and is applicable to all processor platforms of the E2000 series, greatly improving the stability of network data communication between its SGMII interface and other loads.

[0034] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design, characterized in that: The method is implemented through a main control device, which includes two modules: a switching module based on a KD5886 chip and a management module based on an E2000D chip. The SGMII interface of the E2000D communicates with the SGMII interface of the KD5886. The KD5886 chip is used for switching functions. The clock type involved is GE_CLK. This clock can configure the interface mode of the KD5886 to SGMII form, and lead to the Gigabit Copper electrical port of the 1000Base-T protocol through the external first PHY chip XPHY0111H form. The clock frequency is 25MHz. The clock type involved in the E2000D chip is SGMII_REFCLK, which enables the normal use of the SGMII interface of the E2000D and leads to the Gigabit Copper electrical port through an external second PHY chip. The clock frequency is 100MHz. The E2000D chip also includes an RGMII interface. The RGMII interface connects to an external PHY chip, which leads to a Gigabit Copper electrical port for data exchange with the Gigabit Copper electrical port of other load devices. The clock type involved is XTAL_O, which enables the PHY chip to oscillate and operate at a clock frequency of 25MHz. in, The GE_CLK clock of the KD5886 chip, the SGMII_REFCLK clock of the E2000D chip, and the XTAL_O clock of the PHY chip are all generated by the same clock generator chip, which improves the communication efficiency between the SGMII interface of the E2000D and the SGMII interface of the KD5886.

2. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 1, characterized in that: The KD5886 chip communicates with the second PHY chip of the E2000D chip using the Gigabit Copper electrical port through the first PHY chip.

3. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 1, characterized in that: The E2000D chip can be connected to a third PHY chip via the RGMII interface. The third PHY chip can be connected to a fourth PHY chip via the Gigabit Copper electrical port. The fourth PHY chip is connected to other load devices via the RGMII interface.

4. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 1, wherein: The clock generator is the domestically produced clock chip TGEN631BHQFIGR.

5. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 4, characterized in that: The clock generator is driven by the domestic passive crystal SMD3225, which provides 48.000MHz drive for the clock generator.

6. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 3, characterized in that: The clock generator chip is internally configured through firmware, and its clock output mode is a differential clock of 100MHz and a single-ended clock of 25MHz.

7. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 6, characterized in that: Before the MAC driver is loaded in the firmware layer of the E2000D chip (i.e., uboot / UEFI), a digital loopback diagnostic test from the MAC layer to the local PHY is added.

8. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 7, characterized in that: By verifying the messages on the loopback path, the retraining and locking process of the relevant clock phases within the chip is realized. After the training is completed, the subsequent normal working process is entered to further reduce the network packet loss rate.

9. The method for reducing the packet loss rate of a Gigabit Ethernet network based on clock homology design according to claim 6, wherein: A monitoring thread for error packets and on-chip PHY / PCS layer link status is created at the application layer of the E2000D chip. When the number of error packets detected exceeds a certain threshold or the PCS link fails, the monitoring thread triggers the E2000D chip SerDes to reset and relock the KD5886 chip SerDes phase.

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