LDPC (Low Density Parity Check) decoding method and architecture for Ethernet protocol

Abstract

In the information transmission process, due to the influence of channel noise, a receiving end often receives wrong information, in order to correct the wrong information, a solution is provided for an LDPC encoding and decoding algorithm, and correction can be carried out through the algorithm when the received information is wrong by adding redundant data. 802.3 an is a subset of the IEEE802.3 an standard, defines a physical layer specification of using the Ethernet on a copper cable, is mainly applied to 10GBase-T, namely a 10 gigabit Ethernet, and adopts LDPC (Low Density Parity Check) codes to improve the reliability of data transmission. The LDPC decoding algorithm hardware architecture suitable for the 802.3 an protocol comprises a variable node module, a check node module, an information internet module and a parameter-configurable post-processing module, a half-layer decoding mode is adopted, and the decoding process is optimized, so that a decoder is enabled to meet the requirement of throughput rate, and the decoding efficiency is improved. And a high-performance decoding operation process is realized.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to an LDPC decoder hardware architecture of an Ethernet protocol. Background Art

[0002] In the process of information transmission, the receiver receives erroneous information due to noise interference. In order to solve this problem, people have studied many encoding and decoding algorithms, mainly by adding redundant information to protect the data. The encoded data can be restored to the original data at the data receiving end through a specific decoding algorithm. LDPC (Low Density Parity Check Codes) code was proposed by Gallager in 1962, and it has a performance close to the Shannon limit. RS-LDPC is a subset of LDPC code, and its check matrix is ​​generated by RS code. It has excellent performance and low hardware implementation complexity, and is adopted by the 802.3an protocol.

[0003] Since RS-LDPC does not have a quasi-cyclic check matrix like QC-LDPC (Quasi Cyclic Low Density Parity Check Codes), taking RS-LDPC (2048, 1723) given in the 802.3an protocol as an example, although the submatrix of the check matrix of RS-LDPC has only one element 1 in each row and column like QC-LDPC, the information transmission between the variable node and the check node cannot be achieved by a simple cyclic shift. The present invention adopts a multi-layer multiplexer architecture to achieve information transmission. The method has certain flexibility and can automatically generate an information transmission network through a script to reduce the complexity of the design.

[0004] The LDPC decoder used the belief propagation algorithm for decoding in the early days. This algorithm is strictly derived based on probability theory to obtain the probability of each information bit being 0 or 1. However, the algorithm has many multiplication calculations and is very complex. If the probability information is converted into the form of log-likelihood ratio, the multiplication operation can be converted into an addition operation. This algorithm is called the sum-product algorithm. However, this algorithm involves nonlinear operations and is difficult to implement through hardware. Subsequent studies have found that by utilizing the monotonicity of nonlinear operations, the minimum value or second minimum value in the information can be used to approximate the result of the nonlinear operation. This algorithm is called the minimum sum algorithm. The offset minimum sum algorithm adds an offset value to the minimum value and the second minimum value on the basis of the minimum sum algorithm. This value is determined through simulation. In order to make the information transmitted by the check node to the variable node closer to the belief propagation algorithm, this algorithm is widely used because it is easier to implement in hardware and has less hardware overhead.

[0005] The formula for offset minimum sum algorithm decoding is:

[0006]

[0007] Among them, L (m) (q ij ) represents the information transmitted from variable node i to check node j in the mth iteration, L(P i ) represents the initial channel information corresponding to the i-th bit, L (m) (r ji ) is the information passed from the check node j to the variable node i in the mth iteration, C i\j represents all connected check nodes in the i-th column of the check matrix except the j-th row, R j\i represents all connected variable nodes in the j-th row of the check matrix except the i-th column, and β is the offset constant.

[0008] For RS-LDPC (2048, 1723) code, if BPSK modulation is used and the offset minimum sum algorithm is used for decoding, the offset constant is set to 1. When SNR = 5, the bit error rate BER has reached the error floor, which is on the order of 10. -10 The reason for this phenomenon is that the decoding falls into a specific trap set structure, which makes it impossible for the error bit to be flipped to the correct value. Such performance cannot meet the requirements of the protocol. For the 10Gbps throughput requirement, if the decoding architecture of the whole layer decoding is adopted, the hardware overhead is too large. Therefore, an efficient decoding hardware architecture for RS-LDPC codes is needed, and the decoding algorithm is optimized to solve the problems of high design complexity, large resource overhead and poor decoder performance. Summary of the invention

[0009] Purpose of the invention: The present invention implements a layered decoder according to the requirements of the 802.3an protocol. A multi-layer configurable multiplexer architecture is adopted to address the complexity of RS-LDPC information routing. The interconnection can be automatically configured through scripts, thereby reducing the complexity of the overall design. The design adopts a half-layer decoding method. The decoder processes the data of 1024 variable nodes and 64 check nodes in each cycle. A single iteration consumes 12 clock cycles. Compared with the full-layer decoding method, the hardware overhead is saved while meeting the throughput requirements. In order to address the problem of the bit error rate entering the error floor, a configurable multi-parameter post-processing module is adopted to further improve the decoder performance and has certain flexibility. At the same time, the present invention proposes a simple early termination module. After the check node processes the information of all layers, a judgment value will be generated. The decoding success is judged and the decoding process is terminated according to the result of this judgment value. The use of this early termination module can save hardware resources and improve the performance of the decoder.

[0010] Technical solution: The present invention discloses a LDPC decoder hardware architecture suitable for the 802.3an protocol, characterized in that the hardware architecture mainly includes 1024 variable node modules, 64 check node modules, variable node data transmission network, check node data transmission network, early termination module, and configurable multi-parameter post-processing module, which can continuously perform decoding operations on the input channel information to be decoded. The specific architecture is as follows Figure 1 As shown:

[0011] The main modules of this hardware architecture include:

[0012] Verification node processing module: uses the offset minimum sum algorithm to obtain the message transmitted by the variable node, and outputs the minimum value and the second minimum value and the corresponding variable node symbol product.

[0013] Variable node processing module: responsible for storing the input initial channel information LLR value, where each variable node stores two LLR values, uses the information transmitted by the check node to calculate the posterior value corresponding to the node, and outputs the decoding information when the decoding is completed according to the information transmitted by the early termination module and the set maximum number of iterations.

[0014] Post-processing module: uses configurable enhancement / weakening information to process the signal transmitted from the check node, and transmits the enhancement or weakening information to the variable node processing module.

[0015] Variable node to check node interconnection module: This module adopts a multi-layer multiplexer structure. In a single cycle, 1024 variable node information is selected and transmitted, and a single layer of information transmission is completed in two clock cycles.

[0016] Verification node to variable node interconnection module: This module adopts a multi-layer multiplexer structure, which transmits the information of 64 verification nodes to 1024 variable nodes in a single cycle, and completes the single-layer information transmission in two clock cycles.

[0017] The overall design adopts a half-layer decoding architecture and uses an optimized minimum-sum algorithm and early termination algorithm to achieve a balance between power consumption, area, and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the hardware architecture of the RS-LDPC decoder proposed in the present invention.

[0019] Figure 2 This is the specific architecture of the variable node proposed by the present invention.

[0020] Figure 3 This is the specific architecture of the check node proposed by the present invention.

[0021] Figure 4The figure is a decoding flow chart of an embodiment of the present invention.

[0022] Figure 5 1 is a performance curve of an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to illustrate the technical solution disclosed in the present invention in detail, exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] The present invention provides a decoding architecture of an RS-LDPC decoder, the overall architecture is as follows: Figure 1 As shown, the following steps are included:

[0025] Step 1: Cache LLR information from the channel into the FIFO. When a frame of data is completely stored, the decoding process begins. When the first frame of data is processed, the second frame of data can be cached to improve the system throughput.

[0026] Step 2: Input the data read from the FIFO into the VNU module. In the first assignment cycle, the initial LLR data is assigned to register A in the VNU module. After the assignment is completed, the initialization of variable nodes 1-1024 is completed. In the second assignment cycle, the remaining half-frame data is assigned to register B in the VNU module, and the initialization of variable nodes 1025-2048 is completed. At this point, the initial LLR information of all variable nodes has completed the initialization assignment.

[0027] Step 3: In the normal iteration cycle, the offset minimum sum algorithm is used. The variable nodes perform calculations based on prior information and external information. Each cycle processes half a layer of data and sends it to the verification node. The entire layer of information is calculated and transmitted in two cycles.

[0028] Step 4: Based on the information transmitted by the variable node, the check node performs symbolic operations, searches for the minimum and second minimum values, and saves the results of the symbolic operations. The minimum and second minimum values ​​are determined using a multi-layer comparator. First, the data of the 16 variable nodes are classified and grouped. The grouped data is input into the four-choice-two module. The module outputs the minimum and second minimum values ​​of the four values ​​based on the grouped input information, and saves the maximum and minimum values ​​obtained by the module. After obtaining the maximum and minimum values ​​of the other 16 variable node information in the next cycle, the two groups of numbers are compared to obtain the maximum and minimum values ​​corresponding to the entire layer of data, and the results are sent to the variable nodes.

[0029] Step 5: After one iteration is completed, the check node outputs the symbols corresponding to the six-layer data. The early termination module first determines whether all the check equations are satisfied based on the symbol information. If so, the iteration is terminated directly and the process goes to step 7. If not, it determines whether the current number of iterations is greater than the set number of regular iterations. If not, it goes to step 3. If it exceeds the set number of regular iterations, it goes to step 6.

[0030] Step 6: In the post-processing iteration process, the data transmitted by the check node is first modified based on the sign according to the configured data, the information with negative signs is enhanced, and the information with positive signs is weakened, and then the next iteration is started from step 3. The post-processing process is divided into two parts, configuring a set of enhanced information and weakened information respectively. By configuring the post-processing parameters twice and iterating, most of the trap sets are solved and the performance of the decoder is improved.

[0031] Step 7: After the iteration is completed, a 2048-bit decoded codeword is obtained and stored in the FIFO.

[0032] The present invention designs a decoder for the LDPC code specified in the 802.3an protocol. Each cycle processes half a layer of data, with a total of six layers. A total of 12 cycles are required to complete one iteration. An optimized information interaction strategy is adopted. In view of the complexity of the internet design, a script is used to read the check matrix to generate an internet module. Therefore, the present invention can be applied to all RS-LDPC codes of the same type. In view of the problem of a high error floor of the bit error rate of the code type proposed in the 802.3an protocol, a post-processing module with configurable parameters is adopted to optimize the decoding algorithm, and the bit error rate of the decoder is reduced to 10 -12 .

Claims

1. An LDPC decoder architecture suitable for 802.3an protocol, characterized by: The algorithm hardware architecture includes 1024 variable nodes (VNU), 64 check nodes (CNU), early termination module (ET), information interconnection network (V2C_Network, C2V_Network), and a post-processing module with configurable parameters, which can achieve high-performance decoding operations while meeting protocol requirements.

2. The early termination module according to claim 1, characterized in that: During the decoding process, the verification module calculates the signed product corresponding to 32 variable nodes every two cycles, and saves the signed product result through the shift register. When the decoding is completed, the signed product result stored in the shift register is used to determine whether the decoding is completed, thereby terminating the decoding process in advance, improving the system throughput, and saving power consumption.

3. The post-processing module with configurable parameters according to claim 1, characterized in that: The module is integrated inside the variable node. After the conventional decoding cycle fails to decode successfully, two post-processings are used to enhance the information transmitted by the check nodes that do not satisfy the check equation, and to weaken the information transmitted by the check nodes corresponding to the check equation that satisfy the check equation. The present invention collects the initial log-likelihood ratio (LLR) of multiple frames falling into the trap set for simulation, and obtains two sets of post-processing information enhancement / weakening parameters (STG, WK). By configuring these two parameters, most trap sets can be solved and the decoding performance of the decoder can be improved.

4. The information internet network according to claim 1, characterized in that: First, data is selected, half of the variable nodes are selected in a single cycle, and data transmission between the check nodes and the variable nodes is performed by selecting the network. The interconnection network is automatically generated by reading the check matrix through the script, which greatly facilitates the construction of the same type of LDPC decoder.

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