A CAN bus communication interruption reception processing method based on ring FIFO data structure
By adopting a combination of ring FIFO data structure and additional queues in CAN bus communication, the problem of message dropping when the CAN bus communication is high is solved, and higher data reception reliability and stability are achieved.
Patent Information
- Application Number
- CN202411937368.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-04
AI Technical Summary
CAN bus communication is prone to the problem of message frame drops when the load is high, and the prior art is difficult to effectively solve.
The CAN bus communication interrupt reception processing method based on the ring FIFO data structure is adopted. By setting a large FIFO depth within the allowable range of hardware resources, message information is cached, and when the reception speed and processing speed do not match, the cache capacity is dynamically expanded to avoid frame loss.
It effectively avoids the problem of message frame drop when the CAN bus communication load is high, improves the reliability and stability of data reception, especially in key application areas such as automotive electronics, reducing safety hazards.
Smart Images
Figure CN119766749A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of CAN bus communication, and in particular to a CAN bus communication interruption reception processing method based on a ring FIFO data structure. Background Art
[0002] With the rapid development of integrated circuit technology, in order to reduce the cost of wiring harness manufacturing and improve vehicle performance, OEMs began to seek a bus communication solution, and CAN bus communication technology came into being and continued to expand to industrial automation, aerospace, medical equipment, smart home, energy management and other application fields.
[0003] However, CAN bus communication is a serial communication. When the load is high, no matter what receiving method (polling or interrupt) the software adopts, there is a possibility of message frame loss, so it needs to be improved. Summary of the invention
[0004] In order to reduce the technical problem of message frame loss in CAN bus communication, the present application provides a CAN bus communication interruption reception processing method based on a ring FIFO data structure.
[0005] In a first aspect, the present application provides a CAN bus communication interruption reception processing method based on a ring FIFO data structure, comprising: Receive a request instruction, and determine whether a preset annular FIFO queue satisfies a trigger condition corresponding to a request type included in the request instruction; wherein the request type includes at least an enqueue request and a dequeue request, and the annular FIFO queue is used to cache message information; If satisfied, based on the message information contained in the request instruction and the ring FIFO queue, a processing task corresponding to the request type is performed on the message information, wherein the processing task at least includes an enqueue task for storing the message information in the ring FIFO queue, and a dequeue task for removing the message information from the ring FIFO queue; If not, the request execution result is fed back to the issuer of the request instruction based on the memory status of the current ring FIFO queue.
[0006] By adopting the above technical scheme, the triggering condition in this scheme is mainly determined based on the cache capacity of the current circular FIFO queue. For example, if the request type is an enqueue request and the current circular FIFO queue is full, it is impossible to enqueue. The corresponding request execution result may include relevant content of the request failure. If the circular FIFO queue is not full, and the remaining vacant cache bits that can be used to store messages can accommodate the request content contained in the current request instruction, it is considered that the trigger request is met and the enqueue task can be executed; and it should be emphasized that the data structure used for caching CAN messages in this application is a circular FIFO. By adopting a circular FIFO data structure as the CAN bus communication data receiving cache queue and within the scope allowed by hardware resources, a larger FIFO depth is set as much as possible, that is, the number of data caches that the FIFO can accommodate, so as to avoid the problem of CAN message frame loss when the receiving speed and processing speed do not match.
[0007] Optionally, the trigger condition includes at least: if the request type of the current request instruction is an enqueue request, then at the current moment, the circular FIFO queue does not include the message information in the current request instruction; if the request type of the current request instruction is a dequeue request, then at the current moment, the processing tasks being processed do not include processing tasks whose request type and message information are consistent with the current request instruction.
[0008] By adopting the above technical scheme, the trigger conditions are further limited in this scheme to avoid the situation where the same message information triggers the same processing task through multiple request instructions at the same time, that is, the processing tasks proposed by different request instructions are the same, thereby realizing the function of the mutual exclusion lock and ensuring the uniqueness of the data.
[0009] Optionally, if the condition is satisfied, then based on the message information included in the request instruction and the circular FIFO queue, a processing task corresponding to the request type is performed on the message information, including: If the request type is an enqueue request and the trigger condition corresponding to the enqueue request is met, determine the cache bit set required to be occupied by the message information in the current request instruction, determine the queue segment corresponding to the cache bit set, and the processing cycle included in the message information; Based on the processing cycle and the preset correspondence table, the circle corresponding to the queue segment is determined, and according to the pointing order of the processing pointer corresponding to the circle, the queue segment is added to the corresponding circle; wherein the processing cycle refers to the time from the entry to the exit of the request information, and the corresponding relationship table is used to store several circles and the processing cycle range corresponding to each circle, all circles are rings with the same center and different radii, and the processing pointer configured corresponding to each circle is used to determine the order of entry and exit of the message information stored in the queue segment on the corresponding circle; all queue segments contained in all circles are combined to form a circular FIFO queue; If the request type is a dequeue request and the trigger condition corresponding to the dequeue request is met, the dequeue task of the request information will be executed based on the message information contained in the request instruction and the circle layer and according to the moving direction of the processing pointer of the corresponding circle layer.
[0010] By adopting the above-mentioned technical scheme, since the processing cycles of different message information when executing the dequeue task may be different, it is impossible to realize the sequential dequeue of all message information through the moving speed of a single dequeue pointer. Therefore, the present application proposes that when executing the enqueue task for the message information that meets the trigger condition corresponding to the enqueue request, the message information is stored in different circles according to the processing cycle of the message information, and the order of entry and exit of all message information belonging to the same circle is uniformly controlled by the processing pointer of the corresponding circle, and the moving speeds of the processing pointers of different circles are different. In this way, the movement of the processing pointer of the corresponding circle can be used to adapt to the processing cycle of the message information of the corresponding circle, so as to realize the storage classification of the message information and the hierarchical dequeue processing of the message information.
[0011] Optionally, a buffer segment is reserved between any two adjacent queue segments belonging to the same circle layer; The method further comprises: Based on the processing cycle of the message information corresponding to each queue segment, determine the moving speed of the processing pointer of each circle when passing through the buffer segment, and adjust the moving speed and moving position of the corresponding processing pointer in real time according to the determined moving speed, so that when the processing pointer moves to any queue segment, it just reaches the processing cycle of the corresponding queue segment.
[0012] By adopting the above technical solution, since the queue segments of different circles are part of the circular FIFO queue, and since the circle is an annular area with the same center but different radius as the circular FIFO queue, there must be an empty segment (i.e., a buffer segment) between two adjacent queue segments in the circle. Since the buffer segment does not store message information, when the processing pointer points to the buffer segment, the moving speed of the processing pointer can be adjusted with the help of the buffer segment, so that the processing pointer can adapt to the processing cycle of the queue segment to be pointed to, so that when the processing pointer moves to the next queue segment, it just reaches the processing cycle of the corresponding queue segment.
[0013] Optionally, if the above conditions are not met, then based on the memory state of the current ring FIFO queue, the request execution result is fed back to the issuer of the request instruction, including: If the request type of the request instruction is an enqueue request, and the annular FIFO queue does not meet the trigger condition corresponding to the enqueue request, an insertion bit is determined in the cache bit corresponding to the annular FIFO queue according to the message information in the request instruction, and an additional queue is inserted; According to the pointing position of the enqueue pointer of the circular FIFO queue, the priorities of the enqueue pointer of the circular FIFO queue and the enqueue pointer of the additional queue are adjusted so that the enqueue pointer with a higher priority replaces the enqueue pointer with a lower priority, so as to store the message information contained in the current request instruction into the additional queue; According to the pointing position of the dequeue pointer of the circular FIFO queue, the priorities of the dequeue pointer of the circular FIFO queue and the dequeue pointer of the additional queue are adjusted, and the dequeue pointer with a higher priority replaces the dequeue pointer with a lower priority, so that when the dequeue pointer of the circular FIFO queue points to the access position, the dequeue task of the message information in the additional queue is executed; When there is a message overflow in the message information in the request instruction, a request execution result with a request failure is fed back to the issuer of the request instruction; wherein, the message overflow means that the message information exceeds the message information cache capacity available for the additional queue and the circular FIFO queue.
[0014] By adopting the above technical solution, on the basis of using the circular FIFO queue as the main data result of caching message information, if the message information of the request instruction is added to the circular FIFO queue, the circular FIFO queue will overflow, then an additional queue is added, so that the additional queue and the circular FIFO queue cooperate with each other to realize the caching of message information, that is, the circular FIFO can also have the function of dynamically increasing and decreasing the cache capacity possessed by the traditional FIFO. Further, by limiting the priority of the queue pointer and the dequeue pointer (that is, the pointer with a higher priority replaces the pointer with a higher priority), the dequeue and queue order of the message information in the additional queue can be connected and adapted with the queue entry and dequeue order of the circular FIFO queue, such as: when the dequeue pointer of the circular FIFO queue points to the insertion position, the dequeue pointer of the additional queue is used to replace the dequeue pointer of the FIFO queue, until the additional queue is empty, the dequeue pointer of the circular FIFO queue is used to replace the dequeue pointer of the additional queue.
[0015] Optionally, determining an insertion bit in a cache bit corresponding to the circular FIFO queue and inserting an additional queue includes: According to the pointing position of the queue entry pointer corresponding to the circular FIFO queue, the previous bit of the cache bit pointed to by the queue entry pointer of the circular FIFO queue at the current moment is used as the insertion bit; Based on the unqueued message information in the current request instruction, determine the additional bit set corresponding to the additional queue, the additional bit set includes the cache bits required to be occupied by the current request instruction in the preset additional queue, and establish a corresponding relationship between the insertion bit and the additional bit set; If the condition is not satisfied, the request execution result is fed back to the issuer of the request instruction based on the memory state of the current ring FIFO queue, and further includes: Whenever an insertion position is determined, and the corresponding relationship between the insertion position and the additional bit set is determined, the priority of the enqueue pointer of the additional queue is defined to be higher than the priority of the enqueue pointer of the circular FIFO queue, and the position pointed to by the enqueue pointer of the additional queue is adjusted to store the message information that has not been queued in the request instruction into the cache bit corresponding to the additional bit set corresponding to the current insertion position in the additional queue; until the message information corresponding to the cache bit corresponding to the additional bit set is completed to be queued, the priority of the enqueue pointer of the circular FIFO queue is defined to be higher than the priority of the enqueue pointer of the additional queue; When the dequeue pointer of the circular FIFO queue points to the cache bit after the target insertion bit in the circular FIFO queue, the dequeue pointer priority of the additional queue is limited to be higher than the dequeue pointer priority of the circular FIFO queue, and the position pointed to by the dequeue pointer of the additional queue is adjusted to dequeue the message information stored in the additional bit set corresponding to the target insertion bit in the additional queue, and then the dequeue pointer priority of the circular FIFO queue is readjusted to be higher than the priority of the dequeue pointer of the additional queue; wherein the target insertion bit refers to any insertion bit.
[0016] By adopting the above technical solution, the present solution further defines the correspondence between the cache bits in the additional queue and the insertion bits of the circular FIFO queue, so that a single additional queue can be used to cache the message information required for the additional cache each time the circular FIFO queue is fully loaded when the circular FIFO queue is fully loaded multiple times.
[0017] Optionally, according to the pointing position of the enqueue pointer corresponding to the circular FIFO queue, taking the previous bit of the cache bit pointed to by the enqueue pointer of the circular FIFO queue at the current moment as the insertion bit, includes: According to the pointing position of the enqueue pointer corresponding to the circular FIFO queue, the message information is stored in the circular FIFO queue until the enqueue is stopped when the circular FIFO queue is full, and the previous bit of the cache bit pointed to by the enqueue pointer of the circular FIFO queue when the enqueue is stopped is used as the insertion bit.
[0018] By adopting the above technical solution, for the message information at the current moment, if stored in the circular FIFO queue, it will cause the FIFO queue to overflow in the opposite direction, the present application proposes to add an additional queue to dynamically expand the cache capacity of the circular FIFO queue, and the present application further limits that before the circular FIFO queue is full, the circular FIFO queue is preferentially used to cache the message information, and only when the circular FIFO queue is full will the additional queue be used to cache the remaining unqueued message information.
[0019] In a second aspect, the present application provides a CAN bus communication interruption receiving and processing system based on a ring FIFO data structure, comprising: A request trigger determination module, used to receive a request instruction and determine whether a preset annular FIFO queue satisfies a trigger condition corresponding to a request type contained in the request instruction; wherein the request type includes at least an enqueue request and a dequeue request, and the annular FIFO queue is used to cache message information; A request task processing module, configured to, if satisfied, perform a processing task corresponding to the request type on the message information based on the message information contained in the request instruction and the circular FIFO queue, wherein the processing task at least includes an enqueue task for storing the message information in the circular FIFO queue, and a dequeue task for removing the message information from the circular FIFO queue; The request result feedback module is used to feedback the request execution result to the issuer of the request instruction based on the memory status of the current ring FIFO queue if it is not satisfied.
[0020] In a third aspect, the present application provides a CAN bus communication interruption receiving and processing device based on a ring FIFO data structure, comprising a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute any method described in the first aspect.
[0021] In a fourth aspect, the present application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and execute any one of the methods described in the first aspect.
[0022] In summary, this application includes the following beneficial technical effects: In this application, a circular FIFO data structure is used as the CAN bus communication data receiving cache queue. Within the scope of hardware resources, a larger FIFO depth is set as much as possible, that is, the number of data caches that the FIFO can accommodate, to effectively avoid the problem of frame loss when the CAN bus communication load is high. For example, key components such as steering systems and braking systems in the field of automotive electronics involve important safety items. If message frame loss is very likely to cause major safety accidents. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0024] Figure 1 It is a flow chart of a CAN bus communication interruption reception processing method based on a ring FIFO data structure disclosed in an embodiment of the present application.
[0025] Figure 2 It is a logical diagram used in an embodiment of the present application to determine whether the trigger condition corresponding to the request type is met.
[0026] Figure 3It is a structural block diagram of a CAN bus communication interrupt receiving and processing system based on a circular FIFO data structure disclosed in an embodiment of the present application.
[0027] Explanation of reference numerals: 1. Request trigger determination module; 2. Request task processing module; 3. Request result feedback module. Detailed implementation manners
[0028] The following will further describe the present application in detail Figure 1-3 in conjunction with the accompanying drawings.
[0029] An embodiment of the present application discloses a CAN bus communication interrupt receiving and processing method based on a circular FIFO data structure (hereinafter simply referred to as the processing method), and its corresponding execution entity is a CAN bus communication interrupt receiving and processing system based on a circular FIFO data structure (hereinafter simply referred to as the processing system); the following will further describe Figure 1-2 in detail the specific process steps for the processing system to execute the processing method in conjunction with the accompanying drawings.
[0030] S101, Receive a request instruction, and determine whether a preset circular FIFO queue meets the trigger condition corresponding to the request type included in the request instruction; wherein, the request type at least includes an enqueue request and a dequeue request, and the circular FIFO queue is used to cache message information.
[0031] S102, If it is satisfied, then based on the message information included in the request instruction and the circular FIFO queue, execute a processing task corresponding to the request type on the message information, wherein the processing task at least includes an enqueue task for storing the message information into the circular FIFO queue, and a dequeue task for removing the message information from the circular FIFO queue.
[0032] In implementation, the present application proposes to use a circular FIFO queue to cache data. The circular FIFO queue is circular and is formed by splicing a number of cache bits; the present application will preset the FIFO depth (i.e., the cache capacity of the circular FIFO, that is, the number of cache bits) so as to set a relatively large cache capacity as much as possible within the range allowed by the hardware resources. Each data may occupy a number of cache bits.
[0033] In addition, the data cached in the present application is a message structure. Exemplarily, the message structure may specifically include a message ID, an extended frame identifier IDE, a data pointer DATA, a data length LENGTH, and a data valid bit MSB; the corresponding structure of the circular FIFO queue may include the following information: FIFO depth Max, FIFO width, received message Message X (X is a non-negative integer, and 0 ≤ X < Max), enqueue pointer EnqueueOffset, and dequeue pointer DequeueOffset.
[0034] The request instruction at least includes a request type and message information (i.e., the message structure described above), wherein the request type at least includes an enqueue request and a dequeue request. When the occurrence condition of the request instruction corresponds to the request type, such as: the occurrence condition of the request instruction whose request type is an enqueue request is when an interrupt occurs, and the occurrence condition of the request instruction whose request type is a dequeue request is when a periodic task occurs.
[0035] The trigger condition is used to determine whether the circular FIFO queue has the determination condition for executing the processing task corresponding to the request type when receiving the request instruction. If it is satisfied, the processing task corresponding to the corresponding request type will be executed, such as the enqueue task corresponding to the enqueue request to store the message information contained in the request instruction into the circular FIFO queue; or the dequeue task corresponding to the dequeue request to move the message information contained in the request instruction out of the circular FIFO queue.
[0036] Specifically, refer to Figure 2 , the specific process of judging the triggering conditions is as follows: For a request instruction whose request type is an enqueue request, it is determined whether the circular FIFO queue is full or will be in an overflow state when the request instruction is received, wherein the full state means that all cache bits contained in the current FIFO queue store data, and "will be in an overflow state" means that before the current moment, after all message information that has been received and meets the trigger condition and has not completed the enqueue task completes the enqueue task, the number of remaining vacant cache bits m in the circular FIFO queue is less than the number of cache bits N required to be occupied by the message information contained in the currently received request instruction. If the circular FIFO is not full and will not overflow, the enqueue task is performed on the message information corresponding to the current request instruction; and since the circular FIFO queue is equipped with an enqueue pointer, and the cache bit pointed to by the enqueue pointer is the location where the circular FIFO queue can store message information, and the enqueue pointer will move in a specified moving order (such as clockwise or counterclockwise) to sequentially insert the message information into the cache bit it needs to occupy. For message information that has been enqueued and not dequeued, the MSB in the message information is set to 0x01.
[0037] For a request instruction whose request type is a dequeue request, it is determined whether the annular FIFO queue is in an empty state when receiving the request instruction, that is, all cache bits in the FIFO queue are in an empty state, that is, no data is stored. If not, the dequeue task is performed for the message information corresponding to the current request execution, and since the annular FIFO queue is configured with a dequeue pointer, the cache position pointed to by the dequeue pointer is the cache position of the message information to be removed from the annular FIFO queue, and the dequeue pointer moves in a specified moving order, so the dequeue task of the message information can be realized by moving the dequeue pointer and the real-time pointing of the dequeue pointer during the movement, and when the present application receives the request instruction, the cache position corresponding to the message information contained in the request instruction is the cache position pointed to by the current dequeue pointer. For the message information that has been queued and dequeued, the MSB in the message information is set to 0x00.
[0038] Furthermore, for a request instruction whose request type is an enqueue request, the corresponding trigger condition also includes: the circular FIFO queue at the current moment does not include any data that is not stored in the message information consistent with the current request instruction; and: when the current request instruction (hereinafter referred to as instruction A) is received, for all request instructions (hereinafter referred to as instruction B) that meet the trigger conditions before the current moment and whose corresponding processing tasks have not been completed, there is no instruction B whose request type and message information are consistent with instruction A; to avoid triggering multiple enqueue requests for the same message information at the same time.
[0039] For request instructions whose request type is a dequeue request, the corresponding triggering conditions also include: at the current moment, all processing tasks that are being processed or have not been completed do not include processing tasks whose request type and message information are consistent with the current request instruction, so as to avoid triggering multiple dequeue requests for the same message information at the same time.
[0040] Optionally, the present application further defines the structure of the ring FIFO queue, and corresponding S102 includes the following sub-steps: If the request type is an enqueue request and the trigger condition corresponding to the enqueue request is met, determine the cache bit set required to be occupied by the message information in the current request instruction, determine the queue segment corresponding to the cache bit set, and the processing cycle included in the message information; Based on the processing cycle and the preset correspondence table, the circle corresponding to the queue segment is determined, and the queue segment is added to the corresponding circle according to the pointing order of the processing pointer corresponding to the circle; wherein the processing cycle refers to the time from the entry to the exit of the request information, and the correspondence table is used to store several circles and the processing cycle range corresponding to each circle. All circles are rings with the same center and different radii. The processing pointer configured corresponding to each circle is used to determine the order of entry and exit of the message information stored in the queue segment on the corresponding circle; all queue segments contained in all circles are combined to form a circular FIFO queue; If the request type is a dequeue request and the trigger condition corresponding to the dequeue request is met, the dequeue task of the request information will be executed based on the message information contained in the request instruction and the circle in which it is located and according to the moving direction of the processing pointer of the corresponding circle.
[0041] In practice, the present application presets a number of circles with the same center and different radii, each of which is a circle layer, and the circle layer with the smallest radius is defined as the first circle layer. The first circle layer corresponds to an entry pointer and an exit pointer, and all other circles except the first circle layer correspond to a processing pointer.
[0042] In addition, a corresponding relationship table is pre-stored in the processing system, and the corresponding relationship table stores the corresponding relationship between the circle layer and the processing cycle range. The processing cycle can be considered as the cycle duration of the cycle task of the request instruction corresponding to the message information, and the processing cycle range in the corresponding relationship table is a number of cycle time periods. For the request instruction that meets the trigger condition of the queue entry request, the processing system is used to determine the processing cycle range of its processing cycle in the corresponding relationship table based on the processing cycle of the cycle task corresponding to the current request instruction, and the circle layer corresponding to the corresponding processing cycle range, and then according to the number of cache bits required to be occupied by the message information contained in the request instruction (the cache bits here refer to the cache bits of the first circle layer), according to the preset pointing order of the queue pointer of the first circle layer (such as clockwise or counterclockwise), find the queue segment used to store the message information contained in the request instruction from the first circle layer, the cache bit set is the set composed of all cache bits corresponding to the queue segment, and the number of cache bits contained in the cache bit set is the number of cache bits required to be occupied by the message information as determined in the previous text.
[0043] The queue segments on all circles are combined to form a circular FIFO queue, which is the first circle. In other words, the present application divides the queue contained in the first circle into several queue segments, each of which stores the message information contained in a queue entry request instruction, and each queue segment will be translated to the corresponding circle. The processing pointers corresponding to different circles move along the circumference of the corresponding circle in a predetermined pointing order (such as clockwise or counterclockwise), and during the movement, when the processing pointer points to any queue segment of the corresponding circle, it is considered that the processing cycle of the message information corresponding to the queue segment has been reached. At this time, the processing system happens to receive a request instruction with the message information and the request type is a dequeue request. After the processing system determines that it meets the trigger condition corresponding to the dequeue request, it will perform the dequeue task on the message information in the queue segment according to the pointing order of the processing pointer.
[0044] When the message information of all queue segments completes the dequeue task, the processing system moves the vacant queue segments back to the first circle layer to reassemble all the vacant queue segments into a circular queue. When receiving the enqueue request instruction, the queue segments used to store the message information in the enqueue request instruction are separated from the first circle layer according to the preset pointing order of the enqueue pointer of the first circle layer, and then the queue segments are split from the first circle layer to their corresponding circles, and finally the splitting and splicing operations of the circular queue contained in the first circle layer are realized. In summary, this operation can realize the hierarchical storage of the enqueued message information without changing the cache capacity of the circular FIFO queue, so as to adapt to the occurrence time of the dequeue periodic tasks of different enqueued message information.
[0045] Optionally, the processing method also includes: Based on the processing cycle of the message information corresponding to each queue segment, determine the moving speed of the processing pointer of each circle when passing through the buffer segment, and adjust the moving speed and moving position of the corresponding processing pointer in real time according to the determined moving speed, so that when the processing pointer moves to any queue segment, it just reaches the processing cycle of the corresponding queue segment.
[0046] In implementation, since the first circle layer and other circles are annular circles with the same center but different radii, after the queue segments split from the first circle layer are moved to the corresponding circle layer, there will inevitably be gaps (i.e., buffer segments) between adjacent queue segments in other circles belonging to the same circle layer. Therefore, in order to enable the processing pointer to receive a request instruction with a request type of dequeue request containing the message information of the queue segment when it is in any queue segment of the straight line corresponding circle layer, the processing system is used to determine and adjust the movement speed of the processing pointer according to the processing cycle of the next queue segment of the buffer segment when the processing pointer moves and points to the buffer segment in the circle layer.
[0047] S103: If not satisfied, the request execution result is fed back to the issuer of the request instruction based on the memory status of the current ring FIFO queue.
[0048] Wherein S103 specifically includes the following sub-steps: If the request type of the request instruction is an enqueue request, and the annular FIFO queue does not meet the trigger condition corresponding to the enqueue request, then according to the message information in the request instruction and the pointing position of the enqueue pointer corresponding to the annular FIFO queue, the message information is stored in the annular FIFO queue until the annular FIFO queue is full and the enqueue is stopped, and the previous bit of the cache bit pointed to by the enqueue pointer of the annular FIFO queue when the enqueue is stopped is used as the insertion bit; Based on the unqueued message information in the current request instruction, determine the additional bit set corresponding to the additional queue, the additional bit set includes the cache bits required to be occupied by the current request instruction in the preset additional queue, and establish a corresponding relationship between the insertion bit and the additional bit set; According to the pointing position of the enqueue pointer of the circular FIFO queue, the priorities of the enqueue pointer of the circular FIFO queue and the enqueue pointer of the additional queue are adjusted so that the enqueue pointer with a higher priority replaces the enqueue pointer with a lower priority, so as to store the message information contained in the current request instruction into the additional queue; According to the pointing position of the dequeue pointer of the circular FIFO queue, the priorities of the dequeue pointer of the circular FIFO queue and the dequeue pointer of the additional queue are adjusted, and the dequeue pointer with a higher priority replaces the dequeue pointer with a lower priority, so that when the dequeue pointer of the circular FIFO queue points to the insertion position, the dequeue task of the message information in the additional queue is executed; Whenever the insertion position and the corresponding relationship between the insertion position and the additional bit set are determined, the priority of the enqueue pointer of the additional queue is set to be higher than the priority of the enqueue pointer of the circular FIFO queue, and the position pointed to by the enqueue pointer of the additional queue is adjusted to store the message information that has not been queued in the request instruction into the cache bit corresponding to the additional bit set corresponding to the current insertion position in the additional queue; until the message information corresponding to the cache bit corresponding to the additional bit set is completed to be queued, the priority of the enqueue pointer of the circular FIFO queue is set to be higher than the priority of the enqueue pointer of the additional queue; When the dequeue pointer of the circular FIFO queue points to the cache bit after the target insertion bit in the circular FIFO queue, the dequeue pointer priority of the additional queue is limited to be higher than the dequeue pointer priority of the circular FIFO queue, and the dequeue pointer pointing position of the additional queue is adjusted to dequeue the message information stored in the additional bit set corresponding to the target insertion bit in the additional queue, and then the dequeue pointer priority of the circular FIFO queue is readjusted to be higher than the dequeue pointer priority of the additional queue; wherein the target insertion bit refers to any insertion bit; When there is a message overflow in the message information in the request instruction, a request execution result with a request failure is fed back to the issuer of the request instruction; wherein, the message overflow means that the message information exceeds the message information cache capacity available for the additional queue and the circular FIFO queue.
[0049] In implementation, combined with Figure 2 , when the request type is an enqueue request and the annular FIFO is full or about to overflow, the present application will further determine the following content (hereinafter referred to as the determination content) based on the preset additional queue: whether an overflow will occur when the annular FIFO is combined with the preset additional queue. It should be explained that the preset additional queue of the present application can be considered to be an additional queue structure added on the basis of the cache capacity of the annular FIFO queue, which is used to assist the annular FIFO queue to store message information, and the additional queue in the embodiment of the present application can also be an annular FIFO queue structure, which also has an enqueue pointer and a dequeue pointer. The above determination content refers to the number of cache bits N required to be occupied by the message information contained in the currently received request instruction-the number of remaining vacant cache bits m of the annular FIFO queue≤the number of vacant cache bits P of the current additional queue.
[0050] If the determination result of the determination content is overflow, it is considered that the message information in the current request instruction has a message overflow. At this time, the request execution result with request identification is fed back to the sender of the request instruction, such as displaying a request execution result with request failure.
[0051] If the result of the determination on the determination content is no overflow, it is determined whether the current annular FIFO queue is full, then according to the cache bit currently pointed to by the enqueue pointer of the annular FIFO queue and the preset pointing order of the enqueue pointer, part of the data of the message information contained in the current request instruction is stored in the cache bit of the annular FIFO queue, until the annular FIFO queue is full, then the enqueue is stopped, and the cache bit before the cache bit pointed to by the enqueue pointer pointed to by the annular FIFO queue when the enqueue is stopped is used as the insertion bit, and according to the number of cache bits required to be occupied by the message information not currently enqueued in the additional queue, the preset pointing order of the enqueue pointer of the additional queue (such as clockwise or counterclockwise along the circumference of the additional queue), and the cache bit pointed to by the current enqueue pointer of the additional queue (the cache bit pointed to by the enqueue pointer of the additional queue is the next cache bit for data insertion preset according to the enqueue pointer), an additional bit set is determined, where the additional bit set is a set formed according to the cache bits in the additional queue used to store the message information not currently enqueued.
[0052] After determining the insertion bit and the additional bit set, establish and store the corresponding relationship between the insertion bit and the additional bit set, and adjust the priority of the enqueue pointer of the circular FIFO queue and the enqueue pointer of the additional queue at this time, that is, limit the priority of the enqueue pointer of the additional queue to be higher than the priority of the enqueue pointer of the circular FIFO queue, and the present application stipulates that the cache bit pointed to by the enqueue pointer with a higher priority will be used as the enqueue cache bit of the message information after the current moment. Therefore, at this time, since the priority of the enqueue pointer of the additional queue is higher than the priority of the enqueue pointer of the circular FIFO queue, the processing system will store the currently unqueued message information in the additional queue and the cache bit corresponding to the additional bit set under the direction of the enqueue pointer of the additional queue. After completing the enqueue task of the current message information, the priority of the enqueue pointer of the circular FIFO queue will be readjusted to be higher than the priority of the enqueue pointer of the additional queue, that is: only when the insertion bit and the additional bit set are determined, before the corresponding processing task is completed, the priority of the enqueue pointer of the additional queue will be limited to be higher than the priority of the enqueue pointer of the circular FIFO queue.
[0053] Afterwards, when the dequeue pointer of the circular FIFO queue moves to the next cache position of any insertion position (hereinafter referred to as the target insertion position) in the circular FIFO queue according to the preset pointing order, the processing system will limit the priority of the dequeue pointer of the additional queue to be higher than the priority of the dequeue pointer of the circular FIFO queue at this time, and the cache position pointed to by the dequeue pointer with a higher priority as stipulated in the present application will be used as the cache position for removing the message information after the current moment, and at the same time, according to the position of the additional bit set corresponding to the target insertion position stored in the additional queue, the cache position pointed to by the dequeue pointer of the additional queue is adjusted, so that the processing system can execute the dequeue task for the message information stored in the corresponding additional bit set under the movement and real-time pointing of the dequeue pointer of the additional queue, and then after completing the dequeue task, readjust the priority of the dequeue pointer of the circular FIFO queue to be higher than the priority of the dequeue pointer of the additional queue. From this, it can be seen that before executing the dequeue task of the message information of the cache bit pointed to by the dequeue pointer of the circular FIFO queue, the dequeue task will be performed on the message information stored in the additional bit set corresponding to the target insertion bit in the additional queue first, so that the dequeue order of the message information in the additional queue can be adapted and connected with the dequeue order of the message information in the circular FIFO queue, and always follow the first-in-first-out principle.
[0054] The embodiment of the present application also discloses a CAN bus communication interruption receiving and processing system based on a ring FIFO data structure. Figure 3 ,include: A request trigger determination module 1 is used to receive a request instruction and determine whether a preset annular FIFO queue satisfies a trigger condition corresponding to a request type contained in the request instruction; wherein the request type includes at least an enqueue request and a dequeue request, and the annular FIFO queue is used to cache message information; A request task processing module 2, configured to, if satisfied, perform a processing task corresponding to the request type on the message information based on the message information contained in the request instruction and the annular FIFO queue, wherein the communication task at least includes an enqueue task for storing the message information in the annular FIFO queue, and a dequeue task for removing the message information from the annular FIFO queue; The request result feedback module 3 is used to feedback the request execution result to the issuer of the request instruction based on the memory status of the current ring FIFO queue if it is not satisfied.
[0055] Optionally, the request task processing module 2 is further used to determine the cache bit set required to be occupied by the message information in the current request instruction, determine the queue segment corresponding to the cache bit set, and the processing cycle contained in the message information if the request type is a queue entry request and the trigger condition corresponding to the queue entry request is met; The request task processing module 2 is also used to determine the circle corresponding to the queue segment based on the processing cycle and the preset corresponding relationship table, and add the queue segment to the corresponding circle according to the pointing order of the processing pointer corresponding to the circle; wherein the processing cycle refers to the time from the entry to the exit of the request information, and the corresponding relationship table is used to store several circles and the processing cycle range corresponding to each circle, all circles are rings with the same center and different radii, and the processing pointer configured corresponding to each circle is used to determine the order of entry and exit of the message information stored in the queue segment on the corresponding circle; all queue segments contained in all circles are combined to form a circular FIFO queue; The request task processing module 2 is also used to execute the dequeue task of the request information based on the message information contained in the request instruction and the circle in which it is located, according to the moving direction of the processing pointer of the corresponding circle, if the request type is a dequeue request and the trigger condition corresponding to the dequeue request is met.
[0056] Optionally, a buffer segment is reserved between any two adjacent queue segments belonging to the same circle layer; It also includes a pointer movement adjustment module, which is used to determine the movement speed of the processing pointer of each circle layer when passing through the buffer segment based on the processing cycle of the message information corresponding to each queue segment, and adjust the movement speed and movement position of the corresponding processing pointer in real time according to the determined movement speed, so that when the processing pointer moves to any queue segment, it just reaches the processing cycle of the corresponding queue segment.
[0057] Optionally, the request result feedback module 3 is further used to determine an insertion position in the cache position corresponding to the circular FIFO queue according to the message information in the request instruction, and insert the insertion position into the additional queue if the request type of the request instruction is an enqueue request and the circular FIFO queue does not meet the trigger condition corresponding to the enqueue request; The request result feedback module 3 is also used to adjust the priority of the enqueue pointer of the circular FIFO queue and the enqueue pointer of the additional queue according to the pointing position of the enqueue pointer of the circular FIFO queue, so that the enqueue pointer with a higher priority replaces the enqueue pointer with a lower priority, so as to store the message information contained in the current request instruction in the additional queue; The request result feedback module 3 is also used to adjust the priority of the dequeue pointer of the circular FIFO queue and the dequeue pointer of the additional queue according to the pointing position of the dequeue pointer of the circular FIFO queue, and make the dequeue pointer with higher priority replace the dequeue pointer with lower priority, so that when the dequeue pointer of the circular FIFO queue points to the insertion position, the dequeue task of the message information in the additional queue is executed; The request result feedback module 3 is also used to feedback the request execution result with request failure to the issuer of the request instruction when there is a message overflow in the message information in the request instruction; wherein, the message overflow means that the message information exceeds the message information caching capacity available for the additional queue and the circular FIFO queue.
[0058] Optionally, the request result feedback module 3 is further used to use the previous bit of the cache bit pointed to by the enqueue pointer of the circular FIFO queue at the current moment as the insertion bit according to the pointing position of the enqueue pointer corresponding to the circular FIFO queue; based on the unqueued message information in the current request instruction, determine the additional bit set corresponding to the additional queue, the additional bit set includes the cache bits required to be occupied by the current request instruction in the preset additional queue, and establish a corresponding relationship between the insertion bit and the additional bit set; The request result feedback module 3 is also used to define the priority of the enqueue pointer of the additional queue to be higher than the priority of the enqueue pointer of the circular FIFO queue whenever the insertion position and the corresponding relationship between the insertion position and the additional bit set are determined, and adjust the position pointed to by the enqueue pointer of the additional queue to store the message information that has not been queued in the request instruction into the cache bit corresponding to the additional bit set corresponding to the current insertion position in the additional queue; until the message information corresponding to the cache bit corresponding to the additional bit set is completed to be queued, the priority of the enqueue pointer of the circular FIFO queue is defined to be higher than the priority of the enqueue pointer of the additional queue; The request result feedback module 3 is also used to limit the priority of the dequeue pointer of the additional queue to be higher than the priority of the dequeue pointer of the circular FIFO queue when the dequeue pointer of the circular FIFO queue points to the cache position after the target insertion position in the circular FIFO queue, and adjust the position pointed to by the dequeue pointer of the additional queue to dequeue the message information stored in the additional bit set corresponding to the target insertion position in the additional queue, and then readjust the priority of the dequeue pointer of the circular FIFO queue to be higher than the priority of the dequeue pointer of the additional queue; wherein, the target insertion position refers to any insertion position.
[0059] Optionally, the request result feedback module 3 is also used to store the message information in the circular FIFO queue according to the pointing position of the enqueue pointer corresponding to the circular FIFO queue, until the enqueue is stopped when the circular FIFO queue is full, and the previous bit of the cache bit pointed to by the enqueue pointer of the circular FIFO queue when the enqueue is stopped is used as the insertion bit.
[0060] An embodiment of the present application also discloses a CAN bus communication interruption receiving and processing device based on a ring-shaped FIFO data structure. The CAN bus communication interruption receiving and processing device based on a ring-shaped FIFO data structure includes a memory and a processor. The memory stores a computer program that can be loaded by the processor and executes the CAN bus communication interruption receiving and processing method based on the ring-shaped FIFO data structure as described above.
[0061] An embodiment of the present application also discloses a computer-readable storage medium, which stores a computer program that can be loaded by a processor and executes the CAN bus communication interruption reception processing method based on the ring FIFO data structure as described above. The computer-readable storage medium includes, for example: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.
[0062] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0063] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit the protection scope of the application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on these embodiments, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.
Claims
1. A CAN bus communication interrupt reception processing method based on a ring FIFO data structure, characterized in that: include: Receive a request instruction, and determine whether a preset annular FIFO queue satisfies a trigger condition corresponding to a request type included in the request instruction; wherein the request type includes at least an enqueue request and a dequeue request, and the annular FIFO queue is used to cache message information; If satisfied, based on the message information contained in the request instruction and the ring FIFO queue, a processing task corresponding to the request type is performed on the message information, wherein the processing task at least includes an enqueue task for storing the message information in the ring FIFO queue, and a dequeue task for removing the message information from the ring FIFO queue; If not, the request execution result is fed back to the issuer of the request instruction based on the memory status of the current ring FIFO queue.
2. The CAN bus communication interruption receiving processing method based on the ring FIFO data structure according to claim 1 is characterized in that: The trigger conditions include at least: if the request type of the current request instruction is an enqueue request, then at the current moment, the circular FIFO queue does not include the message information in the current request instruction; if the request type of the current request instruction is a dequeue request, then at the current moment, the processing tasks being processed do not include a processing task whose request type and message information are consistent with the current request instruction.
3. The CAN bus communication interruption receiving processing method based on the ring FIFO data structure according to claim 1 is characterized in that: If the condition is satisfied, based on the message information contained in the request instruction and the circular FIFO queue, a processing task corresponding to the request type is performed on the message information, including: If the request type is an enqueue request and the trigger condition corresponding to the enqueue request is met, determine the cache bit set required to be occupied by the message information in the current request instruction, determine the queue segment corresponding to the cache bit set, and the processing cycle included in the message information; Based on the processing cycle and the preset correspondence table, the circle corresponding to the queue segment is determined, and according to the pointing order of the processing pointer corresponding to the circle, the queue segment is added to the corresponding circle; wherein the processing cycle refers to the time from the entry to the exit of the request information, and the corresponding relationship table is used to store several circles and the processing cycle range corresponding to each circle, all circles are rings with the same center and different radii, and the processing pointer configured corresponding to each circle is used to determine the order of entry and exit of the message information stored in the queue segment on the corresponding circle; all queue segments contained in all circles are combined to form a circular FIFO queue; If the request type is a dequeue request and the trigger condition corresponding to the dequeue request is met, the dequeue task of the request information will be executed based on the message information contained in the request instruction and the circle layer and according to the moving direction of the processing pointer of the corresponding circle layer.
4. The CAN bus communication interruption receiving processing method based on the ring FIFO data structure according to claim 3 is characterized in that: A buffer segment is reserved between any two adjacent queue segments belonging to the same circle; The method further comprises: Based on the processing cycle of the message information corresponding to each queue segment, determine the moving speed of the processing pointer of each circle when passing through the buffer segment, and adjust the moving speed and moving position of the corresponding processing pointer in real time according to the determined moving speed, so that when the processing pointer moves to any queue segment, it just reaches the processing cycle of the corresponding queue segment.
5. The CAN bus communication interruption receiving processing method based on the ring FIFO data structure according to claim 1 or 3, characterized in that: If the above conditions are not met, based on the memory status of the current ring FIFO queue, the request execution result is fed back to the issuer of the request instruction, including: If the request type of the request instruction is an enqueue request, and the annular FIFO queue does not meet the trigger condition corresponding to the enqueue request, an insertion bit is determined in the cache bit corresponding to the annular FIFO queue according to the message information in the request instruction, and an additional queue is inserted; According to the pointing position of the enqueue pointer of the circular FIFO queue, the priorities of the enqueue pointer of the circular FIFO queue and the enqueue pointer of the additional queue are adjusted so that the enqueue pointer with a higher priority replaces the enqueue pointer with a lower priority, so as to store the message information contained in the current request instruction into the additional queue; According to the pointing position of the dequeue pointer of the circular FIFO queue, the priorities of the dequeue pointer of the circular FIFO queue and the dequeue pointer of the additional queue are adjusted, and the dequeue pointer with a higher priority replaces the dequeue pointer with a lower priority, so that when the dequeue pointer of the circular FIFO queue points to the insertion position, the dequeue task of the message information in the additional queue is executed; When there is a message overflow in the message information in the request instruction, a request execution result with a request failure is fed back to the issuer of the request instruction; wherein, the message overflow means that the message information exceeds the message information cache capacity available for the additional queue and the circular FIFO queue.
6. The CAN bus communication interruption receiving processing method based on the ring FIFO data structure according to claim 5 is characterized in that: The step of determining an insertion position in a cache position corresponding to the annular FIFO queue and inserting an additional queue comprises: According to the pointing position of the queue entry pointer corresponding to the circular FIFO queue, the previous bit of the cache bit pointed to by the queue entry pointer of the circular FIFO queue at the current moment is used as the insertion bit; Based on the unqueued message information in the current request instruction, determine the additional bit set corresponding to the additional queue, the additional bit set includes the cache bits required to be occupied by the current request instruction in the preset additional queue, and establish a corresponding relationship between the insertion bit and the additional bit set; If the condition is not satisfied, the request execution result is fed back to the issuer of the request instruction based on the memory state of the current ring FIFO queue, and further includes: Whenever an insertion position is determined, and the corresponding relationship between the insertion position and the additional bit set is determined, the priority of the enqueue pointer of the additional queue is defined to be higher than the priority of the enqueue pointer of the circular FIFO queue, and the position pointed to by the enqueue pointer of the additional queue is adjusted to store the message information that has not been queued in the request instruction into the cache bit corresponding to the additional bit set corresponding to the current insertion position in the additional queue; until the message information corresponding to the cache bit corresponding to the additional bit set is completed to be queued, the priority of the enqueue pointer of the circular FIFO queue is defined to be higher than the priority of the enqueue pointer of the additional queue; When the dequeue pointer of the circular FIFO queue points to the cache bit after the target insertion bit in the circular FIFO queue, the dequeue pointer priority of the additional queue is limited to be higher than the dequeue pointer priority of the circular FIFO queue, and the position pointed to by the dequeue pointer of the additional queue is adjusted to dequeue the message information stored in the additional bit set corresponding to the target insertion bit in the additional queue, and then the dequeue pointer priority of the circular FIFO queue is readjusted to be higher than the priority of the dequeue pointer of the additional queue; wherein the target insertion bit refers to any insertion bit.
7. The CAN bus communication interruption receiving processing method based on the ring FIFO data structure according to claim 6 is characterized in that: The method of using, according to the pointing position of the enqueue pointer corresponding to the annular FIFO queue, the previous bit of the cache bit pointed to by the enqueue pointer of the annular FIFO queue at the current moment as the insertion bit, comprises: According to the pointing position of the enqueue pointer corresponding to the circular FIFO queue, the message information is stored in the circular FIFO queue until the enqueue is stopped when the circular FIFO queue is full, and the previous bit of the cache bit pointed to by the enqueue pointer of the circular FIFO queue when the enqueue is stopped is used as the insertion bit.
8. A CAN bus communication interrupt receiving and processing system based on a ring FIFO data structure, characterized in that: include: A request trigger determination module (1) is used to receive a request instruction and determine whether a preset annular FIFO queue satisfies a trigger condition corresponding to a request type contained in the request instruction; wherein the request type includes at least an enqueue request and a dequeue request, and the annular FIFO queue is used to cache message information; A request task processing module (2) is used to, if satisfied, execute a processing task corresponding to the request type on the message information based on the message information contained in the request instruction and the annular FIFO queue, wherein the processing task at least includes an enqueue task for storing the message information in the annular FIFO queue, and a dequeue task for removing the message information from the annular FIFO queue; The request result feedback module (3) is used to feedback the request execution result to the issuer of the request instruction based on the memory state of the current ring FIFO queue if the condition is not satisfied.
9. A CAN bus communication interrupt receiving and processing device based on a ring FIFO data structure, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute any one of the methods according to claims 1 to 7.
10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute any one of the methods as claimed in claims 1 to 7.