Dynamic circuit applicable to switch, switch and system

Abstract

The present invention discloses a dynamic circuit applicable to a switch, a switch and a system. The dynamic circuit includes selection circuits corresponding one by one to the transmission ports of the switch. The selection circuit is used to control the transmission port corresponding to it to be electrically connected to one of the other transmission ports. The selection circuit includes a first port and a plurality of second ports. The first port is used to be electrically connected to the transmission port corresponding to the selection circuit, and the plurality of second ports are electrically connected to the other transmission ports one by one. And one of the two ports of the first port and the second port is an input end, and the other port is an output port. The first port and the second port are electrically connected respectively to form a plurality of transmission lines. A plurality of controllable switches are arranged on each transmission line. The controllable switch is used to control that at most only one transmission line is conducting at the same time. The present invention can reduce the data transmission delay of the switch, improve the working efficiency and overall performance of the switch.

Description

Technical Field

[0001] The present invention relates to the technical field of computer network devices, and particularly to a dynamic circuit, a switch, and a system applicable to a switch. Background Art

[0002] With the development of artificial intelligence (AI) technology, the computing demand is increasing day by day, prompting switches to expand the number of GPUs to meet higher computing power requirements. For this reason, the number of ports on the switch is increasing continuously, thereby increasing the number of input lines of the high fan-in gate circuit between ports. However, in order to reduce power consumption and improve the transistor switching speed, modern manufacturing processes have continuously reduced the threshold voltage of transistors, resulting in a weakened driving ability of traditional high fan-in gate circuits, which are gradually replaced by circuits composed of multiple low fan-in gate circuits.

[0003] As Figure 1 shown, a high fan-in gate circuit is constructed by cascading multiple low fan-in gate circuits to adapt to the increasing port inputs. These low fan-in gate circuits operate synchronously through a clock signal to ensure the correct transmission of data between different ports. Although the low fan-in gate circuit has lower power consumption and a relatively simple circuit design, and also meets the expansion requirements of the switch to a certain extent, this cascaded circuit design needs to wait for the clock signal during data transmission, resulting in a large amount of delay accumulated in data transmission.

[0004] In summary, although the low fan-in gate circuit has the advantages of low power consumption and simple design, they need to wait for the clock signal to perform data transmission, which results in a large amount of delay accumulated during the data transmission between these gate circuits. This delay not only affects the transmission efficiency of the switch but also limits the improvement of the overall system performance.

[0005] The disclosure of the above background art content is only used to assist in understanding the inventive concept and technical solution of the present invention, and it does not necessarily belong to the prior art of this application, nor does it necessarily provide technical guidance; in the case where there is no clear evidence that the above content was publicly available before the filing date of this application, the above background art should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0006] The purpose of the present invention is to provide a dynamic circuit, a switch, and a system applicable to a switch, which can improve the data transmission delay problem of the switch, as well as improve the working efficiency and overall performance of the switch.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A dynamic circuit applicable to a switch, the dynamic circuit including a plurality of selection circuits, the selection circuits corresponding one-to-one to the transmission ports of the switch, and the selection circuits being configured to control the transmission port corresponding thereto to be electrically connected to one of the other transmission ports;

[0009] The selection circuit includes a first port and a plurality of second ports. Among them, the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, and the plurality of second ports are electrically connected to the other transmission ports one-to-one. It should be noted that "the plurality of second ports are electrically connected to the other transmission ports one-to-one" in the present invention includes two cases. One is that the plurality of second ports are directly electrically connected to the other transmission ports one-to-one, and the other case is that the plurality of second ports are directly electrically connected to the first ports corresponding to the other transmission ports one-to-one. And for the two ports of the first port and the second port, one of the ports is configured as an input end, and the other port is configured as an output port;

[0010] The first port is electrically connected to each of the second ports respectively to form a plurality of transmission lines, and a plurality of controllable switches are arranged on each transmission line. The controllable switches are configured to control that at most one of the transmission lines is conducting at the same time.

[0011] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the selection circuit further includes a plurality of control lines, and the plurality of controllable switches are distributed on the plurality of control lines. Each control line is configured to input a control signal to some of the plurality of controllable switches;

[0012] Define the combination of the control lines where the controllable switches are located on the electrical connection path between a second port and the first port as the control scheme of the corresponding transmission line, and the control schemes of different transmission lines do not repeat.

[0013] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the controllable switch is an NMOS switch tube, the number of transmission ports of the switch is N, and N is a natural number greater than 1. The number of control lines is not less than , where log is the logarithm operator, represents taking the ceiling of .

[0014] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the number of control lines is , and the number of NMOS switch tubes arranged on each transmission line is not less than .

[0015] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, the number of NMOS switching transistors provided on each of the control lines is not greater than .

[0016] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, the controllable switch is a CMOS switching transistor, the number of transmission ports of the switch is N, and N is a natural number greater than 1. Then the number of control lines is not less than , where log is the logarithm operator, denotes rounding up.

[0017] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, the number of control lines is , and the number of CMOS switching transistors provided on each of the transmission lines is not less than .

[0018] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, the number of CMOS switching transistors provided on each of the control lines is not greater than .

[0019] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, the dynamic circuit further includes a clock signal management circuit. The clock signal management circuit includes a first switching transistor, a second switching transistor, and a capacitor. The gate of the first switching transistor is configured as an input terminal of a clock signal, the source of the first switching transistor is configured to be electrically connected to an output terminal of a first power supply, and the drain of the first switching transistor is electrically connected to a first end of the capacitor;

[0020] The gate of the second switching transistor is configured as an input terminal of a clock signal, the source of the second switching transistor is configured to be grounded, and the drain of the second switching transistor is electrically connected to the first end of the capacitor;

[0021] The clock signal management circuit corresponds to the selection circuit one by one, and an output terminal of the selection circuit is electrically connected to the first end of the capacitor.

[0022] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, it further includes determining the clock signal when each of the selection circuits operates by the following method:

[0023] If the capacitor is in a non-charged state, the clock signal must be 0; otherwise, the clock signal is 1;

[0024] and / or,

[0025] It also includes determining the output signal when the selection circuit is operating in the following manner: monitoring the charge and discharge state of the capacitor when the clock signal is 0. If the capacitor is in a discharging state, the output signal of the selection circuit is 0; otherwise, the output signal of the selection circuit is 1.

[0026] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the first switching transistor is an NMOS switching transistor, and the second switching transistor is a PMOS switching transistor.

[0027] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, each of the selection circuits is arranged in layers on the same circuit unit. The number of transmission ports of the switch is N, and there are N layers of selection circuits correspondingly arranged on the circuit unit;

[0028] Data transmission occurs between the first port and the second port on the same layer of the selection circuit, and no data transmission occurs between the first port and the second port on different layers of the circuit.

[0029] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, a controllable switch is provided on each of the transmission lines, and each controllable switch is configured to be independently controlled.

[0030] According to another aspect of the present invention, the present invention provides a network-type selection circuit, including a first port and multiple second ports. For the two ports of the first port and the second port, one port is configured as an input end, and the other port is configured as an output port;

[0031] The first port is electrically connected to each of the second ports respectively to form multiple transmission lines. A number of controllable switches are provided on each of the transmission lines, and the controllable switches are configured to control that at most only one of the transmission lines is conducting at the same moment;

[0032] The selection circuit further includes multiple control lines, and the multiple controllable switches are distributed on the multiple control lines. Each control line is configured to input control signals to some of the controllable switches among the multiple controllable switches;

[0033] Define the combination of the control lines where the controllable switches are located on the electrical connection path between a second port and the first port as the control scheme corresponding to its corresponding transmission line, and the control schemes of different transmission lines do not repeat.

[0034] According to another aspect of the present invention, the present invention provides a switch, and the switch includes the dynamic circuit as described in any one of the foregoing technical solutions or a combination of multiple technical solutions.

[0035] According to another aspect of the present invention, the present invention provides a computer system, which includes a switch as described in any one of the above technical solutions or a combination of multiple technical solutions, and a device that needs to perform data transmission and is electrically connected to the transmission port of the switch.

[0036] The beneficial effects brought by the technical solutions provided by the present invention are as follows:

[0037] a. By simplifying the logic gates of the cascaded multiplexers and demultiplexers that are repeatedly applied in large quantities in the switch, the present invention constructs multiple straight-line transmission lines from the second port to the first port, and controls the matrix composed of multiple transmission lines provided with controllable switches to output data from different sources to the target end. This dynamic circuit can quickly receive the transmitted data within one clock cycle, avoiding the delay caused by waiting for the clock signal in the traditional multi-stage cascaded circuit, and the data from other transmission ports of the switch can smoothly pass through the selection circuit corresponding to other transmission ports and be transmitted to another transmission port of the switch, further improving the speed and efficiency of data transmission and reducing the complexity of the circuit.

[0038] b. The logic function circuits of each selection circuit in the present invention can work independently, reducing the dependence on multiple cascaded circuits, being able to reduce the expansion cost of the switch, and the first port in the selection circuit can be either an output port or an input port, facilitating bidirectional data transmission between two transmission ports in the switch. In addition, there are two transmission lines between two transmission ports in the switch, making it possible for the two transmission ports in the switch to transmit data bidirectionally simultaneously.

[0039] c. By designing a network-type selection circuit, the present invention can control data transmission between multiple transmission ports through fewer control lines, and for switches with a larger number of transmission ports, its advantages in reducing data transmission delay, simplifying circuit design, and improving the reliability of data transmission by the switch are greater. In addition, by applying NMOS switching tubes that can provide lower power consumption and faster switching speed in the selection circuit, the data transmission delay of the switch can be further reduced.

[0040] d. By providing a clock signal management circuit corresponding to the selection circuit, it is possible to know whether the clock signal outputs 0 or 1 and whether the output end of the selection circuit is a high-level signal or a low-level signal by detecting whether the capacitor in the clock signal management circuit discharges, and it is possible to record the clock signals corresponding to the data transmission of each port in the selection circuit and confirm the data transmission content. While reducing the data transmission delay between the switch ports, this technical solution can also improve the accuracy and reliability of data transmission. Description of the Drawings

[0041] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0042] Figure 1 Circuit diagram of cascading multiple low fan-in gate circuits in the prior art;

[0043] Figure 2 Schematic diagram of a dynamic circuit applicable to a switch provided by an exemplary embodiment of the present invention;

[0044] Figure 3 Schematic diagram of a nine-port selection circuit provided by an exemplary embodiment of the present invention;

[0045] Figure 4 Schematic diagram of a five-port selection circuit provided by an exemplary embodiment of the present invention;

[0046] Figure 5 Schematic diagram of a four-port selection circuit provided by an exemplary embodiment of the present invention;

[0047] Figure 6 Schematic diagram of a clock signal management circuit provided by an exemplary embodiment of the present invention. Detailed implementation manners

[0048] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0050] In an embodiment of the present invention, a dynamic circuit applicable to a switch is provided. Refer to Figures 1 to 5 , the dynamic circuit includes a plurality of selection circuits, the selection circuits correspond to the transmission ports of the switch one by one, and the selection circuits are configured to control the transmission port corresponding to it to be electrically connected to one of the other transmission ports.

[0051] Each selection circuit includes a first port and a plurality of second ports. Among them, the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, and the plurality of second ports are electrically connected to the other transmission ports one by one. And for the two ports of the first port and the second port, one port is configured as an input end and the other port is configured as an output end.

[0052] The first port is electrically connected to each of the second ports respectively to form a plurality of transmission lines. A plurality of controllable switches are arranged on each transmission line, and the controllable switches are configured to control that at most one of the transmission lines is conducting at the same time.

[0053] The multiplexer of the prior art uses a plurality of small units to form a large unit. As Figure 1 shown, a plurality of 2-port to 1-port multiplexers are used to form an 8-port to 1-port multiplexer. The current needs to pass through several small multiplexers, so a relatively long delay will be generated. The dynamic circuit applicable to a switch described in this embodiment, by a large number of repeated applications in the switch such as Figure 1The logic gates of the cascaded multiplexer and demultiplexer shown are simplified. By constructing multiple straight transmission lines from the second port to the first port, and controlling the controllable switch matrices distributed on each transmission line, data from different sources can be output to the target end. Thus, the dynamic circuit designed in this application can quickly receive the transmitted data within one clock cycle, avoiding the delay caused by waiting for the clock signal in traditional multi-cascaded circuits. Moreover, data from other transmission ports of the switch can smoothly pass through the selection circuits corresponding to the other transmission ports and be transmitted to another transmission port of the switch, further improving the speed and efficiency of data transmission.

[0054] The dynamic circuit not only reduces the delay in the data transmission path within the switch and improves the data transmission efficiency, but also enables each logic function circuit to work independently, reducing the dependence on multiple cascaded circuits, thereby reducing the circuit complexity. When the switch needs to expand the interface, a corresponding selection circuit can be configured for the expanded port and the first port and the second port in the selection circuit can be correspondingly connected to the transmission ports of the switch, which can reduce the expansion cost of the switch. In addition, in this technical solution, as Figure 2 shown, the first port in each selection circuit can be either an output port or an input port, which can facilitate the bidirectional data transmission between two transmission ports in the switch. And there are two transmission lines between two transmission ports in the switch, making it possible for the two transmission ports in the switch to transmit data bidirectionally simultaneously.

[0055] In an embodiment of the present invention, the selection circuit is a network structure, and it further includes multiple control lines. The multiple controllable switches are distributed on the multiple control lines, and each control line accesses a clock signal and is configured to input a control signal to some of the controllable switches among the multiple controllable switches. Define the combination of the control lines where the controllable switches are located on the electrical connection path between the second port and the first port as the control scheme of its corresponding transmission line, and the control schemes of different transmission lines do not repeat. Taking MOS switch tubes as an example, the clock signal accessed by each control line is simultaneously input to the gates of the MOS switch tubes located on this control line, and then all the MOS switch tubes on this control line are turned on or off simultaneously.

[0056] It should be noted that to control the on-off states of all the controllable switches through several control lines, one control line is used to control the on-off states of several controllable switches on different transmission lines, that is, one control line does not control the on-off states of two controllable switches arranged on the same transmission line.

[0057] In this embodiment, the dynamic circuit further includes a clock signal management circuit, see Figure 6, the clock signal management circuit includes a first switching transistor, a second switching transistor, and a capacitor. Wherein, the gate of the first switching transistor is configured as the input terminal of the clock signal, the source of the first switching transistor is configured to be electrically connected to the output terminal of the first power supply, and the drain of the first switching transistor is electrically connected to the first end of the capacitor. The other end of the capacitor can be grounded or connected to other discharge circuits. The gate of the second switching transistor is configured as the input terminal of the clock signal, the source of the second switching transistor is configured to be grounded, and the drain of the second switching transistor is electrically connected to the first end of the capacitor. The clock signal management circuit corresponds to the selection circuit one by one, and the output terminal of the selection circuit is electrically connected to the first end of the capacitor.

[0058] See Figure 6 , preferably, the first switching transistor is an NMOS switching transistor, and the second switching transistor is a PMOS switching transistor. When the clock signal is 1, the first switching transistor is turned on and the first switching transistor is not turned on, and the capacitor is in a charging state; when the clock signal is 0, the first switching transistor is not turned on and the first switching transistor is turned on. If the signal at the output terminal of the selection circuit is 1, then the capacitor is in a charging state or neither charging nor discharging. If the signal at the output terminal of the selection circuit is 0, the capacitor is in a discharging state. Thus, by monitoring the charge and discharge state of the capacitor when the clock signal is 0, it can be determined whether the signal transmitted from the input terminal to the output terminal of the selection circuit is 0 or 1. Thus, the data transmitted by the selection circuit can be accurately determined. Therefore, while reducing the data transmission latency between switch ports, the technical solution can also improve the accuracy and reliability of data transmission.

[0059] In order to minimize the area of the selection circuit, the number of controllable switches, and the number of control lines, in an embodiment of the present invention, the controllable switch is a CMOS switching transistor, and the number of transmission ports of the switch is N, where N is a natural number greater than 1. Then the number of control lines is not less than , where log is the logarithm operator, represents rounding up.

[0060] More preferably, the number of control lines is , and the number of CMOS switching transistors provided on each transmission line is not less than . The number of CMOS switching transistors provided on each control line is not greater than .

[0061] In another embodiment of the present invention, different from the CMOS switch tube used for the controllable switch in the above embodiment, in this embodiment, the controllable switch uses an NMOS switch tube. The number of transmission ports of the switch is N, where N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithm operator, denotes rounding up

[0062] More preferably, the number of control lines is , and the number of NMOS switch tubes provided on each transmission line is not less than . The number of NMOS switch tubes provided on each control line is not greater than .

[0063] In this embodiment, the complementary metal oxide semiconductor (CMOS) switch tube is replaced with an N-type metal oxide semiconductor (NMOS) switch tube. Since NMOS can provide lower power consumption and faster switching speed under specific conditions, this is crucial for reducing data transmission delay. Through this replacement, the present solution can further reduce the delay of data during circuit transmission while ensuring the accuracy of data transmission.

[0064] In an embodiment of the present invention, in order to reduce the area of the dynamic circuit and the delay of data transmission, for a switch with N transmission ports, N selection circuits are correspondingly provided, and the N selection circuits are hierarchically arranged on the same circuit unit. Data is transmitted between the first port and the second port on the same layer of the selection circuit, and data is not transmitted between the first port and the second port on different layer circuits. The hierarchical arrangement scheme of the N selection circuits can be designed with reference to the technical solution disclosed in the Chinese patent application with the application number 2024114493648. The following uses multiple specific embodiments to illustrate the dynamic circuit applicable to the switch provided in the present application.

[0065] Taking a nine-port switch as an example, to control one of the devices connected to eight transmission ports of the switch to transmit data to the device connected to the ninth transmission port of the switch, if the prior art is used, at least a three-stage cascaded multiplexer as shown in Figure 1 is required. The larger the multiplexer constructed by using multiple small multiplexers, the higher the delay of its data transmission, and there is also a problem of insufficient voltage caused by gate circuits such as AND gates and OR gates.

[0066] Adopting the technical solution proposed by the present invention, a network-type selection circuit as shown in Figure 3 is constructed. Figure 3The first ports a to h therein respectively represent eight different input terminals, and the second port O / P represents an output terminal. The ports a to h are respectively electrically connected to the port O / P to form 8 (9 - 1 = 8) transmission lines, and a number of series-connected NMOS switching transistors are provided on each transmission line. Controlling the 8 transmission lines requires 6 control lines to achieve (if CMOS switches are used for the controllable switches, 3 control lines are required). The number of NMOS switching transistors on each transmission line is 3, and the number of NMOS switching transistors on each control line is 4. As described above, defining the combination of the control lines where the NMOS switching transistors on a transmission line are located as the control scheme corresponding to the transmission line, and the control schemes of different transmission lines do not repeat, thus obtaining Figure 3 the selection circuit shown.

[0067] Figure 3 In it, s0, s1, and s2 are three control lines with the same high and low output levels of the output voltage, , , are three control lines with the same high and low output levels of the output voltage, and if one of the s0 control line and the control line outputs a high level, then the other outputs a low level; if one of the s1 control line and the control line outputs a high level, then the other outputs a low level; if one of the s2 control line and the control line outputs a high level, then the other outputs a low level. The gates of the NMOS switching transistors are electrically connected to the output terminals of their corresponding control lines. When the output of the control line on the NMOS switching transistor is at a high level, the NMOS will conduct. For example, when the s0, s1, and s2 control lines output high levels, only the h input terminal is conducted to the O / P output terminal. At this time, the device connected to the h input terminal transmits data to the device connected to the O / P output terminal. If it is necessary to achieve the transmission of data from the device connected to the a input terminal to the device connected to the O / P output terminal, then control , , the three control lines respectively output high levels.

[0068] Adopting the selection circuit provided by this application, only 6 control lines (at least 3) are required to control the alternative transmission of 8 transmission lines, and the data transmission can be completed within one clock cycle, effectively reducing the data delay, and there will be no conflict situation where two transmission lines transmit data simultaneously.

[0069] Taking a five-port switch as an example, if NMOS switching transistors are used for the controllable switches, the selection circuit corresponding to each transmission port in the switch is as Figure 4 shown.

[0070] Taking a four-port switch as an example, the connection mode of the dynamic circuit and the four transmission ports of the switch is as Figure 2 shown. The four-port switch includes transmission ports one to four, and is correspondingly configured with a first selection circuit to a fourth selection circuit. Each selection circuit has a first port and three second ports. Taking the first selection circuit as an example, it includes a first port I1 and three second ports O12, O13, and O14. Among them, the first port I1 is electrically connected to the first transmission port of the switch, and the second port O12 is electrically connected to the second transmission port of the switch or the first port of the second selection circuit. The second port O13 is electrically connected to the third transmission port of the switch or the first port of the third selection circuit. The second port O14 is electrically connected to the fourth transmission port of the switch or the first port of the fourth selection circuit. If the controllable switch in the first selection circuit uses an NMOS switch tube, the structure of the first selection circuit is as Figure 5 shown. The circuit principles of the second selection circuit to the fourth selection circuit are the same as that of the first selection circuit, and will not be elaborated here.

[0071] It should be noted that for the dynamic circuit applicable to the switch and the above-mentioned network-type selection circuit provided by the present invention, the more transmission ports the switch has, the greater its advantages in reducing data transmission delay, simplifying circuit design, and improving the reliability of data transmission by the switch. For switches with fewer transmission ports, a controllable switch can be directly provided on each of the transmission lines, and each controllable switch is configured to be independently controlled. This method can save costs while reducing latency.

[0072] In an embodiment of the present invention, a network-type selection circuit is provided, which includes a first port and multiple second ports. For the two ports of the first port and the second port, one port is configured as an input end, and the other port is configured as an output port. The first port is electrically connected to each of the second ports respectively to form multiple transmission lines, and a plurality of controllable switches are provided on each of the transmission lines. The controllable switches are configured to control that at most only one of the transmission lines is conducting at the same time.

[0073] The selection circuit further includes multiple control lines, and the plurality of controllable switches are distributed on the multiple control lines. Each control line is configured to input control signals to some of the controllable switches among the plurality of controllable switches. Define the combination of the control lines where the controllable switches are located on the electrical connection path between a second port and the first port as the control scheme of its corresponding transmission line, and the control schemes of different transmission lines do not repeat.

[0074] It should be noted that the network-type selection circuit can be applied not only to switches, but also to other applications for electrical connection control or data transmission control from one end to multiple ends or from multiple ends to one end.

[0075] In an embodiment of the present invention, a switch is provided. The switch includes the dynamic circuit described in any one of the above embodiments or a combination of multiple embodiments.

[0076] In an embodiment of the present invention, a computer system is provided. The computer system includes the switch described in the above embodiment and multiple devices that need to perform data transmission. The devices are correspondingly connected to the transmission ports of the switch.

[0077] It should be noted that the embodiments of the network-type selection circuit, the switch, and the computer system provided by the present invention have the same inventive concept as the embodiment of the dynamic circuit applicable to switches. By way of introduction, all the content of the embodiment of the dynamic circuit applicable to switches is incorporated into the embodiments of the network-type selection circuit, the switch, and the computer system.

[0078] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0079] The above are only the specific embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A dynamic circuit suitable for a switch, characterized in that: The dynamic circuit includes a plurality of selection circuits, each of which corresponds to a transmission port of the switch, and each of which is configured to control the transmission port corresponding to the selection circuit to be electrically connected to one of the other transmission ports; The selection circuit includes a first port and a plurality of second ports, wherein the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, the plurality of second ports are electrically connected to other transmission ports in a one-to-one correspondence, and one of the first port and the second port is configured as an input port, and the other port is configured as an output port; The first port is electrically connected to each of the second ports to form a plurality of transmission lines, and a plurality of controllable switches are arranged on each of the transmission lines, and the controllable switches are configured to control at most one of the transmission lines to be turned on at the same time; The dynamic circuit further includes a clock signal management circuit, the clock signal management circuit includes a first switch tube, a second switch tube and a capacitor, the gate of the first switch tube is configured as an input end of the clock signal, the source of the first switch tube is configured to be electrically connected to the output end of the first power supply, and the drain of the first switch tube is electrically connected to the first end of the capacitor; The gate of the second switch tube is configured as an input end of a clock signal, the source of the second switch tube is configured to be grounded, and the drain of the second switch tube is electrically connected to the first end of the capacitor; The clock signal management circuit corresponds to the selection circuit one by one, and the output end of the selection circuit is electrically connected to the first end of the capacitor.

2. The dynamic circuit applicable to a switch according to claim 1, characterized in that: The selection circuit further comprises a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches; A combination of control lines where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme of the corresponding transmission line, and control schemes of different transmission lines are not repeated.

3. The dynamic circuit applicable to a switch according to claim 2, characterized in that: The controllable switch is an NMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithmic operator, Express Round up.

4. The dynamic circuit applicable to a switch according to claim 3, characterized in that: The number of control lines is The number of NMOS switches provided on each transmission line is not less than .

5. The dynamic circuit applicable to a switch according to claim 4, characterized in that: The number of NMOS switches provided on each control line is not greater than .

6. The dynamic circuit applicable to a switch according to claim 2, characterized in that: The controllable switch is a CMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than , where log is the logarithmic operator, Express Round up.

7. The dynamic circuit applicable to a switch according to claim 6, characterized in that: The number of control lines is The number of CMOS switches provided on each transmission line is not less than .

8. The dynamic circuit applicable to a switch according to claim 7, characterized in that: The number of CMOS switches provided on each control line is not greater than .

9. The dynamic circuit applicable to a switch according to claim 1, characterized in that: The method further includes determining the clock signal of each selection circuit when the selection circuit is working in the following manner: if the capacitor is in a non-charging state, the clock signal is 0; otherwise, the clock signal is 1; and / or, It also includes determining the output signal of the selection circuit when it is working in the following manner: when the clock signal is monitored to be 0, the capacitor is in a charging and discharging state; if the capacitor is in a discharging state, the output signal of the selection circuit is 0; otherwise, the output signal of the selection circuit is 1.

10. The dynamic circuit applicable to a switch according to claim 8, characterized in that: The first switch tube is an NMOS switch tube, and the second switch tube is a PMOS switch tube.

11. The dynamic circuit applicable to a switch according to claim 1, characterized in that: Each of the selection circuits is hierarchically arranged on the same circuit unit, the number of the transmission ports of the switch is N, and the circuit unit is correspondingly provided with N layers of selection circuits; Data is transmitted between the first port and the second port on the selection circuit of the same layer, and data is not transmitted between the first port and the second port on circuits of different layers.

12. The dynamic circuit applicable to a switch according to claim 1, characterized in that: One controllable switch is provided on each of the transmission lines, and each of the controllable switches is configured to be independently controlled.

13. A switch, characterized in that: The switch comprises a dynamic circuit as claimed in any one of claims 1 to 12.

14. A computer system, characterized in that: The computer system comprises the switch as claimed in claim 13 and a device requiring data transmission which is electrically connected to a transmission port of the switch.

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