Substrate structure and communication equipment

Abstract

The present disclosure provides a substrate structure and communication equipment. The substrate structure includes: at least one signal layer, wherein the wiring density of the first area in the substrate structure is higher than that of the second area; a differential signal line is arranged in the signal layer, the line width of the differential signal line in the first area is different from the line width of the differential signal line in the second area, and the impedance formed by the differential signal line in the first area and the impedance formed by the differential signal line in the second area are within the same impedance range. The present disclosure can reduce the skin loss of the differential signal line in the local low-density area and improve the quality of the eye diagram of the differential signal line by setting the differential signal lines in different wiring density areas in the same layer and the same network to different line widths.

Description

Technical Field

[0001] The present disclosure relates to the technical field of circuit boards, and in particular to a substrate structure and communication equipment. Background Art

[0002] As the operating frequency of electronic products, communication equipment, industrial equipment and medical equipment continues to increase, the signal transmission rate in PCB (Printed Circuit Board) is also increasing. The signal insertion loss in differential routing or MIPI (Mobile industry Processor Interface) routing has become a design bottleneck in high-density PCB boards. For example, the operating frequency of the 5G band of Wifi6 routers reaches 1000Mbps, the effective bandwidth of the professional network of Wifi7 routers reaches 320MHz, the maximum physical layer rate of the system reaches 33Gbps, and the point-to-point connection rate exceeds 10Gbps. The PCI-E 4.0 standard is mainly used in occasions with high data bandwidth requirements. The speed of each data channel has been increased from 8Gbps in 3.0 to 16Gbps. Graphics cards usually use x16 channels. Graphics cards with the PCI-E 4.0 standard will have a data throughput of 64GB / s. There are 4 pairs of differential signal lines in the 100G switch motherboard, and the rate of each pair of differential signal lines is up to 25Gb / s.

[0003] The higher the signal transmission rate, the more obvious the skin effect on the PCB board, and the greater the loss caused by the skin effect. In the design process of the PCB board, it is often encountered that the local density of the PCB board is high. For example, the CPU or DSP uses a high-density BGA packaging area, while the density of other areas of the PCB board is relatively low. However, in order to meet the requirement that the impedance of the differential signal lines of the same layer and the same network is basically the same, the line width and line spacing of the differential signal line will be set according to the position with higher local density of the PCB board to achieve the purpose of consistent impedance. This will cause the line width of the differential signal line of the same layer and the same network to be very narrow. The narrower the line width of the differential signal line, the greater the skin loss on the differential signal line. When the transmission rate of the differential signal line is high and the transmission distance is long, if the line width of the differential signal line is narrow, for example, the line width is less than 3.5mil, it will cause the signal attenuation of the entire link to be too large, and the eye opening of the receiving end will be too small, so that the signal cannot be received correctly. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the above-mentioned defects in the prior art and to provide a substrate structure and a communication device.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] A first aspect of the present disclosure provides a substrate structure, comprising: at least one signal layer, wherein the wiring density of a first area in the substrate structure is higher than the wiring density of a second area; a differential signal line is arranged in the signal layer, the line width of the differential signal line located in the first area is different from the line width of the differential signal line located in the second area, and the impedance formed by the differential signal line in the first area and the impedance formed by the differential signal line in the second area are within the same impedance range.

[0007] Optionally, the substrate structure further includes at least one ground layer, and the ground layer is stacked between the signal layer.

[0008] Optionally, none of the adjacent layers to the layer where the differential signal line in the first region is located is a ground layer, and at least one adjacent layer to the layer where the differential signal line in the second region is located is a ground layer.

[0009] Optionally, a line spacing of the differential signal lines located in the first area is different from a line spacing of the differential signal lines located in the second area.

[0010] Optionally, the line width of the differential signal line in the first area is smaller than the line width of the differential signal line in the second area, and the line spacing of the differential signal line in the first area is smaller than the line spacing of the differential signal line in the second area.

[0011] Optionally, a line spacing of the differential signal lines located in the first region is less than or equal to 2.2 times a line width of the differential signal lines located in the first region.

[0012] Optionally, a line spacing of the differential signal lines located in the second region is less than or equal to 2.2 times of a line width of the differential signal lines located in the second region.

[0013] Optionally, a line spacing of the differential signal lines located in the first area is the same as a line spacing of the differential signal lines located in the second area.

[0014] Optionally, a first grounding circuit is provided in the signal layer where the differential signal circuit is located;

[0015] The differential signal lines in the first area and the differential signal lines in the second area are surrounded by the first ground line;

[0016] Alternatively, the differential signal circuit in the first area is surrounded by a first ground circuit, and the differential signal circuit in the second area is not surrounded by the first ground circuit;

[0017] Alternatively, the differential signal lines in the first region are not surrounded by the first ground line, and the differential signal lines in the second region are surrounded by the first ground line.

[0018] Optionally, a first signal circuit is provided in the signal layer where the differential signal circuit is located; and the first ground circuit is provided between the first signal circuit and the differential signal circuit.

[0019] Optionally, a first power supply circuit is provided in the signal layer where the differential signal circuit is located; and the first ground circuit is provided between the first power supply circuit and the differential signal circuit.

[0020] Optionally, a ground via is provided in the first grounding circuit;

[0021] The first grounding circuit is arranged on the top layer and / or the bottom layer of the substrate structure, and the ground via passes through the first grounding circuit and the first reference plane in a direction perpendicular to the substrate structure; the ground via is electrically connected to the first grounding circuit and the first reference plane respectively;

[0022] Alternatively, the first grounding circuit is arranged in the middle layer of the substrate structure, and the ground via passes through the first grounding circuit, the first reference plane and the second reference plane in a direction perpendicular to the substrate structure; the ground via is electrically connected to the first grounding circuit, the first reference plane and the second reference plane respectively.

[0023] Optionally, the first area is located on a surface layer of the substrate, the differential signal circuit located in the first area is provided with ink, and the differential signal circuit located in the second area is not provided with ink.

[0024] Optionally, an impedance formed between the differential signal line and the first reference plane in the first region and an impedance formed between the differential signal line and the first reference plane in the second region are within the same impedance range.

[0025] Optionally, the differential signal line is arranged on a top layer of the substrate structure, and the first reference plane is a ground layer adjacent to the top layer.

[0026] Optionally, the differential signal line is arranged on a bottom layer of the substrate structure, and the first reference plane is a ground layer adjacent to the bottom layer.

[0027] Optionally, the differential signal line is arranged in a middle layer of the substrate structure, and the first reference plane includes a proximal ground layer and a distal ground layer adjacent to the middle layer.

[0028] Optionally, an impedance formed between the differential signal line and the first reference plane in the first region and an impedance formed between the differential signal line and the second reference plane in the second region are within the same impedance range.

[0029] Optionally, the differential signal line is arranged on the top layer of the substrate structure, the first reference plane is a ground layer adjacent to the top layer, the projection area of ​​the differential signal line on the adjacent ground layer in the second area is hollowed out, the second reference plane is the ground plane of the target layer, the target layer is an internal signal layer adjacent to the ground layer, and the ground plane of the target layer is obtained by copper foil cladding the projection area of ​​the differential signal line on the target layer.

[0030] Optionally, the differential signal line is arranged on the bottom layer of the substrate structure, the first reference plane is a ground layer adjacent to the bottom layer, the projection area of ​​the differential signal line on the adjacent ground layer in the second region is hollowed out, the second reference plane is the ground plane of the target layer, the target layer is an internal signal layer adjacent to the ground layer, and the ground plane of the target layer is obtained by copper foil cladding the projection area of ​​the differential signal line on the target layer.

[0031] Optionally, the differential signal line is arranged in the middle layer of the substrate structure, the first reference plane includes a proximal ground layer and a distal ground layer adjacent to the middle layer, the projection area of ​​the differential signal line on the proximal ground layer in the second area is hollowed out, the second reference plane includes a reference ground layer and a distal ground layer adjacent to the middle layer, and the reference ground layer is a ground layer adjacent to the proximal ground layer.

[0032] Optionally, the line width of the differential signal line located in the first area and the line width of the differential signal line located in the second area transition in a gradual manner.

[0033] Optionally, the line width of the differential signal line located in the first area and the line width of the differential signal line located in the second area transition in an abrupt manner.

[0034] A second aspect of the present disclosure provides a communication device, comprising the substrate structure as described in the first aspect.

[0035] Based on the common sense in the art, the above optional conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0036] The positive progressive effect of the present disclosure is that by setting the differential signal lines in different wiring density areas in the same layer and the same network to different line widths, the skin loss of the differential signal lines in the local low density areas can be reduced, and the quality of the eye diagram of the differential signal lines can be improved.

[0037] In order to meet the impedance consistency of differential signal lines with different line widths, the line spacing of differential signal lines in different wiring density areas can be adjusted. Ink can be set on the differential signal lines in areas with higher local density and no ink can be set on the differential signal lines in areas with lower local density. The distance between the surrounding ground lines and the differential signal lines can be adjusted. The dielectric constant can also be changed by changing some materials in the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a cross-sectional view of a differential signal line in the X region of the substrate provided in Embodiment 1 of the present disclosure.

[0039] Figure 2 This is a cross-sectional view of the differential signal line of the substrate in the Z region provided in Example 1 of the present disclosure.

[0040] Figure 3 A schematic diagram of two different line widths of differential signal lines of the same layer and the same network provided in Example 1 of the present disclosure.

[0041] Figure 4 Another schematic diagram of two different line widths of differential signal lines of the same layer and the same network provided in Example 1 of the present disclosure.

[0042] Figure 5 A top view of a ground wire provided in Example 1 of the present disclosure.

[0043] Figure 6 A top view of a ground copper foil provided in Example 1 of the present disclosure.

[0044] Figure 7 A top view of another ground copper foil provided in Example 1 of the present disclosure.

[0045] Figure 8 A top view of a microstrip differential signal line on the bottom layer of a substrate provided in Example 1 of the present disclosure.

[0046] Fig. 9 A top view of a microstrip differential signal line on the bottom layer of another substrate provided in Embodiment 1 of the present disclosure.

[0047] Fig.10 Embodiment 1 of the present disclosure provides a cross-sectional view of a characteristic differential signal line on the top layer or bottom layer of a substrate.

[0048] Fig.11 A cross-sectional view of a vertical section of a characteristic differential signal line on the top layer or bottom layer of a substrate provided in Embodiment 1 of the present disclosure.

[0049] Fig.12 A schematic diagram of an interface of an impedance calculation tool provided in Example 1 of the present disclosure.

[0050] Fig.13 Another schematic diagram of the interface of the impedance calculation tool provided in Example 1 of the present disclosure.

[0051] Fig.14 Another cross-sectional view of a vertical section of a characteristic differential signal line on the top or bottom layer of a substrate provided in Embodiment 1 of the present disclosure.

[0052] Fig.15 A cross-sectional view of a differential signal line on a top layer or a bottom layer in a direction vertical to a substrate provided in Embodiment 1 of the present disclosure.

[0053] Fig.16 A cross-sectional view of another top or bottom layer of differential signal lines in a direction vertical to the substrate provided in Embodiment 1 of the present disclosure.

[0054] Fig.17 A cross-sectional view of another top layer or bottom layer differential signal line in a direction vertical to the substrate provided in Embodiment 1 of the present disclosure.

[0055] Fig.18 This is the SATA_TX0 eye diagram of the SATA hard disk provided in Example 1 of the present disclosure.

[0056] Fig.19 This is a graph of the SATA_TX0 test results of the SATA hard disk provided in Example 1 of the present disclosure. DETAILED DESCRIPTION

[0057] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0058] The substrate structure provided in the embodiments of the present disclosure is suitable for driving recorders, Wifi5 / Wifi6 / Wifi7 routers, mobile phones, VR / AR products, tablets, notebooks, industrial computers, medical equipment, servers, 100G switches, wireless base station motherboards and other fields.

[0059] The following is an explanation of the terms in the embodiments of the present disclosure:

[0060] Low-speed signals refer to signals transmitted on low-speed signal lines, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral interface), 1-Wire Bus, GPIO (General Purpose Input Output), SMBus (System Management Bus), CAN (Controller Area Network), LIN (Local Interconnect Network), ARINC429, Fieldbus, etc., which are insensitive to surrounding noise and have low self-interference.

[0061] Differential signaling, also known as differential mode signaling, is a signal transmission technology. Different from the traditional method of one signal line and one ground line, differential transmission transmits signals on both lines. The amplitudes of the two signals are equal and the phases are opposite. The signal transmitted on these two lines is a differential signal.

[0062] The MIPI protocol is proposed to solve the contradiction between the growing high-bandwidth requirements of high-definition image (video) transmission and the low rate of traditional interfaces, and to provide a unified standard for the entire industry, thereby shortening the product development cycle and enhancing the compatibility of products between different manufacturers. That is, the MIP protocol is an open standard and a specification initiated by the MIPI Alliance for mobile application processors. MIPI has two main applications, CSI (Camera Serial Interface) and DSI (Display Serial Interface). MIPI routing is a differential routing set for transmitting high-definition image (video) signals.

[0063] In this embodiment, the substrate includes a printed circuit board, a SIP, an integrated circuit board, etc. Among them, SIP (System In a Package) is a packaging concept, which is a packaging method in which all or most of the electronic functions of a system or subsystem are configured in an integrated substrate, and the chip is connected to the integrated substrate in a 2D or 3D manner. SIP can not only assemble multiple chips, but also act as a dedicated processor, DRAM, flash memory and passive components combined with resistors and capacitors, connectors, antennas, etc., all installed on the same substrate. A complete functional unit can be built in a multi-chip package, so a small number of external components need to be added to make it work. The integrated substrate connects the chip's wafer to a high-density substrate through gold wires, such as WLCSP (Wafer Level Chip Scale Package), which is a packaging technology that combines wafer-level packaging (WLP) and chip-size packaging (CSP) into one.

[0064] Printed circuit board, also known as printed circuit board, can also be called PCB board, is an important electronic component, a support for electronic components, and a provider of circuit connections for electronic components.

[0065] The main factors that affect the impedance of the differential signal line are: the line width of the differential signal line, the line spacing, the distance from the differential signal line to the reference plane, the dielectric constant of the PCB board, the thickness of the copper foil of the differential signal line, etc. In order to meet the impedance consistency of the differential signal lines with different line widths, the line spacing of the differential signal lines in different wiring density areas can be adjusted, and ink can be set on the differential signal lines in the local high density area and no ink can be set on the differential signal lines in the local low density area. The distance between the surrounding ground line and the differential signal line can also be adjusted, and the dielectric constant can also be changed by changing some materials in the substrate.

[0066] Example 1

[0067] This embodiment provides a substrate structure, including: at least one signal layer, wherein the wiring density of a first area in the substrate structure is higher than the wiring density of a second area.

[0068] A differential signal line is provided in the signal layer, the line width of the differential signal line in the first area is different from the line width of the differential signal line in the second area, and the impedance formed by the differential signal line in the first area and the impedance formed by the differential signal line in the second area are within the same impedance range.

[0069] It should be noted that the impedance formed by the differential signal line in the first region and the impedance formed by the differential signal line in the second region are within the same impedance range. Ideally, the impedance formed by the differential signal line in the first region and the impedance formed by the differential signal line in the second region are exactly the same. However, in actual applications, due to the superposition of various factors, the impedances of differential signal lines with different line widths may not be exactly the same, and there may be a certain error. The above impedance range can be set according to actual conditions, for example, it can be {0.9Rm, 1.1Rm}, where Rm is the target impedance.

[0070] In an optional embodiment, the substrate structure further includes at least one ground layer, and the ground layer is stacked with the signal layer. It should be noted that in other embodiments, the substrate structure may not include a ground layer.

[0071] In an optional implementation, none of the adjacent layers to the layer where the differential signal line in the first region is located is a ground layer, and at least one adjacent layer to the layer where the differential signal line in the second region is located is a ground layer.

[0072] Among them, differential signal lines are divided into microstrip differential signal lines and strip differential signal lines. Figure 1 is a cross-sectional view of the differential signal line of the substrate in the X region, Figure 2 : is a cross-sectional view of the differential signal line of the substrate in the Z region. The X region is a high-density region of the substrate wiring, corresponding to the first region; the Z region is a low-density region of the substrate wiring, corresponding to the second region.

[0073] The strip differential signal line refers to the strip differential signal line set in the inner layer of the substrate, that is, buried inside the substrate, such as Figure 1As shown, the differential signal line 2 and the differential signal line 3 are both strip differential signal lines arranged in the inner layer of the substrate. Taking the differential signal line 2 in the LY03 layer as an example, the differential signal line 2 is composed of two parallel and symmetrical conductors A1 and A2, and the same layer around the two parallel and symmetrical conductors A1 and A2 is composed of insulating medium. The adjacent layers of the differential signal line 2 in the LY03 layer are the GND02 layer and the GND05 layer. The projection position of the differential signal line 2 in the LY03 layer on the GND02 layer is the ground metal plane G2. The differential signal line 2 in the LY03 layer and the ground metal plane G2 in the projection position of the differential signal line 2 in the LY03 layer are filled with insulating medium; the differential signal line in the LY03 layer The projection position of the differential signal line 2 in the GND05 layer is the ground metal plane G5, the projection position of the differential signal line 2 in the LY03 layer is hollowed out in the projection position of the LY04 layer, and the differential signal line 2 in the LY03 layer is filled with an insulating medium between the ground metal plane G5 in the projection position of the GND05 layer; since the two parallel and symmetrical conductors A1 and A2 in the LY03 layer are embedded between the two layers of planar conductors of the TOP layer ground metal plane G2 and the GND05 layer ground metal plane G5, the electric field distribution of the differential signal line 2 in the LY03 layer is between the two conductors A1 and A2 that surround it, and it will not radiate energy and will not be interfered by external radiation. However, since the differential signal line 2 in the LY03 layer is surrounded by dielectrics (dielectric constant is greater than 1), the transmission speed of the differential signal line 2 in the LY03 layer (i.e., the strip differential signal line) in the inner layer is slower than that in the surface layer (such as the TOP layer and the BOTTOM layer).

[0074] Microstrip differential signal lines refer to those arranged on the surface of the substrate (such as the TOP layer or the BOTTOM layer), that is, microstrip differential signal lines arranged on the surface of the substrate, such as Figure 1As shown, differential signal line 1 and differential signal line 4 are both microstrip differential signal lines arranged in the BOTTOM layer of the substrate. Taking the differential signal line 1 in the BOTTOM layer as an example, the differential signal line 1 is composed of two parallel and symmetrical conductors B1 and B2. The two parallel and symmetrical conductors B1 and B2 are filled with insulating medium between the inner layer GND09. The same layer around and bottom of the two parallel and symmetrical conductors B1 and B2 are composed of air, and the dielectric of air (dielectric constant is 1), so the differential signal line 1 in the BOTTOM layer (i.e., microstrip differential signal line) has a faster transmission speed in the surface layer than the inner layer strip differential signal line (e.g., differential signal line 2 in the LY03 layer). The two parallel and symmetrical conductors B1 and B2 are filled with insulating medium between the inner layer GND09. The surrounding and bottom layers of the same layer of the two parallel and symmetrical conductors B1 and B2 are all composed of air. The electromagnetic field generated by the two parallel and symmetrical conductors B1 and B2 has the opportunity to radiate, which may cause EMC problems such as EMI radiation exceeding the standard, and may also interfere with circulating sensitive signals (such as RF routing). At the same time, the differential signal line 1 is also easily affected by strong external interference, such as interference generated by radiation from surrounding high-power switching power supplies.

[0075] There is currently only one useful and reasonable approximation method for calculating the differential impedance of edge-coupled microstrip lines or strip lines. This approximation method is an empirical formula based on a large amount of experimental data. The following is an approximate calculation formula for the impedance of differential signal lines.

[0076] The calculation formula for the differential impedance of a microstrip differential signal line is:

[0077]

[0078] The calculation formula for the differential impedance of the strip differential signal line is:

[0079]

[0080] Among them, Z0 is the single-ended impedance value, S represents the edge-to-edge distance of the differential pair, in mils; h is the dielectric thickness between each single-ended line in the differential pair and the reference plane, in mils; b is the total thickness of the upper and lower dielectric layers of the stripline, in mils. By comparing with the differential impedance calculated by the precise field solution method, it can be found that the errors of the above two approximate formulas are between 1% and 10%.

[0081] In an optional embodiment, the line spacing of the differential signal lines located in the first area is different from the line spacing of the differential signal lines located in the second area. In this embodiment, when the differential signal lines of the same layer and the same network are set to two different line widths, the impedance consistency of the differential signal lines with different line widths can be met by reasonably adjusting the line spacing of the differential signal lines. In addition, by setting the differential signal lines of the same layer and the same network to two line widths and line spacings, the routing rate of the differential signal lines in the high-density area of ​​the substrate can also be taken into account, and the skin loss of the differential signal lines in the local low-density area is effectively reduced, and the quality of the eye diagram of the differential signal lines is improved.

[0082] In an optional embodiment, the line width of the differential signal line located in the first area is smaller than the line width of the differential signal line located in the second area, and the line spacing of the differential signal line located in the first area is smaller than the line spacing of the differential signal line located in the second area. In this embodiment, when the line width of the differential signal line in the same layer and the same network increases and the line spacing remains unchanged, the impedance of the differential signal line will decrease accordingly, and the line spacing of the differential signal line can be appropriately adjusted to offset the risk of reduced impedance of the differential signal line due to increased line width.

[0083] In an optional implementation manner, the line spacing of the differential signal lines located in the first region is less than or equal to 2.2 times the line width of the differential signal lines located in the first region. Corresponding to the above example, S3≤2.2W1.

[0084] In an optional implementation, the line spacing of the differential signal lines located in the second region is less than or equal to 2.2 times the line width of the differential signal lines located in the second region. Corresponding to the above example, S4≤2.2W2.

[0085] It should be noted that for the conditions of S3≤2.2W1, S4≤2.2W2, there are two coupling modes for differential signal lines, namely tight coupling and loose coupling. When S3>2W1, S4>2W2, the differential signal line is in loose coupling; when S3<2W1, S4<2W2, the differential signal line is in tight coupling. Tight coupling is more conducive to the signal transmission of the differential signal line. The differential signal line is not prone to packet loss when transmitting differential signals, and is not easily interfered by surrounding signal traces and vias, power traces and vias. Therefore, it is preferred that the differential signal line is in a tight coupling mode. Taking into account the influence of other factors such as the distance from the differential signal line to the reference plane and the PCB process technology, the proportional relationship between the line width and the line spacing is relaxed to S3≤2.2W1, S4≤2.2W2. It can also be selected according to the actual situation and is not limited here.

[0086] In other optional implementations, the line spacing of the differential signal lines located in the first area is the same as the line spacing of the differential signal lines located in the second area.

[0087] Two connection methods between different differential signal line widths are given below.

[0088] In an optional implementation manner, the line width of the differential signal line located in the first area and the line width of the differential signal line located in the second area transition in a gradual manner. Figure 3 A schematic diagram showing two different line widths of differential signal lines in the same layer and network, wherein the two different line widths of differential signal lines are transitioned using a gradient method. Figure 3 As shown, the X region is a high-density region of substrate wiring, corresponding to the first region, the line width of the differential signal line 11 in the X region is W1, and the line spacing is S3; the Z region is a low-density region of substrate wiring, corresponding to the second region, the line width of the differential signal line in the Z region is W2, and the line spacing is S4; the Y region is a gradient region, and the Y region is the region where the differential signal line in the X region is connected to the differential signal line in the Z region. The differential signal line 11 is composed of two parallel and symmetrical conductors K1 and K2.

[0089] In an optional implementation manner, the line width of the differential signal line located in the first area and the line width of the differential signal line located in the second area transition in an abrupt manner. Figure 4 A schematic diagram showing two different line widths of differential signal lines in the same layer and network, wherein the differential signal lines of the two different line widths are transitioned using a mutation method. Figure 4 As shown, the X region is a high-density region of substrate wiring, corresponding to the first region, the line width of the differential signal line 11 in the X region is W1, and the line spacing is S3; the Z region is a low-density region of substrate wiring, corresponding to the second region, the line width of the differential signal line in the Z region is W2, and the line spacing is S4; the Y region is a mutation region, and the Y region is the region where the differential signal line in the X region is connected to the differential signal line in the Z region. The differential signal line 11 is composed of two parallel and symmetrical conductors K1 and K2.

[0090] In an optional implementation, a first grounding circuit is provided in the signal layer where the differential signal circuit is located. In one specific implementation example, the differential signal circuit in the first area and the differential signal circuit in the second area are surrounded by the first grounding circuit. In another specific implementation example, the differential signal circuit in the first area is surrounded by the first grounding circuit, and the differential signal circuit in the second area is not surrounded by the first grounding circuit. In another specific implementation example, the differential signal circuit in the first area is not surrounded by the first grounding circuit, and the differential signal circuit in the second area is surrounded by the first grounding circuit.

[0091] In an optional implementation manner, a first signal circuit is provided in the signal layer where the differential signal circuit is located; and the first ground circuit is provided between the first signal circuit and the differential signal circuit.

[0092] In an optional implementation manner, a first power supply circuit is provided in the signal layer where the differential signal circuit is located; and the first ground circuit is provided between the first power supply circuit and the differential signal circuit.

[0093] In an optional embodiment, a ground via is provided in the first grounding circuit. In one specific implementation example, the first grounding circuit is arranged on the top layer and / or bottom layer of the substrate structure, and the ground via passes through the first grounding circuit and the first reference plane in a direction perpendicular to the substrate structure; the ground via is electrically connected to the first grounding circuit and the first reference plane, respectively. In another specific implementation example, the first grounding circuit is arranged in the middle layer of the substrate structure, and the ground via passes through the first grounding circuit, the first reference plane, and the second reference plane, in a direction perpendicular to the substrate structure; the ground via is electrically connected to the first grounding circuit, the first reference plane, and the second reference plane, respectively.

[0094] The first grounding circuit includes ground copper foil and ground wire, etc., and the specific form of grounding is not limited. The first signal circuit can be a clock line, a clock via, an RF signal line, an RF signal via, a digital signal line, a digital signal via, a differential signal line, a differential signal via, etc., and the type of the first signal circuit is not limited. The first power supply circuit includes a power via and a power supply line, etc., and the specific form of grounding is not limited.

[0095] Figure 5 A top view of a ground wire provided in one embodiment of the present application; Figure 6 A top view of a ground copper foil provided in one embodiment of the present application; Figure 7 This is a top view of a ground copper foil provided in another embodiment of the present application. Figure 6 A top view of the copper foil with regular pattern is given; Figure 7 A top view of the irregular pattern ground copper foil is given. It should be noted that the ground copper foil 233 has the same function as the ground wire 234, except that the width of the ground copper foil 233 is larger than the width of the ground wire 234: the width of the ground wire 234 is less than 1 mm, and the width of the ground copper foil 233 is greater than 1 mm. In addition, the line width of the ground wire 234 is fixed, for example, the line width of a ground wire is all 0.8 mm or 0.9 mm. Figure 5 In order to bypass the signal via 901, the ground wire 234 has a bend 902. The shape of the ground wire 234 is not limited. The shape of the ground copper foil 233 can be a regular pattern, such as Figure 6 The shape of the ground copper foil 233 is a regular rectangle, the width of the ground copper foil 233 is ≧1 mm, and a plurality of ground holes 900 are distributed in the ground copper foil 233. The shape of the ground copper foil 233 can also be an irregular pattern, for example Figure 7 The shape of the ground copper foil 233 is an irregular pattern, and there is a slot 905 under the ground copper foil 233. At the same time, the ground copper foil 233 can also have a ground hole 900, a power via 903, and a signal via 901. In order to avoid short circuits between the power via 903 and the signal via 901 in the ground copper foil 233, a clearance area 904 (i.e., a copper-free area) is set between the ground copper foil 233 and the power via 903, and a clearance area 906 (i.e., a copper-free area) is set between the ground copper foil 233 and the signal via 901. That is, Figure 7 The ground copper foil 233 has a slot 905, a clearance area 906, a clearance area 904, etc. The ground copper foil 233 is an irregular shape.

[0096] Figure 8 A top view of a microstrip differential signal line on the bottom layer (BOTTOM layer) of a substrate is given. Fig. 9 A top view of the microstrip differential signal line on the bottom layer of another substrate is given. Figure 8 As shown, a microstrip differential signal line 1 is arranged on the bottom layer of the substrate, a first signal line 300, a power via 310, etc. are arranged near the same layer of the microstrip differential signal line 1, and a ground copper foil 233 is arranged around the same layer of the microstrip differential signal line 1. Figure 8 for Figure 1 and 2 A top view of the first region and the second region of the microstrip differential signal line on the bottom layer of the mid-substrate.

[0097] The microstrip differential signal line 1 is composed of two parallel and symmetrical conductors B1 and B2, and the conductor B1 includes the conductor X1 in the X region, the conductor Y1 in the Y transition region, and the conductor Z1 in the Z region, and the conductor B2 includes the conductor X2 in the X region, the conductor Y2 in the Y transition region, and the conductor Z2 in the Z region. The X region is composed of two parallel and symmetrical conductors X1 and X2, the Y transition region is composed of two parallel and symmetrical conductors Y1 and Y2, and the Z region is composed of two parallel and symmetrical conductors Z1 and Z2. Within the X region, the line width of the conductors X1 and X2 of the microstrip differential signal line 1 is W1, the line spacing between the conductors X1 and X2 of the microstrip differential signal line 1 is S21, and the spacing between the conductors X1 and X2 of the microstrip differential signal line 1 and the surrounding ground copper foil 233 is D31. Within the Z region, the line width of the conductors Z1 and Z2 of the microstrip differential signal line 1 is W2, the line spacing between the conductors Z1 and Z2 of the microstrip differential signal line 1 is S22, and the spacing between the conductors Z1 and Z2 of the microstrip differential signal line 1 and the surrounding ground copper foil 233 is D32.

[0098] The first signal line 300 is arranged in the layer where the microstrip differential signal line 1 is located. Specifically, the first signal line 300 is arranged near the position of the conductors X1 and Y1 of the microstrip differential signal line 1, and the power via 310 is arranged near the position of the conductor X2 of the microstrip differential signal line 1. Since the conductors X1 and Y1 of the microstrip differential signal line 1 are isolated from the first signal line 300 by the ground copper foil 233, the pulse electric field and pulse magnetic field interference generated by the first signal line 300 are isolated by the ground copper foil 233, and the high-frequency pulse electric field and high-frequency pulse magnetic field interference generated by the conductors X1 and Y1 of the microstrip differential signal line 1 are isolated by the ground copper foil 233. The conductors X1, X2, Y1, Y2 of the microstrip differential signal line 1 and the first signal line 300 will not generate mutual pulse electric field and pulse magnetic field coupling, that is, there will be no electromagnetic interference between them. Since the conductor X2 of the microstrip differential signal line 1 is isolated from the power via 310 by the ground copper foil 233, the pulse electric field and pulse magnetic field interference generated by the power via 310 are isolated by the ground copper foil 233, and the high-frequency pulse electric field and high-frequency pulse magnetic field interference generated by the conductors X1 and X2 of the microstrip differential signal line 1 are isolated by the ground copper foil 233. There will be no mutual pulse electric field and pulse magnetic field coupling between the conductors X1 and X2 of the microstrip differential signal line 1 and the power via 310, that is, there will be no electromagnetic interference between them.

[0099] The first signal lines 300 are isolated by the ground copper foil 233, so the pulse electric field and pulse magnetic field interference generated by the first signal line 300 are isolated by the ground copper foil 233, and the high-frequency pulse electric field and high-frequency pulse magnetic field interference generated by the conductors X1 and Y1 of the microstrip differential signal line 1 are isolated by the ground copper foil 233. There is no mutual pulse electric field and pulse magnetic field coupling between the conductors X1 and Y1 of the microstrip differential signal line 1 and the first signal line 300, that is, there is no electromagnetic interference between them.

[0100] Since the conductor X2 of the microstrip differential signal line 1 is isolated from the power via 310 by the ground copper foil 233, the low-frequency pulse electric field and low-frequency pulse magnetic field interference generated by the power via 310 are isolated by the ground copper foil 233, and the high-frequency pulse electric field and high-frequency pulse magnetic field interference generated by the conductors X1 and Y1 of the microstrip differential signal line 1 are isolated by the ground copper foil 233. There is no coupling of pulse electric field and pulse magnetic field between the conductors X1 and Y1 of the microstrip differential signal line 1 and the power via 310, that is, there is no electromagnetic interference between them. The ground copper foil 233 is set around the two conductors X1 and X2 in the X region of the same layer of the microstrip differential signal line 1, the ground copper foil 233 is set around the two conductors Y1 and Y2 in the Y region, and the ground copper foil 233 is set around the two conductors Z1 and Z2 in the Z region. The ground copper foil 233 shields the microstrip differential signal line 1 from external radiation interference, and also avoids external radiation interference of the microstrip differential signal line 1. However, the ground copper foil 233 set in the X region, Y region, and Z region of the same layer of the microstrip differential signal line 1 is too close to the two conductors of the microstrip differential signal line 1, which will affect its impedance parameters. Taking the conductors X1 and X2 of the microstrip differential signal line 1 in the X region as an example, when there is no ground copper foil 233 around the same layer of the conductors X1 and X2 of the microstrip differential signal line 1, the calculated impedance value is 100 ohms, and when the ground copper foil 233 is set around the same layer of the conductors X1 and X2 of the microstrip differential signal line 1, and the distance D31 between the ground copper foil 233 and the conductors X1 and X2 is less than 2 times the line width W1, the calculated impedance of the microstrip differential signal line 1 will become smaller.

[0101] Will Figure 8 Replacing the ground copper foil 233 with the ground wire 234 can yield Fig. 9 ,in, Fig. 9 The role of ground wire 234 in the scheme and Figure 8 The function of the copper foil 233 in the solutions is basically the same and will not be described again.

[0102] exist Figure 1 , Figure 8 , Fig. 9The first grounding line is set around the microstrip differential signal line 1, the strip differential signal line 2, the strip differential signal line 3, and the microstrip differential signal line 4 in the same layer. The first grounding line is set around the microstrip differential signal line 1 on the bottom layer, and the first grounding line surrounds the microstrip differential signal line 1 on the bottom layer; the first grounding line is set around the microstrip differential signal line 4 on the bottom layer, and the first grounding line surrounds the microstrip differential signal line 4 in the bottom layer; the first grounding line is set around the strip differential signal line 2 on the LY03 layer, and the first grounding line surrounds the strip differential signal line 2 in the LY03 layer; the first grounding line is set around the strip differential signal line 3 on the LY04 layer, and the first grounding line surrounds the strip differential signal line 3 in the LY04 layer. Therefore, the microstrip differential signal line 1, the strip differential signal line 2, the strip differential signal line 3, and the microstrip differential signal line 4 are all coplanar differential signal lines, and the distance between the first grounding line and the coplanar differential signal line will affect the impedance of the coplanar differential signal line.

[0103] Continue reading Figure 8 and 9 Since the first ground line is not set around the same layer of the differential signal line, Figure 8 and 9 The differential signal line shown is a characteristic differential signal line. The impedance of the characteristic differential signal line is not affected by the surrounding first ground line on the same layer.

[0104] In an optional embodiment, the first area is located on the surface layer of the substrate, the differential signal circuit located in the first area is provided with ink, and the differential signal circuit located in the second area is not provided with ink.

[0105] Fig.10 A cross-sectional view of a characteristic differential signal line disposed on a top layer or a bottom layer of a substrate is provided, wherein: Fig.10 for Figure 3 sectional view of the cross section. Among them, C1 is the thickness of the ink covering the characteristic differential signal line 11, C2 is the thickness of the ink covering the copper-free area between the characteristic differential signal line 11 and the surrounding lines, C3 is the thickness of the ink covering the copper-free area between the conductors B1 and B2 in the characteristic differential signal line 11, S1 is the distance between the bottom of the conductors B1 and B2 in the characteristic differential signal line 11, T1 is the thickness of the conductors B1 and B2 in the characteristic differential signal line 11, and H1 is the thickness of the PP from the conductors B1 and B2 in the characteristic differential signal line 11 to the reference plane of the adjacent layer. Among them, PP is a semi-cured sheet, which is a sheet-like adhesive material synthesized from resin and carrier, a glass fiber epoxy resin material, and a type of FR-4 medium. Fig.11 Provide a cross-sectional view of a vertical section of a characteristic differential signal line arranged on the top or bottom layer of a substrate, Fig.11for Figure 3 Ink 700 is provided in the first region (X region) and the second region (Z region) of the conductors B1 and B2 of the characteristic differential signal line.

[0106] by Figure 3 , Fig.10 , Fig.11 The characteristic differential signal line 11 is set on the top layer of the substrate as an example for analysis and explanation. The characteristic differential signal line 11 uses the adjacent GND02 layer as the reference plane. The impedance calculation tool SI9000 is used to obtain Figure 3 , Fig.10 , Fig.11 The impedance of the characteristic differential signal line in the X area of ​​the top layer is 100.06 ohms, as shown below: Fig.12 The corresponding parameter values ​​and the impedance values ​​of the characteristic differential signal lines in the top layer X area are calculated by SI9000 using the parameters:

[0107] Substrate 1Height H1: 8.0mil, the thickness of the conductor B1 and B2 in the characteristic differential signal line to the PP of the adjacent layer reference plane is 8.0mil; Substrate 1Dielectric Er1: 4.2, the dielectric constant of the insulation layer between the characteristic differential signal line and the reference ground copper foil is 4.2; Lower Trace Width W1: 5.58mil, the line width of the lower part of the characteristic differential signal line is 5.58mil; Upper Trace Width W2: 4.58mil, the line width of the upper part of the characteristic differential signal line is 4.58mil; Trace Separation: S1: 4.0mil, the distance between the characteristic differential signal line conductors B1 and B2 is 4.0mil; Trace Thickness T1: 1.2mil, the thickness of the characteristic differential signal line conductors B1 and B2 is 1.2mil; Coating Above Substrate C1: 0.4mil, the thickness of the ink on the characteristic differential signal line conductors B1 and B2 is 0.4mil; Coating Above Trace C2: 1mil, the thickness of the ink from the characteristic differential signal line conductors B1 and B2 to the surrounding copper foil-free area is 1mil; Coating Between Trace C3: 1mil, the thickness of the ink in the copper foil-free area between the characteristic differential signal line conductors B1 and B2 is 1mil; Coating Dielectric: 4.2, the dielectric constant of the ink is 4.2; Impedance: 100.06 ohms, the calculated impedance value is 100.06 ohms.

[0108] The impedance calculation tool SI9000 is used to obtain Fig.11 The impedance of the characteristic differential signal line in the top layer X area is 100.06 ohms based on the impedance of the ground copper foil G2 of the GND02 layer. Fig.13 The corresponding parameter values ​​and the impedance values ​​of the characteristic differential signal lines in the top layer Z area are calculated by SI9000 using the parameters:

[0109] Substrate 1Height H1: 8.0mil, the thickness of the conductor B1 and B2 in the characteristic differential signal line 11 to the PP of the adjacent layer reference plane is 8.0mil; Substrate 1Dielectric Er1: 4.2, the dielectric constant of the insulation layer between the characteristic differential signal line 11 and the reference ground copper foil is 4.2; Lower Trace Width W1: 6.55mil, the line width of the lower part of the characteristic differential signal line 11 is 6.55mil; Upper Trace Width W2: 5.55mil, the line width of the upper part of the characteristic differential signal line 11 is 5.55mil; Trace Separation: S1: 4.7mil, the distance between the conductors B1 and B2 of the characteristic differential signal line 11 is 4.7mil; Trace Thickness T1: 1.2mil, the thickness of the conductors B1 and B2 of the characteristic differential signal line is 1.2mil; Coating Above Substrate C1: 0.4mil, the thickness of the ink on the conductors B1 and B2 of the characteristic differential signal line 11 is 0.4mil; Coating Above Trace C2: 1mil, the thickness of the ink from the conductors B1 and B2 of the characteristic differential signal line 11 to the surrounding copper foil-free area is 1mil; Coating Dielectric: 4.2, the dielectric constant of the ink is 4.2; Impedance: 100.09 ohms, the calculated impedance value is 100.09 ohms.

[0110] In summary, Fig.11 The line width of the characteristic differential signal line 11 in the X area, i.e., the high-density area, is 5.58 mil, the line spacing is 4 mil, and the impedance value calculated by the impedance calculation tool SI9000 is 100.06 ohms, which is within the target impedance range of 100 ohms ±10 ohms of the differential signal line 11, i.e., 90 ohms to 110 ohms; and Fig.11The line width of the characteristic differential signal line 11 in the Z region, i.e., the low-density region, is 6.55 mil, and the line spacing is 4.7 mil. The impedance value calculated using the impedance calculation tool SI9000 is 100.09 ohms, which is within the impedance range of the target impedance of the differential signal line 11 of 100 ohms ±10 ohms. The line width of the characteristic differential signal line 11 in the Z region, 6.55 mil, is greater than the line width of 5.58 mil in the X region, and the characteristic differential signal line 11 in the Z region can greatly reduce the skin loss, thereby achieving the purpose of reducing the insertion loss and improving the eye diagram quality. The wider the line width of the differential signal line, the smaller the skin loss. Among them, the insertion loss includes skin loss and dielectric loss.

[0111] It should be noted that, combined with Figure 3 , Fig.11 and Fig.12 , the line width of the characteristic differential signal line 11 in the X region is 5.58mil, and the line spacing of the conductors K1 and K2 is 4mil. The line spacing of the conductors K1 and K2 in the characteristic differential signal line 11 in the X region is 4mil, which is much smaller than 2 times the line width, i.e., 2×5.58mil=11.16mil. The characteristic differential signal line 11 in the X region is in a tightly coupled state. The characteristic differential signal line 11 in the X region is not prone to packet loss when transmitting differential signals, and is not easily interfered by surrounding signal lines or signal vias, power lines or power vias. Combined with Figure 3 , Fig.11 and Fig.13 , the line width of the characteristic differential signal line 11 in the Z region is 6.55mil, and the line spacing of the conductors K1 and K2 is 4.7mil. The line spacing of the conductors K1 and K2 in the characteristic differential signal line 11 in the Z region is 4.7mil, which is much smaller than 2 times the line width, i.e. 2×6.55mil=13.1mil. The characteristic differential signal line 11 in the Z region is in a tightly coupled state. The characteristic differential signal line 11 in the Z region is not prone to packet loss when transmitting differential signals, and is not easily interfered by surrounding signal lines or signal vias, power lines or power vias. Therefore, Fig.12 and Fig.13 Various settings of the medium characteristic differential signal line 11 in the X region and the Z region are feasible and scientific.

[0112] Fig.14Another cross-sectional view of a vertical section of a characteristic differential signal circuit arranged on the top or bottom layer of a substrate is given. Ink 700 is arranged in the X region of the conductors B1 and B2 of the characteristic differential signal circuit, and the ink 700 is removed in the Z region of the conductors B1 and B2 of the characteristic differential signal circuit to obtain a differential signal circuit 701 with exposed copper, which further reduces the loss of the conductors B1 and B2 of the characteristic differential signal circuit in the Z region. Since the ink 700 covers the conductors B1 and B2 of the characteristic differential signal circuit, there will also be dielectric loss, so the eye diagram quality of the differential signal in the characteristic differential signal circuit can be further improved. That is, the line width of the differential signal circuit in the Z region is not only wider than the line width of the differential signal circuit in the X region, but also has smaller skin loss than that of the differential signal circuit in the X region. After removing the ink on the conductors B1 and B2 of the differential signal circuit in the Z region, the dielectric loss is smaller than that of the differential signal circuit in the X region.

[0113] by Figure 3 , Fig.10 , Fig.14 The characteristic differential signal line 11 is set on the top layer of the substrate as an example for analysis and explanation. The characteristic differential signal line 11 uses the adjacent GND02 layer as the reference plane. The impedance calculation tool SI9000 is used to obtain Figure 3 , Fig.10 , Fig.11 The impedance of the characteristic differential signal line 11 in the top layer X region is 100.06 ohms with reference to the impedance of the ground copper foil G2 of the GND02 layer. The following are the corresponding parameter values ​​and the impedance values ​​of the characteristic differential signal line 11 in the top layer X region calculated by SI9000 using the parameters:

[0114] Substrate 1Height H1: 8.0mil, the thickness of the conductor B1 and B2 in the characteristic differential signal line 11 to the PP of the adjacent layer reference plane is 8.0mil; Substrate 1Dielectric Er1: 4.2, the dielectric constant of the insulation layer between the characteristic differential signal line 11 and the reference ground copper foil is 4.2; Lower Trace Width W1: 5.58mil, the line width of the lower part of the characteristic differential signal line 11 is 5.58mil; Upper Trace Width W2: 4.58mil, the line width of the upper part of the characteristic differential signal line 11 is 4.58mil; Trace Separation: S1: 4.0mil, the distance between the conductors B1 and B2 of the characteristic differential signal line 11 is 4.0mil; Trace Thickness T1: 1.2mil, the thickness of the conductors B1 and B2 of the characteristic differential signal line 11 is 1.2mil; Coating Above Substrate C1: 0.4mil, the thickness of the ink on the conductors B1 and B2 of the characteristic differential signal line 11 is 0.4mil; Coating Above Trace C2: 1mil, the thickness of the ink from the conductors B1 and B2 of the characteristic differential signal line 11 to the surrounding copper-free area is 1mil; Coating Between Trace C3: 1mil, the thickness of the ink in the copper-free area between the conductors B1 and B2 of the characteristic differential signal line 11 is 1mil; Coating Dielectric: 4.2, the dielectric constant of the ink is 4.2; Impedance: 100.06 ohms, the calculated impedance value is 100.06 ohms.

[0115] The impedance calculation tool SI9000 is used to obtain Fig.14 The impedance of the characteristic differential signal line in the X region of the middle top layer is 100.06 ohms, referring to the impedance of the ground copper foil G2 of the GND02 layer. The following are the corresponding parameter values ​​and the impedance values ​​of the characteristic differential signal line in the Z region of the top layer calculated by SI9000 using the parameters:

[0116] Substrate 1Height H1: 8.0mil, the thickness of the conductors B1 and B2 in the characteristic differential signal line to the PP of the adjacent layer reference plane is 8.0mil; Substrate 1Dielectric Er1: 4.2, the dielectric constant of the insulating layer between the characteristic differential signal line and the reference ground copper foil is 4.2; Lower Trace Width W1: 7.65mil, the line width of the lower part of the characteristic differential signal line is 7.65mil; Upper Trace Width W2: 6.65mil, the line width of the upper part of the characteristic differential signal line is 6.65mil; Trace Separation: S1: 4.0mil, the distance between the characteristic differential signal line conductors B1 and B2 is 4.0mil; Trace Thickness T1: 1.2mil, the thickness of the characteristic differential signal line conductors B1 and B2 is 1.2mil; Impedance: 100.01 ohms, the calculated impedance value is 100.01 ohms.

[0117] In summary, Fig.14 The line width of the characteristic differential signal line 11 in the X area, i.e., the high-density area, is 5.58 mil, the line spacing is 4 mil, and the impedance value calculated by the impedance calculation tool SI9000 is 100.06 ohms, which meets the target impedance of the differential signal line 11 of 100 ohms ± 10 ohms (that is, within the range of 90 ohms to 110 ohms); and Fig.14 The line width of the characteristic differential signal line 11 in the Z region, i.e., the low-density region, is 7.65 mil, and the line spacing is 4 mil. The impedance value calculated using the impedance calculation tool SI9000 is 100.01 ohms, which meets the target impedance of the differential signal line 11 of 100 ohms ± 10 ohms (that is, within the range of 90 ohms to 110 ohms). The line width of the characteristic differential signal line 11 in the Z region, 7.65 mil, is greater than the line width of 5.58 mil in the X region, which can greatly reduce the skin loss; and removing the ink 700 covering the Z region of the characteristic differential signal line 11 can greatly reduce the dielectric loss caused by the ink 700 and improve the eye diagram quality. Fig.14 Although the line widths of the medium characteristic differential signal line 11 in the X region and the Z region are different, the line spacing is 4 mil, and the impedance of the X region and the impedance of the Z region both meet the same impedance range, which is the target impedance of the differential signal line 11 of 100 ohms ± 10 ohms, that is, 90 ohms to 110 ohms.

[0118] It should be noted that, combined with Figure 3 and Fig.14, the line width of the characteristic differential signal line 11 in the X region is 5.58mil, and the line spacing of the conductors K1 and K2 is 4mil. The line spacing of the conductors K1 and K2 in the characteristic differential signal line 11 in the X region is 4mil, which is much smaller than 2 times the line width, i.e., 2×5.58mil=11.16mil. The characteristic differential signal line 11 in the X region is in a tightly coupled state. The characteristic differential signal line 11 in the X region is not prone to packet loss when transmitting differential signals, and is not easily interfered by surrounding signal lines or signal vias, power lines or power vias. Combined with Figure 3 and Fig.14 The line width of the characteristic differential signal line 11 in the Z region is 7.65 mil, and the line spacing of the conductors K1 and K2 is 4 mil. The line spacing of the conductors K1 and K2 of the characteristic differential signal line 11 in the Z region is 4 mil, which is much smaller than 2 times the line width (i.e., 2×7.65 mil=15.3 mil). The characteristic differential signal line 11 in the Z region is in a tightly coupled state. The characteristic differential signal line 11 in the Z region is not prone to packet loss when transmitting differential signals, and is not easily interfered by surrounding signal routings or signal vias, power routings or power vias. Therefore, the above-mentioned settings of the characteristic differential signal line 11 in the X region and the Z region are feasible and scientific.

[0119] It should be noted that Figure 4 After the ink is removed from the characteristic differential signal line 11 in the middle Z area, the following situations may occur: direct copper exposure, copper exposure after chemical nickel-gold surface treatment, copper exposure after chemical palladium-gold surface treatment, copper exposure after immersion tin surface treatment, copper exposure after immersion silver surface treatment, etc. Direct copper exposure mainly refers to the solder pads, test points, copper exposure positions, etc. of the substrate, which are treated with OSP surface treatment and high-temperature reflow soldering. The test points and copper exposure positions without tinning will expose the copper foil, that is, they are in direct contact with the air, which is easy to oxidize and corrode, and are generally not used. After the ink is removed from the characteristic differential signal line 11 in the Z area, the copper exposure is exposed after chemical nickel-gold surface treatment, copper exposure after chemical palladium-gold surface treatment, copper exposure after immersion tin surface treatment, and copper exposure after immersion silver surface treatment. This can not only reduce the dielectric loss of the characteristic differential signal line 11 in the Z area, but also is not easy to oxidize and corrode.

[0120] In an optional embodiment, the impedance formed between the differential signal line in the first region and the first reference plane and the impedance formed between the differential signal line in the second region and the first reference plane are within the same impedance range. In this embodiment, the differential signal lines of the same layer and the same network are to be set with two different line widths, but the differential signal lines of the two different line widths are impedance controlled based on the first reference plane. Among them, the first reference plane includes two situations:

[0121] First, when the differential signal lines are arranged on the top layer and / or the bottom layer of the substrate, the impedance control of the differential signal lines (two different line widths) of the same layer and the same network in the high-density area (X area) of the substrate wiring and the impedance control in the low-density area (Z area) of the substrate wiring are both based on their adjacent ground layer as the first reference plane. Figure 1 and Figure 2 It can be seen that the impedance control of the differential signal line located at the bottom layer (BOTTOM layer), i.e., the differential signal line 1, in the high-density area (X area) of the substrate wiring and the impedance control in the low-density area (Z area) of the substrate wiring both use the ground copper foil G9 in the ground layer adjacent to the BOTTOM layer, i.e., the GND09 layer, as the first reference plane.

[0122] Second, when the differential signal line is set in the middle layer of the substrate, that is, the signal layer inside the substrate, the first reference plane of the differential signal line in the high-density area (X area) of the substrate wiring and in the low-density area (Z area) of the substrate wiring includes the adjacent proximal reference plane (i.e., the proximal ground layer) and the adjacent distal reference plane (i.e., the distal ground layer). Figure 1 and Figure 2 It can be seen that in the high-density area (X area) of substrate wiring and in the low-density area (Z area) of substrate wiring, the distance between the differential signal line in the LY03 layer, that is, the differential signal line 2, and the proximal reference plane GND02 layer is H3, and the distance between the differential signal line 2 in the LY03 layer and the distal reference plane GND05 layer is H4, and H4>H3, and the impedance effect of the proximal reference plane on the differential signal line 2 is greater than the impedance effect of the distal reference plane on the differential signal line 2. When the differential signal line 2 of the LY03 layer transitions from the line width W1 in the high-density area of ​​the substrate to the line width W2 in the low-density area of ​​the substrate, the line spacing of the differential signal line 2 can be appropriately adjusted to offset the risk of reduced impedance of the differential signal line 2 due to the increase in line width.

[0123] In an optional embodiment, the impedance formed by the differential signal line in the first area and the first reference plane is the same as the impedance formed by the differential signal line in the second area and the second reference plane. The differential signal lines in the same layer and the same network should be set with two different line widths. Although the impedance of the differential signal lines in the first area and the second area is consistent, the impedance of the differential signal line in the first area is controlled based on the first reference plane, and the impedance of the differential signal line in the second area is controlled based on the second reference plane. Among them, the first reference plane and the second reference plane include two situations:

[0124] First, when the differential signal line is set on the top layer of the substrate, the impedance control in the high-density area (X area) is controlled with the ground layer adjacent to the top layer as the reference, that is, the ground layer adjacent to the top layer is the first reference plane; when the differential signal line is set on the bottom layer, the impedance control in the high-density area (X area) is controlled with the ground layer adjacent to the bottom layer as the reference, that is, the ground layer adjacent to the bottom layer is the first reference plane. When the differential signal line is set on the top layer, the impedance control in the low-density area (Z area) is not controlled with the ground layer adjacent to the top layer as the reference, the differential signal line on the top layer is projected on the ground layer adjacent to the top layer for hollowing out, and the projection of the differential signal line on the top layer on the internal signal layer adjacent to the ground layer adjacent to the top layer is copper-clad (local ground plane), so that the differential signal line on the top layer uses the ground plane on the projection area of ​​the differential signal line on the top layer on the internal signal layer adjacent to the ground layer adjacent to the top layer as the impedance reference. When the differential signal line is set on the bottom layer, the impedance control in the low-density area (Z area) is not controlled based on the ground layer adjacent to the bottom layer. The differential signal line on the bottom layer is hollowed out by projection on the ground layer adjacent to the bottom layer, and the projection of the differential signal line on the bottom layer on the internal signal layer adjacent to the ground layer adjacent to the bottom layer is copper-clad (local ground plane), so that the differential signal line on the bottom layer uses the ground plane on the projection area of ​​the differential signal line on the bottom layer on the internal signal layer adjacent to the ground layer adjacent to the bottom layer as the impedance reference. Figure 1 It can be seen that the differential signal line located at the bottom layer (BOTTOM layer), that is, the differential signal line 4, is impedance controlled in the high-density area (X area) of the substrate wiring with the ground copper foil G9 in the GND09 layer as the first reference plane. Figure 2It can be seen that the differential signal line located at the bottom layer (BOTTOM layer), that is, the differential signal line 4, is not impedance-controlled with the ground copper foil G9 in the GND09 layer as the first reference plane in the low-density area (Z area) of the substrate wiring. The differential signal line 4 of the bottom layer is hollowed out by projection on the GND09 layer adjacent to the bottom layer (to obtain the hollowed-out area 40), and the differential signal line 4 of the bottom layer is copper-clad on the projection of the LY08 layer to obtain a local ground plane (ground copper foil G8), so that the differential signal line 4 of the bottom layer uses the local ground plane (ground copper foil G8) on the projection area of ​​the differential signal line 4 on the LY08 layer as the reference of impedance. Since the differential signal line 4 is farther away from the reference plane in the Z area than in the X area, the differential signal line 4 can be set with a wider line width in the Z area than in the X area, further reducing the skin loss on the differential signal line signal, which greatly improves the loss of high-speed differential signal lines with long-distance transmission. In addition, whether the differential signal line 4 is in the Z region or the X region, a first grounding line such as a ground copper foil 233 is arranged around the same layer of the differential signal line 4 to increase the isolation of the differential signal line 4. On the one hand, it prevents the radiation on the differential signal line 4 from leaking outward, and on the other hand, it prevents the differential signal line 4 from interfering with other signals, and also prevents other signals from interfering with the differential signal line 4. It should be noted that the first grounding line arranged around the same layer of the differential signal line 4 needs to have more ground vias 900 and the ground layer (for example Figure 3 and Figure 4 The first grounding line of the same layer cannot be too close to the differential signal line 4, otherwise the local grounding copper foil of the same layer will affect the impedance of the differential signal line 4.

[0125] Second, when the differential signal line is set in the middle layer of the substrate, that is, the signal layer inside the substrate, the first reference plane of the differential signal line in the high-density area (X area) of the substrate wiring includes the adjacent proximal reference plane (that is, the proximal ground layer) and the adjacent distal reference plane (that is, the distal ground layer); in the low-density area (Z area) of the substrate wiring, the projection area of ​​the differential signal line on the proximal ground layer is hollowed out, and the second reference plane of the differential signal line in the low-density area of ​​the substrate wiring includes the reference ground layer adjacent to the middle layer and the distal ground layer, and the reference ground layer is the ground layer adjacent to the proximal ground layer. Figure 1 It can be seen that in the high-density area (X area) of the substrate wiring, the distance from the differential signal line 3 in the LY04 layer to the far-end reference plane GND02 layer is H5, and the distance from the differential signal line 3 in the LY04 layer to the near-end reference plane GND05 layer is H6, and H5>H6. The near-end reference plane has a greater impact on the impedance of the differential signal line than the far-end reference plane. Figure 2It can be seen that in the low-density area (Z area) of the substrate wiring, the distance from the differential signal line 3 in the LY04 layer to the far-end reference plane GND02 layer is H5, and the distance from the differential signal line 3 in the LY04 layer to the near-end reference plane GND06 layer is H7, and H5>H7; the differential signal line 3 in the LY04 layer is hollowed out on the projection of the GND05 layer (to obtain the hollowed-out area 30), so that the differential signal line 3 in the LY04 layer uses the GND06 layer as the near-end reference plane. Since the near-end plane of the differential signal line 3 in the Z area is farther than that in the X area, the differential signal line 3 can be set with a wider line width in the Z area than in the X area, further reducing the skin loss of the differential signal line signal, which greatly improves the loss of high-speed differential signal lines transmitted over long distances. In addition, whether the differential signal line 3 is in the Z region or the X region, a first grounding line 233 is arranged around the same layer of the differential signal line 3 to increase the isolation of the differential signal line 3. On the one hand, it prevents the radiation on the differential signal line 3 from leaking outward, and on the other hand, it prevents the differential signal line 3 from interfering with other signals, and also prevents other signals from interfering with the differential signal line 3. It should be noted that the first grounding line arranged around the same layer of the differential signal line 3, such as the ground copper foil 233, needs to have more ground vias 900 connected to the ground layer (for example, Figure 1 and Figure 2 The GND06 layer, GND09 layer, and GND02 layer in the same layer are electrically connected, and the first ground line on the same layer cannot be too close to the differential signal line 3, otherwise the local grounding copper foil on the same layer will affect the impedance of the differential signal line 3.

[0126] Fig.15 Used to show Figure 3 The cross-sectional view in the vertical direction of the substrate. The differential signal line 11 can be arranged on the top layer or the bottom layer of the substrate. Taking the differential signal line 11 arranged on the top layer of the substrate as an example, a local grounding metal plane or a whole-board grounding metal plane is arranged on the second layer adjacent to the differential signal line 11. Fig.15As shown, a local grounding metal plane G is provided on the second layer adjacent to the differential signal line 11, and the local grounding metal plane G completely covers the differential signal line 11 on the top layer, that is, the projection of the differential signal line 11 on the top layer on the adjacent second layer all falls on the local grounding metal plane G, that is, among the differential signal lines 11 on the top layer, whether it is the differential signal line 11 in the X region, the differential signal line 11 in the Y region, or the differential signal line 11 in the Z region, all completely refer to the local grounding metal plane G, and the local grounding metal plane G has a very large influence on the impedance of the differential signal line 11 in the X region, the differential signal line 11 in the Y region, and the differential signal line 11 in the Z region. The impedance of the differential signal line 11 in the X region, the impedance of the differential signal line 11 in the Y region, and the impedance of the differential signal line 11 in the Z region are related to the line width W1 of the conductor K1, the line width W2 of the conductor K2, the distance S4 between the conductor K1 and the conductor K2, the dielectric constant of the substrate, whether the line width W1 of the conductor K1 and the line width W2 of the conductor K2 are covered with ink, and the distance between the conductor K1 and the local grounding metal plane G. It should be noted that the impedance of the differential signal line 11 in the X region and the differential signal line 11 in the Z region can be within the same impedance range, for example, they both meet the tolerance range of 10% or 8% of the target impedance, which can also avoid the differential signal line 11 from having signal reflection when transmitting differential signals and affecting the quality of the eye diagram.

[0127] and Fig.15 compared to, Fig.16Among the differential signal lines 11 in the middle and top layers, only the projections of the differential signal lines 11 in the Z region on the adjacent second layer all fall on the local grounding metal plane G, the projections of the differential signal lines 11 in the Y region on the adjacent second layer may fall on the local grounding metal plane G, or may not fall on the local grounding metal plane G, but the projections of the differential signal lines 11 in the X region on the adjacent second layer do not fall on the local grounding metal plane G, that is, the differential signal lines 11 in the X region hollow out the local grounding metal plane G on the adjacent second layer, that is, the differential signal lines 11 in the X region do not have any grounding metal plane as a reference, that is, the impedance of the differential signal lines 11 in the X region is only related to the line width W1 of the conductor K1, the line width W2 of the conductor K2, the distance S4 between the conductor K1 and the conductor K2, the dielectric constant of the substrate, whether the line width W1 of the conductor K1 and the line width W2 of the conductor K2 are covered with ink, etc., and has nothing to do with the distance between the grounding metal planes. The impedance of the differential signal line 11 in the Z region is related to the line width W1 of the conductor K1, the line width W2 of the conductor K2, the distance S4 between the conductor K1 and the conductor K2, the dielectric constant of the substrate, whether the line width W1 of the conductor K1 and the line width W2 of the conductor K2 are covered with ink, etc., and is also related to the distance between the adjacent second-layer local grounding metal planes G2. It should be noted that the impedance of the differential signal line 11 in the X region and the differential signal line 11 in the Z region can be within the same impedance range, for example, they both meet the 10% or 8% tolerance range of the target impedance, which can also avoid the differential signal line 11 from having signal reflection when transmitting differential signals and affecting the quality of the eye diagram.

[0128] and Fig.15 and 16 compared to, Fig.17The differential signal lines 11 in the X region, the differential signal lines 11 in the Y region, and the differential signal lines 11 in the Z region of the top layer do not refer to any grounded metal plane, and the impedance of the differential signal lines 11 in the X region, the differential signal lines 11 in the Y region, and the differential signal lines 11 in the Z region are related to the line width W1 of the conductor K1, the line width W2 of the conductor K2, the distance S4 between the conductor K1 and the conductor K2, the dielectric constant of the substrate, and whether the line width W1 of the conductor K1 and the line width W2 of the conductor K2 are covered with ink. That is, the impedance of the differential signal lines 11 in the X region, the impedance of the differential signal lines 11 in the Y region, and the impedance of the differential signal lines 11 in the Z region are not affected by the grounded metal plane of the adjacent layer. It should be noted that the impedances of the differential signal line 11 in the X region and the differential signal line 11 in the Z region are both within the same impedance range, for example, both meet the 10% or 8% tolerance range of the target impedance. This can also avoid the differential signal line 11 from being mutually coupled to achieve reflux when transmitting the differential signal, and will not cause signal reflection to affect the quality of the eye diagram.

[0129] During the test of a fixed network motherboard, it was found that the 1.25GHz signal sent by an external optical port had serious bit errors in the service board. After inspection, it was found that in the 12-layer single board, in order to control its 100-ohm impedance within a thickness of 2mm, a 4mil / 8mil routing structure was used. Due to structural limitations, the routing length reached 20 inches, resulting in excessive loss. The eye diagram was tested on the half of the differential signal routing and found to be good. Under the condition of meeting the impedance, try to adjust the width of the differential signal line to minimize the loss.

[0130] It should be noted that, in order to prove the design rationality and practicality of the differential signal line structure in the above embodiment of the present disclosure, Figure 1 The differential signal line structure shown is applied to the Wifi6 router with video recording function. The Wifi6 router with video recording function has a built-in SATA hard disk. The SATA hard disk adopts the SATAII interface. The PCB board adopts a 6-layer board structure. After fine differentiation and wiring, the SATAII signal line impedance is strictly within the range of 100Ω+ / -10Ω. After the product is proofed, it can pass the first functional test, signal test, EMC test, and power supply test normally.

[0131] The following is the entire SATAII signal test and analysis process: The signal test mainly uses SATAII (3.0Gb / s) as an example to explain its performance test. For the SATAII (3.0Gb / s) signal test, a high sampling rate, high bandwidth oscilloscope (TDS7704B) and Tektronix related test software are used to test and analyze the SATA signal. The SATAII (3.0Gb / s) bus signal is mainly verified by the signal voltage, timing, transmission rate and its stability (mainly verified by jitter test). After these verification indicators are tested by software, the results are generally reflected in the form of eye diagrams. The following will specifically explain the test and analysis results of the SATAII (3.0Gb / s) eye diagram.

[0132] Here we will simply illustrate the test results of two SATAII (3.0Gb / s) interfaces. As shown in the figure, Fig.18 and Fig.19 The SATA_TX0 eye diagram and test results are shown respectively. Fig.18 It can be seen that the eye diagram does not intersect with the gray standard area, and there is a long distance between them. The eye amplitude is small, indicating that the SATAII (3.0Gb / s) signal meets the quality specification, the signal jitter is very small, and there is no crosstalk. Fig.19 As can be seen, the performance parameter values ​​of the SATAII interface are all very good and within the specification range. All passed the test and the result shows pass. Fig.19 The test results show that the transmission rate is 3.0012Gb / s, the maximum left-right jitter is 14.9712ps, and the minimum left-right jitter of the eye diagram is 7.5684ps; the maximum up-down jitter is 26.31056ps, and the minimum up-down jitter is 14.13544ps, which fully meets the design requirements. The maximum and minimum values ​​of the signal voltage amplitude are also within the specification range of -0.35V to 0.35V, which meets the design requirements. Among them, SATA_TX0 refers to the transmission signal of SATAII interface 1.

[0133] Example 2

[0134] This embodiment provides a communication device, including the substrate structure described in Embodiment 1.

[0135] In specific implementations, the above-mentioned communication equipment can be a driving recorder, Wifi5 / Wifi6 / Wifi7 router, mobile phone, VR / AR product, tablet, notebook, industrial computer, medical equipment, server, 100G switch, wireless base station motherboard, etc.

[0136] In this embodiment, the substrate structure in the communication device can take into account the routing rate of the differential signal lines in the high-density area of ​​the substrate by setting the differential signal lines of the same layer and the same network to two line widths and line spacings, and effectively reduce the skin loss of the differential signal lines in the local low-density area, improve the quality of the eye diagram of the differential signal lines, and thus improve the signal transmission performance of the communication device.

[0137] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A substrate structure, characterized in that: include: at least one signal layer, wherein the wiring density of the first area of ​​the substrate structure is higher than the wiring density of the second area; A differential signal line is provided in the signal layer, the line width of the differential signal line in the first area is different from the line width of the differential signal line in the second area, and the impedance formed by the differential signal line in the first area and the impedance formed by the differential signal line in the second area are within the same impedance range.

2. The substrate structure according to claim 1, characterized in that: The substrate structure further includes at least one ground layer, and the ground layer is stacked between the signal layer.

3. The substrate structure according to claim 2, characterized in that: The adjacent layers of the layer where the differential signal line in the first region is located are not ground layers, and at least one adjacent layer of the layer where the differential signal line in the second region is located is a ground layer.

4. The substrate structure according to claim 1, characterized in that: The line pitch of the differential signal lines located in the first region is different from the line pitch of the differential signal lines located in the second region.

5. The substrate structure according to claim 4, characterized in that: The line width of the differential signal line located in the first area is smaller than the line width of the differential signal line located in the second area, and the line spacing of the differential signal line located in the first area is smaller than the line spacing of the differential signal line located in the second area.

6. The substrate structure according to claim 5, characterized in that: The line spacing of the differential signal lines located in the first region is less than or equal to 2.2 times the line width of the differential signal lines located in the first region; And / or, the line spacing of the differential signal lines located in the second region is less than or equal to 2.2 times the line width of the differential signal lines located in the second region.

7. The substrate structure according to claim 1, characterized in that: The line spacing of the differential signal lines located in the first area is the same as the line spacing of the differential signal lines located in the second area.

8. The substrate structure according to claim 1, characterized in that: A first grounding circuit is provided in the signal layer where the differential signal circuit is located; The differential signal lines in the first area and the differential signal lines in the second area are surrounded by the first ground line; Alternatively, the differential signal circuit in the first area is surrounded by a first ground circuit, and the differential signal circuit in the second area is not surrounded by the first ground circuit; Alternatively, the differential signal lines in the first region are not surrounded by the first ground line, and the differential signal lines in the second region are surrounded by the first ground line.

9. The substrate structure according to claim 8, characterized in that: A first signal circuit is provided in the signal layer where the differential signal circuit is located; and the first ground circuit is provided between the first signal circuit and the differential signal circuit; And / or, a first power supply circuit is provided in the signal layer where the differential signal circuit is located; The first ground line is provided between the first power line and the differential signal line.

10. The substrate structure according to claim 8, characterized in that: A ground via is provided in the first grounding circuit; The first grounding line is arranged on the top layer and / or the bottom layer of the substrate structure, and the ground via passes through the first grounding line and the first reference plane in a direction perpendicular to the substrate structure; The ground vias are electrically connected to the first ground line and the first reference plane respectively; Alternatively, the first grounding circuit is arranged in the middle layer of the substrate structure, and in a direction perpendicular to the substrate structure, the ground via passes through the first grounding circuit, the first reference plane and the second reference plane; The ground via is electrically connected to the first ground line, the first reference plane, and the second reference plane respectively.

11. The substrate structure according to claim 1, characterized in that: The first area is located on the surface layer of the substrate, the differential signal line located in the first area is provided with ink, and the differential signal line located in the second area is not provided with ink.

12. The substrate structure according to claim 2, characterized in that: An impedance formed between the differential signal line and the first reference plane in the first region and an impedance formed between the differential signal line and the first reference plane in the second region are within the same impedance range.

13. The substrate structure according to claim 12, characterized in that: The differential signal line is arranged on a top layer of the substrate structure, and the first reference plane is a ground layer adjacent to the top layer; Alternatively, the differential signal line is provided on the bottom layer of the substrate structure, and the first reference plane is a ground layer adjacent to the bottom layer; Alternatively, the differential signal line is arranged on a middle layer of the substrate structure, and the first reference plane includes a proximal ground layer and a distal ground layer adjacent to the middle layer.

14. The substrate structure according to claim 2, characterized in that: An impedance formed between the differential signal line and the first reference plane in the first region and an impedance formed between the differential signal line and the second reference plane in the second region are within the same impedance range.

15. The substrate structure according to claim 14, characterized in that: The differential signal line is arranged on the top layer of the substrate structure, the first reference plane is a ground layer adjacent to the top layer, the projection area of ​​the differential signal line on the adjacent ground layer in the second region is hollowed out, the second reference plane is a ground plane of a target layer, the target layer is an internal signal layer adjacent to the ground layer, and the ground plane of the target layer is obtained by copper-cladding the projection area of ​​the differential signal line on the target layer; Alternatively, the differential signal line is arranged on the bottom layer of the substrate structure, the first reference plane is a ground layer adjacent to the bottom layer, the projection area of ​​the differential signal line on the adjacent ground layer in the second region is hollowed out, the second reference plane is a ground plane of a target layer, the target layer is an internal signal layer adjacent to the ground layer, and the ground plane of the target layer is obtained by copper-cladding the projection area of ​​the differential signal line on the target layer; Alternatively, the differential signal line is arranged in the middle layer of the substrate structure, the first reference plane includes a proximal ground layer and a distal ground layer adjacent to the middle layer, the projection area of ​​the differential signal line on the proximal ground layer in the second area is hollowed out, the second reference plane includes a reference ground layer and a distal ground layer adjacent to the middle layer, and the reference ground layer is a ground layer adjacent to the proximal ground layer.

16. The substrate structure according to any one of claims 1 to 15, characterized in that: The line width of the differential signal line located in the first area and the line width of the differential signal line located in the second area transition in a gradual manner; Alternatively, the line width of the differential signal line located in the first area and the line width of the differential signal line located in the second area transition in an abrupt manner.

17. A communication device, characterized in that: Comprising the substrate structure as claimed in any one of claims 1 to 16.

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