Preparation method of charge trapping type memory with TiN-doped Si3N4 storage layer

Abstract

The invention relates to the technical field of semiconductors, and provides a preparation method of a charge trapping type memory with a TiN-doped Si3N4 storage layer. The preparation method comprises the following steps: S1, cleaning a substrate, and then depositing a tunneling layer on the surface of the substrate; s2, depositing m layers of Si3N4 films and p layers of TiN films on the surface of the tunneling layer, repeating the process for x times, and finally depositing n layers of Si3N4 films to obtain a TiN-doped Si3N4 storage layer; wherein 25 < = m < = 50, 25 < = n < = 50, p = 1, and 5 < = x < = 11; and S3, depositing a barrier layer on the surface of the storage layer, and then evaporating an Al electrode on the surface of the barrier layer. The storage layer Si3N4 film is doped with TiN, more charge traps are provided, the charge trap density of the storage layer is improved, compared with an undoped control group, the storage window is larger, the fatigue characteristic of the device is better, the retention performance is excellent, and the reliability of the charge trapping type memory is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer. Background Art

[0002] The development of digitalization and integrated circuits has greatly changed our lives. The emergence of mobile phones, computers and artificial intelligence has generated a large amount of data, which has promoted the development of various memories. As a non-volatile memory, flash memory occupies an important position in the market due to its high density, fast speed, durability and low cost. The transition of flash memory from 2D to 3D structure has greatly improved the storage density and broken the limit of semiconductor technology.

[0003] The core of 3D flash memory is charge trap memory. At present, the main storage unit of 3D NAND flash memory is charge trap memory, in which the storage layer material is Si3N4. However, the shallow trap energy level in Si3N4 causes the device reliability to decrease. Especially in the 3D structure, the charge stored in the shallow trap energy level in the storage layer is very easy to diffuse horizontally and vertically, resulting in reduced device reliability. Therefore, how to reduce the shallow trap energy level in Si3N4 and increase the number of charge traps in the storage layer is also the focus of current research. Atomic doping can change the band gap of materials, defect energy levels, etc., and has been widely used in the field of electronic devices. In charge trap memory, there are many studies on improving the storage performance of devices by atomic doping, including Hf, Al, Zr, Ti, Y and other elements. However, there is no good explanation on how to perform experimental operations for the doping of metal elements and the amount of metal elements to be doped. Therefore, how to perform atomic doping on the storage layer of charge trap memory by experimental means is a problem that needs to be studied and solved. Summary of the invention

[0004] In view of the above-mentioned problems of how to increase the charge trap density of the storage layer Si3N4 film, reduce the shallow trap energy level, and how to dope the metal elements. The present invention proposes a process method for doping the storage layer Si3N4 film with TiN using the PEALD process. The method of doping the TiN medium grown by NH3 plasma in the process of growing the Si3N4 film by the PEALD process, on the one hand, dopes the metal Ti element in the process of TiN doping the Si3N4 film, replaces the shallow trap energy level in the Si3N4 film, and at the same time increases the number of charge traps in the Si3N4 film, thereby improving the device storage window. The doping of the metal Ti element regulates the trap energy level of the Si3N4 film, introduces a deeper charge trap energy level, and improves the retention performance of the device. On the other hand, the interface of the Si3N4 film is treated with NH3 plasma during the TiN growth process, the boundary state density of the film is reduced, the shallow trap energy level of the interface is reduced, the quality of the Si3N4 film is improved, and the endurance and retention characteristics of the device are significantly improved. At the same time, the NH3 plasma treatment of the Si3N4 film effectively reduces the content of oxygen in the film and improves the quality of the nitride film. Finally, the dielectric film was subjected to high-temperature rapid thermal annealing treatment, which promoted the filling of shallow trap energy levels in the Si3N4 film by Ti elements and the fusion between TiN and Si3N4 dielectrics, repaired the lattice defects generated during the film deposition process, further improved the film quality, reduced leakage, and increased the breakdown voltage.

[0005] The technical solution of the present invention is implemented as follows: The present invention provides a method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer, comprising the following steps:

[0006] S1, cleaning the substrate, and then depositing a tunneling layer on the surface of the substrate;

[0007] S2, depositing m layers of Si3N4 film and p layers of TiN film on the surface of the tunneling layer, repeating this process x times, and finally depositing n layers of Si3N4 film to obtain a TiN-doped Si3N4 storage layer;

[0008] Where 25≤m≤50, 25≤n≤50, p=1, 5≤x≤11;

[0009] S3, depositing a barrier layer on the surface of the storage layer, and then evaporating an Al electrode on the surface of the barrier layer.

[0010] Specifically, the present invention adopts a doping method of first depositing m layers of Si3N4 film and p layers of TiN film, repeating x times and then depositing n layers of Si3N4 film, so that TiN and Si3N4 are fully mixed, so that the Ti element can better fill the shallow trap energy levels in the Si3N4 film, provide deep trap energy levels, increase the charge trap density of the storage layer, and further improve the storage window and retention characteristics of the storage device.

[0011] On the basis of the above technical solution, preferably, m=n=25, x=11, and p=1.

[0012] On the basis of the above technical scheme, preferably, during the deposition of the storage layer in step S2, the precursors for the growth of the Si3N4 film are bis(diethylamino)silane and N2 plasma, and the precursors for the growth of the TiN film are titanium tetrachloride and NH3 plasma; the growth temperature of the two films is 300°C-400°C, and the gas atmosphere and purge gas are argon.

[0013] Specifically, Si3N4 film is grown by nitriding silicon source with N2 plasma, and TiN film is grown by nitriding titanium source with NH3 plasma. Since the number of growth cycles of TiN film is small, on the one hand, the use of NH3 dangerous gas is reduced, and the preparation method is safer and more environmentally friendly; on the other hand, a small amount of NH3 plasma plays a nitriding role on the interface of Si3N4 film, reducing the interface state density, reducing the shallow trap energy level, and improving the film quality.

[0014] Based on the above technical solution, preferably, in step S3, the device on which the three dielectric films of the tunneling layer, the storage layer and the barrier layer are deposited is annealed and then an Al electrode is evaporated, and the annealing temperature is 750° C.-850° C. and the time is 60-90 s.

[0015] On the basis of the above technical solution, preferably, in step S3, the device after the Al electrode is evaporated is annealed in an annealing furnace at 250° C.-350° C. for 15-25 min.

[0016] On the basis of the above technical solution, preferably, the materials of the tunneling layer and the barrier layer are the same or different, and the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

[0017] On the basis of the above technical solution, preferably, the deposition temperature of the tunnel layer and the barrier layer is 100°C-300°C.

[0018] Based on the above technical solution, preferably, the thickness of the tunneling layer is 2-10 nm.

[0019] Based on the above technical solution, preferably, the thickness of the storage layer is 5-20 nm.

[0020] Based on the above technical solution, preferably, the thickness of the barrier layer is 10-30 nm.

[0021] The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer of the present invention has the following beneficial effects compared with the prior art:

[0022] (1) The storage layer material of the conventional charge trapping memory is Si3N4, while the present invention brings the following benefits by doping TiN into the storage layer Si3N4 film:

[0023] ①TiN doping provides more charge traps for Si3N4 film, increases the charge trap density of the storage layer, and thus increases the device storage window. And as the amount of TiN dielectric doping in the storage layer Si3N4 film increases, the device storage window increases significantly.

[0024] ②In the process of TiN doping Si3N4 film, the metal Ti element provides a deeper trap energy level, replacing the shallow trap energy level in the Si3N4 film. Therefore, the doping of the metal Ti element regulates the trap energy level of the Si3N4 film, so that the charge in the storage layer is better captured by the deep trap energy level, less likely to leak, and improves the retention characteristics of the storage device. At the same time, in the TiN doping process, the NH3 plasma used in TiN growth has a nitriding effect on the interface of the Si3N4 film, reducing the interface state density of the film, reducing the interface shallow trap energy level, and improving the film quality and voltage resistance operation capability. Therefore, by using TiN doped Si3N4 film as a storage layer, the fatigue characteristics and retention characteristics of the device are improved.

[0025] ③ In the process of using N2 plasma to grow Si3N4 film in the PEALD process, a small amount of NH3 plasma is used to grow TiN doping step, which can significantly reduce the oxide component in the Si3N4 film grown by the PEALD process using N2 plasma and increase the proportion of Si-N content.

[0026] (2) The TiN-doped Si3N4 storage layer film of the present invention is grown at 300°C using the PEALD process, and the growth temperature is relatively low. The precursors for the growth of the Si3N4 film are bis(diethylamino)silane and N2 plasma. These two precursors do not contain dangerous and harmful elements such as Cl and NH3, and the growth is safe and environmentally friendly. The precursors for the growth of the TiN film are titanium tetrachloride and NH3 plasma. Since the number of TiN growth cycles is small, the environmental pollution is small. Therefore, the growth process of the storage layer of the device of the present invention is safer and more environmentally friendly.

[0027] (3) The functional layer (tunneling layer-storage layer-barrier layer) films of the charge trapping memory of the present invention are all grown using the ALD process. The device can complete the growth and preparation of all films on the same device, avoiding the contamination of the interface caused by the device during the transfer process between different devices. This is beneficial to improving the quality of the film and further improving the performance of the prepared device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 The manufacturing process flow of the charge trapping memory of the present invention is shown in FIG.

[0030] Figure 2 It is a schematic diagram of the thin film structure of TiN-doped Si3N4 storage layer;

[0031] Figure 3 Schematic diagram of the effect of TiN-doped Si3N4 storage layer on the device storage window, (a) is a storage layer without TiN doping, (b) is a storage layer doped with 5 cycles of TiN, (c) is a storage layer doped with 9 cycles of TiN, and (d) is a storage layer doped with 11 cycles of TiN;

[0032] Figure 4 Comparison of storage window sizes of devices with undoped TiN and storage layers doped with 5, 9, and 11 cycles of TiN;

[0033] Figure 5 Schematic diagram of the effect of TiN-doped Si3N4 storage layer on device fatigue characteristics, (a) is a storage layer without TiN doping, (b) is a storage layer doped with 5 cycles of TiN, (c) is a storage layer doped with 9 cycles of TiN, and (d) is a storage layer doped with 11 cycles of TiN;

[0034] Figure 6 Schematic diagram of the effect of TiN-doped Si3N4 storage layer on device retention characteristics, (a) is a storage layer without TiN doping, (b) is a storage layer doped with 5 cycles of TiN, (c) is a storage layer doped with 9 cycles of TiN, and (d) is a storage layer doped with 11 cycles of TiN;

[0035] Figure 7 Schematic diagram of XPS test results of storage layer Si3N4 and 9-cycle TiN film doped with TiN. (a)-(c) are N 1s 、Si 2p , O 1s Peak spectra, (d)-(f) are N of 300-cycle Si3N4-doped 9-cycle TiN films 1s 、Si 2p 、Ti 2p Peak spectrum. DETAILED DESCRIPTION

[0036] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] Example 1

[0038] The method for preparing a charge trapping memory of the TiN-doped Si3N4 storage layer comprises the following steps:

[0039] S1, substrate cleaning:

[0040] The present invention adopts a p-Si substrate with a resistivity of 1-10Ω·cm. The Si wafer is cleaned by a standard RCA cleaning process, and the purpose is to remove organic and inorganic impurities on the surface of the Si wafer and obtain a clean surface. The cleaning method is: ultrasonically oscillate and clean with acetone and anhydrous ethanol in sequence. After being rinsed with deionized water, the wafer is placed in a solution of NH4OH (mass fraction is 29%): H2O2 (mass fraction is 30%): H2O=1:1:5 (v / v), boiled at 70°C for 10 minutes, and then repeatedly rinsed with deionized water for multiple times. Then, the silicon wafer is placed in a solution of HCl (mass fraction is 37%): H2O2 (mass fraction is 30%): H2O=1:1:6 (v / v), boiled at 75°C for 10 minutes, and then repeatedly rinsed with deionized water, and then the silicon wafer that has been boiled twice is placed in a HF solution diluted to 5% v / v (HF: H2O=10:70) and soaked for 2 minutes to remove the natural oxide layer on the surface of the silicon wafer. Finally, rinse repeatedly with deionized water to remove the HF solution remaining on the surface of the Si wafer, and then use N2 to blow dry the Si wafer.

[0041] S2, ALD deposition of tunneling layer Al2O3 film:

[0042] The Al2O3 film was grown using a thermal atomic layer deposition device (TALD). The cleaned Si substrate was placed in the TALD chamber to grow a 3nm Al2O3 film. The tunneling layer material was Al2O3, the Al2O3 growth temperature was 200℃, and the growth precursors were trimethylaluminum (TMA) and water (H2O).

[0043] The deposition sequence for growing a cycle of Al2O3 film is TMA-N2-H2O-N2, and the corresponding time is 0.02s-15s-0.015s-15s. The thickness of Al2O3 growth in one cycle is 0.1nm, so a 3nm Al2O3 tunneling layer film requires 30 cycles of ALD growth.

[0044] S3, PEALD deposition of storage layer Si3N4 (TiN) film:

[0045] The Si3N4 film was grown using a plasma enhanced atomic layer deposition device (PEALD). The Si substrate with the Al2O3 tunneling layer film grown was placed in the PEALD chamber to grow a 6nm Si3N4 film. The Si3N4 growth temperature was 300℃, and the precursors were bis(diethylamino)silane (BDEAS) and N2 plasma (gas flow rate 50sccm, power 200W).

[0046] The deposition sequence for growing a cycle of Si3N4 film is BDEAS-Ar-N2 Plasma-Ar, and the time is 0.2s-15s-15s-15s. The thickness of Si3N4 growth in one cycle is 0.02nm, so a 6nm Si3N4 storage layer film requires 300 cycles of ALD growth.

[0047] The TiN film growth temperature is 300°C, the precursor is titanium tetrachloride (TiCl4), NH3 plasma (gas flow rate 10 sccm, power 200 W). The deposition sequence of growing a cycle of TiN film is TiCl4-Ar-NH3Plasma-Ar, and the time is 0.1s-30s-10s-30s.

[0048] The storage layer Si3N4 (TiN) film structure is as follows Figure 2 As shown, it is prepared by growing 300 cycles of Si3N4 film and uniformly doping it with x cycles of TiN film. The deposition sequence of the storage layer Si3N4 (TiN) film is [(BDEAS-Ar-Plasma N2-Ar)×m-(TiCl4-Ar-Plasma NH3-Ar)×p]×x-(BDEAS-Ar-Plasma N2-Ar)×n. The time is [(0.2s-15s-15s-15s)×m-(0.1s-30s-10s-30s)×p]×x-(0.2s-15s-15s-15s)×n.

[0049] In this embodiment, 5 cycles of TiN film are doped during the growth of 300 cycles of Si3N4 film, so m=50, p=1, x=5, and n=50.

[0050] S4, ALD deposition barrier layer Al2O3 film:

[0051] The Al2O3 film was grown using a thermal atomic layer deposition device (TALD). The Si substrate on which the Al2O3 tunneling layer film and Si3N4 (TiN) storage layer film were grown was placed in the TALD chamber to grow a 13nm Al2O3 film. Al2O3 was selected as the barrier layer material. The Al2O3 growth temperature was 200℃, and the growth precursors were trimethylaluminum (TMA) and water (H2O).

[0052] The deposition sequence for growing a cycle of Al2O3 film is TMA-N2-H2O-N2, and the time is 0.02s-15s-0.015s-15s. The thickness of Al2O3 growth in one cycle is 0.1nm, so 130 cycles of ALD growth are required for a 13nm Al2O3 tunneling layer film.

[0053] S5, rapid thermal annealing of dielectric film:

[0054] The device with three dielectric films of tunneling layer, storage layer and barrier layer deposited by ALD was placed in a rapid thermal annealing furnace, annealed at 800°C in N2 atmosphere for 60s, and then naturally cooled to room temperature and taken out.

[0055] S6, Metal Electrode Preparation:

[0056] There are no special requirements for the preparation of metal electrodes. The present invention only provides a circular Al electrode evaporation method with a diameter of 100um and a thickness of 100nm. First, AZ5214 photoresist is spin-coated on the surface of the device at 4000r / 60s, and baked at 110°C for 10min. Then, a circular electrode mask with a diameter of 100um is selected, exposed for 5.5s under a photolithography machine, and developed for 70s. Finally, deionized water is used to remove excess developer, and a 100nm Al electrode is evaporated on the device after photolithography in a thermal evaporator. After the evaporation is completed, acetone is used to remove the excess photoresist. Finally, the device with the Al electrode evaporated is annealed in an annealing furnace at 300°C and N2 atmosphere for 20min to improve the contact characteristics between the metal Al electrode and the medium.

[0057] Example 2

[0058] The difference between this embodiment and embodiment 1 is that 9 cycles of TiN film are added during the growth of 300 cycles of Si3N4 film, m=30, p=1, x=9, n=30. The rest of the contents are the same as embodiment 1.

[0059] Example 3

[0060] The difference between this embodiment and embodiment 1 is that 11 cycles of TiN film are added during the growth of 300 cycles of Si3N4 film, m=25, p=1, x=11, n=25. The rest of the contents are the same as embodiment 1.

[0061] In some embodiments of the present invention, the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

[0062] In some embodiments of the present invention, the thickness of the tunneling layer is 2-10 nm.

[0063] In some embodiments of the present invention, the thickness of the storage layer is 5-20 nm.

[0064] In some embodiments of the present invention, the thickness of the barrier layer is 10-30 nm.

[0065] As the thickness of the tunneling layer increases, the fatigue characteristics of the device will improve; as the thickness of the storage layer increases, the storage window of the device becomes larger; as the thickness of the barrier layer increases, the retention characteristics of the device become better. However, as the thickness of each layer increases, the operating voltage required for the device increases, and the programming / erasing speed slows down.

[0066] In some embodiments of the present invention, the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

[0067] When SiO2 is used as a barrier layer / tunneling layer material, it can improve the retention / fatigue characteristics of the device due to its large bandgap. High-k materials such as Al2O3\HfO2\ZrO2 have a large dielectric constant and when used as tunneling / barrier layers, they can be beneficial to device size scaling and improve programming / erasing speeds.

[0068] In some embodiments of the present invention, the growth temperature of the Si3N4 film and the TiN film is 300°C-400°C, and the deposition temperature of the tunneling layer and the barrier layer is 100°C-300°C.

[0069] The deposition temperature has little effect on the device storage performance, but mainly affects the film growth rate. As the deposition temperature increases, the film deposition rate will increase and finally saturate.

[0070] In some embodiments of the present invention, a device having three dielectric films of a tunneling layer, a storage layer and a barrier layer is annealed and then an Al electrode is evaporated. The annealing temperature is 750° C.-850° C. and the time is 60-90 seconds.

[0071] In some embodiments of the present invention, the device after the Al electrode is evaporated is annealed in an annealing furnace at 250° C.-350° C. for 15-25 min.

[0072] For thin film dielectric annealing, in this example, a higher annealing temperature and a suitable annealing time are conducive to the mixing of TiN and Si3N4 and the doping of Ti elements, reducing lattice damage during thin film deposition. However, too high an annealing temperature or too long an annealing time will damage the film, so it is necessary to select a suitable annealing temperature and time.

[0073] For electrode annealing, in this example, a suitable annealing temperature and time (such as 300° C., 20 min) are beneficial to improving the contact characteristics between the Al electrode and the dielectric. However, if the annealing temperature is too high or the time is too long, the interface contact characteristics will be damaged.

[0074] Comparative Example 1

[0075] The storage layer without TiN film doping only grows 300 cycles of Si3N4 film, then m=300, x=1, p=n=0. The rest of the contents are the same as in Example 1.

[0076] 1. The influence of TiN doped storage layer on the device storage window size

[0077] The storage windows of the charge trapping memory prepared in the embodiment and the comparative example at the operating voltages of ±10V, ±12V, and ±15V are respectively tested. Figure 3 .

[0078] like Figure 3 As shown, when the storage layer Si3N4 film is not doped with TiN dielectric (see Figure 3 a), the device storage window is the smallest, as the storage layer Si3N4 thin film TiN dielectric doping amount increases (see Figure 3 b-3d), the device storage window increases significantly. Figure 4 In the figure, the increase in the amount of TiN dielectric doping makes the slope of the device storage window change with the operating voltage larger, which is conducive to realizing the multi-value storage function of the device. Under different operating voltages, the number of charges stored in the storage layer is different. Therefore, through the above storage window comparison, it can be seen that doping Si3N4 film with TiN dielectric can increase the charge trap density of the storage layer, thereby increasing the storage window size of the device.

[0079] 2. Effect of TiN-doped storage layer on device fatigue characteristics

[0080] A +10V_1s / -10V_1s periodic rectangular pulse was applied to the device, and the device flat band voltage offset was tested after 1, 10, 100, 1000, and 5000 pulses, respectively, to obtain the device fatigue performance. Figure 5 .

[0081] from Figure 5 It can be seen that the fatigue performance of the device without TiN dielectric doping in the storage layer Si3N4 film is poor (see Figure 5a), after 1000 rectangular pulse operations, the flat band voltage shifts significantly and the storage window is severely reduced. As the amount of TiN dielectric doping increases, the device fatigue performance improves (see Figure 5 b-5d). Especially when the Si3N4 film was doped with TiN dielectric for 11 cycles, after the device was operated with 5000 rectangular pulses, the flat band voltage did not shift significantly compared with the initial value, and the storage window hardly changed (see Figure 5 d).

[0082] Therefore, through the above fatigue characteristics analysis, the Si3N4 film grown using N2 plasma has poor quality, more interface states, and poor film withstand voltage. After multiple pulse voltage operations, the film is damaged. However, the fatigue characteristics of the Si3N4 film doped with TiN dielectric become better, and as the doping amount increases, the fatigue characteristics become better. This is because during the TiN dielectric doping process, the NH3 plasma used in the growth of the TiN film nitridates the interface of the Si3N4 film to a certain extent, reducing the interface state density, improving the quality of the Si3N4 film, and further improving the film's withstand voltage, so that it can withstand more voltage operations without damage. Therefore, in the present invention, the quality of the storage layer Si3N4 film and the fatigue characteristics of the device as a whole are improved through the treatment of NH3 plasma during the TiN film doping process.

[0083] 3. Effect of TiN-doped storage layer on device retention characteristics

[0084] The retention characteristics of the charge trapping memory prepared in the embodiment and the comparative example were tested respectively. The testing method was as follows: pulse voltages of +10V_1s and -10V_1s were applied to the device respectively, and then the CV curves were tested after 1s, 10s, 100s, 500s, 1000s, 1500s, and 2000s respectively to extract the flat band voltage. The flat band voltage of the device after programming / erasing was plotted over time, and then extrapolated for 10 years to obtain the device retention performance. The results are shown in Figure 6 .

[0085] Depend on Figure 6 It can be seen that the charge trap energy level of Si3N4 film grown by using BDEAS silicon source and N2 plasma is low and the charge retention ability is poor. The charge trapping memory prepared by using it as the storage layer has poor retention characteristics (see Figure 6 a). The stored charge loses quickly over time. After 10 years, the stored charge is completely leaked, which cannot meet the requirements of memory. However, after the storage layer Si3N4 film is doped with TiN dielectric, the device retention performance is greatly improved (see Figure 6 b-6d). Especially when the TiN doping number reaches 11 cycles, the charge loss is only 1.17% after 10 years (see Figure 6d), greatly improving the reliability of the device.

[0086] Analysis of the reasons:

[0087] On the one hand, this is because the metallic Ti element provides charge traps with deeper energy levels during the TiN doping process, and the Ti element replaces the shallow trap energy levels in the original Si3N4 film, reducing the number of these unstable trap energy levels and better maintaining the charge captured by the storage layer.

[0088] On the other hand, the NH3 plasma in the TiN doping process nitridates the interface of the Si3N4 film, reducing the interface state density and the shallow trap energy level at the interface of the Si3N4 film, making it less likely for the captured charge to leak. In summary, TiN doping of Si3N4 film grown by BDEAS silicon source and N2 plasma can significantly improve the device retention characteristics, which further improves the reliability of the memory and has a great impact and significance on the actual production of the device.

[0089] 4. XPS test of storage layer Si3N4 and doped TiN film

[0090] 300 cycles Si3N4 and 300 cycles Si3N4+9 cycles TiN films were deposited on p-Si substrates, and annealed at 800℃ for 60s. Finally, their XPS spectra were tested. The results are shown in Figure 7 .

[0091] Figure 7 The XPS test results confirm that the TiN doping method provided by this patent successfully introduces the metallic Ti element into the Si3N4 film. Figure 7 Figures b and 7e 2p Peak comparison shows that the Si element in the Si3N4 film without TiN doping mainly forms Si-N bonds, with obvious O 1s The Si element in the Si3N4 film doped with TiN mainly forms Si-N bonds, with a content of 94.71%, and no obvious Si-O bond peak appears.

[0092] Therefore, the method of TiN doping Si3N4 film proposed in this patent effectively reduces the oxygen content in Si3N4 film and improves its ability to capture charge as a storage layer, which can also be reflected in the excellent storage performance of the prepared device. Figure 7 fTi 2pPeak spectrum shows that the TiN doping method proposed in this patent successfully introduces metal Ti element into Si3N4 film, achieving the purpose of metal doping to regulate energy level. At the same time, due to the incorporation of metal Ti, more traps and deeper trap energy levels are provided, which explains Figure 3 , 4 The reasons why TiN doping improves the device storage window and retention characteristics in 6.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer, characterized in that: The following steps are involved: S1, cleaning the substrate, and then depositing a tunneling layer on the surface of the substrate; S2, depositing m layers of Si3N4 film and p layers of TiN film on the surface of the tunneling layer, repeating this process x times, and finally depositing n layers of Si3N4 film to obtain a TiN-doped Si3N4 storage layer; Where 25≤m≤50, 25≤n≤50, p=1, 5≤x≤11; S3, depositing a barrier layer on the surface of the storage layer, and then evaporating an Al electrode on the surface of the barrier layer.

2. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer according to claim 1, characterized in that: Said m=n=25, x=11, p=1.

3. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer according to claim 1, characterized in that: During the deposition of the storage layer in step S2, the precursors for the growth of the Si3N4 film are bis(diethylamino)silane and N2 plasma, and the precursors for the growth of the TiN film are titanium tetrachloride and NH3 plasma; the growth temperature of the two films is 300°C-400°C, and the gas atmosphere and purge gas are argon.

4. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer according to claim 1, characterized in that: In step S3, the device on which the three dielectric films of the tunneling layer, the storage layer and the barrier layer are deposited is annealed and then an Al electrode is evaporated. The annealing temperature is 750° C.-850° C. and the time is 60-90 seconds.

5. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer as claimed in claim 4, characterized in that: In step S3, the device after the Al electrode is evaporated is annealed in an annealing furnace at 250° C.-350° C. for 15-25 minutes.

6. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer according to claim 1, characterized in that: The materials of the tunneling layer and the barrier layer are the same or different, and the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

7. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer as claimed in claim 6, characterized in that: The deposition temperature of the tunneling layer and the barrier layer is 100°C-300°C.

8. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer according to claim 1, characterized in that: The thickness of the tunneling layer is 2-10 nm.

9. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer according to claim 1, characterized in that: The storage layer has a thickness of 5-20 nm.

10. The method for preparing a charge trapping memory of a TiN-doped Si3N4 storage layer according to claim 1, characterized in that: The thickness of the barrier layer is 10-30 nm.

Images