Silicon carbide device, manufacturing method thereof and electronic device

Abstract

The silicon carbide device, its manufacturing method and electronic device disclosed in the present invention can improve the conduction capability, radiation resistance and reverse withstand voltage capability of the device. The silicon carbide device includes an n+ substrate with an offset angle less than 0.5°, and a first n-drift layer, a second n-type doped drift layer, a p-well layer and an n+ electrode layer arranged in sequence on the n+ substrate; a groove, which penetrates the n+ electrode layer, the p-well layer and the second n-type doped drift layer, and the groove includes a direction of [11 _ 20] crystal orientation of the first trench, and the orientation of [ _ 1100] A second groove in a crystal direction, the first groove and the second groove define a plurality of square cell regions; a p-protective layer, including a connecting portion, the connecting portion covers at least a portion of the side surface of the first groove on at least one side of the square cell region, and is blankly arranged on at least a portion of the side surface of the second groove on at least one side of the square cell region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a silicon carbide device, a manufacturing method thereof, and an electronic device. Background Art

[0002] As a semiconductor material with a wide bandgap, high breakdown field strength, high thermal conductivity, and mobility similar to that of silicon, silicon carbide has broad prospects in power electronics applications and is widely used in new energy vehicles, charging piles, photovoltaics and other fields. Summary of the invention

[0003] The present disclosure provides a silicon carbide device, a manufacturing method thereof, and an electronic device, which can improve the conduction capability, radiation resistance, and reverse voltage withstand capability of the silicon carbide device.

[0004] The silicon carbide device, its manufacturing method and electronic device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a silicon carbide device, comprising:

[0006] An n+ substrate, wherein the off-angle of the n+ substrate is less than 0.5°;

[0007] A first n-drift layer, located on one side of the n+ substrate;

[0008] a second n-type doped drift layer, located on a side of the first n- drift layer away from the n+ substrate;

[0009] A p-well layer, located on a side of the second n-type doped drift layer away from the first n-drift layer;

[0010] An n+ electrode layer is located on a side of the p-well layer away from the second n-type doped drift layer;

[0011] A groove, which penetrates the n+ electrode layer, the p-well layer and the second n-type doped drift layer, and the groove includes a direction of [11 _ 20] crystal orientation of the first trench, and the orientation of [ _ 1100] a second trench in a crystal direction, wherein the first trench and the second trench define a plurality of square cell regions;

[0012] The p-protection layer includes a connection portion, which covers at least a portion of the side surface of the first groove on at least one side of the square cell region and is blankly disposed on at least a portion of the side surface of the second groove on at least one side of the square cell region.

[0013] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting portion covers the side surface of the first groove on one side of the square cell region.

[0014] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting portion covers the side surface of the first groove on the other side of the square cell region, or the connecting portion is left blank on the side surface of the first groove on the other side of the square cell region.

[0015] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiments of the present disclosure, the square cell region includes an edge region adjacent to the first groove and a middle region located between the edge regions, and the connecting portion is blankly arranged on the side of the second groove on one side of the middle region.

[0016] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiments of the present disclosure, the connecting portion is left blank on the side of the second trench on the other side of the middle region, or the connecting portion covers the side of the second trench on the other side of the middle region.

[0017] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting portion covers the side surfaces of the second trench on both sides of the edge region.

[0018] In some embodiments, in the silicon carbide device provided in the embodiments of the present disclosure, the bottom surface of the groove includes a first bottom surface connected to the side surface of the groove, and a second bottom surface located between the first bottom surfaces; the side surface of the groove includes a first side surface covered by the connecting portion, and a second side surface not covered by the connecting portion;

[0019] The p-protective layer also includes a bottom located in the groove, the bottom having a first thickness at the first bottom surface connected to the second side surface, the bottom having a second thickness at the first bottom surface connected to the first side surface, and the bottom having a third thickness at the second bottom surface, the first thickness is less than the second thickness, and the second thickness is greater than or equal to the third thickness.

[0020] In some embodiments, in the silicon carbide device provided in the embodiments of the present disclosure, the side surface of the groove includes a first side surface covered by the connecting portion, and a second side surface not covered by the connecting portion, the square cell region includes an electrode contact region, and the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion connected to each other, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the electrode contact region;

[0021] The p-protective layer also includes a first terrace portion and a second terrace portion, the first terrace portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the first side surface, the second terrace portion at least covers the second n+ electrode portion on the side where the second side surface is located, and the thickness of the second terrace portion is less than or equal to the thickness of the first terrace portion.

[0022] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the second mesa portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the second side surface, and the thickness of the second mesa portion is less than the thickness of the first mesa portion.

[0023] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the thickness of the first n+ electrode portion adjacent to the second side surface is equal to the thickness of the second n+ electrode portion connected thereto.

[0024] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiments of the present disclosure, the second table portion covers the second n+ electrode portion on the side where the second side surface is located, and is left blank at the first n+ electrode portion adjacent to the second side surface, and the thickness of the second table portion is equal to the thickness of the first table portion.

[0025] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the thickness of the first n+ electrode portion adjacent to the second side surface is smaller than the thickness of the second n+ electrode portion connected thereto.

[0026] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiments of the present disclosure, the thickness of the first n+ electrode portion adjacent to the first side surface is equal to the thickness of the second n+ electrode portion connected thereto, and the thickness of the second n+ electrode portion on the side where the first side surface is located is equal to the thickness of the second n+ electrode portion on the side where the second side surface is located.

[0027] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiment of the present disclosure, the plurality of square cell regions are in [11 _ 20] crystal orientation and [ _ 1100] are arranged in an array in the crystal direction.

[0028] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiment of the present disclosure, the plurality of square cell regions are in [11 _ 20] crystal orientation and / or [ _ 1100] The crystals are arranged in a staggered manner.

[0029] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the n+ electrode layer is an n+ source layer or an n+ emitter layer.

[0030] On the other hand, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned silicon carbide device, comprising:

[0031] Providing an n+ substrate with an off-angle of less than 0.5°;

[0032] A first n-drift layer, a second n-type doped drift layer, a p-well layer and an n+ electrode layer are stacked in sequence, and a trench penetrating the n+ electrode layer, the p-well layer and the second n-type doped drift layer is formed by etching, wherein the trench includes a direction of [11 _ 20] crystal orientation of the first trench, and the orientation of [ _ 1100] a second trench in a crystal direction, wherein the first trench and the second trench define a plurality of square cell regions;

[0033] A p-protective layer is formed by epitaxial growth, wherein the p-protective layer includes a connecting portion, which covers at least a portion of the side surface of the first groove on at least one side of the square cell region and is blankly disposed on at least a portion of the side surface of the second groove on at least one side of the square cell region.

[0034] In some embodiments, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, a p-protective layer is formed by epitaxial growth, and the p-protective layer includes a connecting portion, and the connecting portion covers at least a portion of the side surface of the first groove on at least one side of the square cell area, and is blankly arranged on at least a portion of the side surface of the second groove on at least one side of the square cell area, specifically including:

[0035] Using silane, propane, hydrogen, hydrogen chloride and trimethylaluminum, epitaxially forming a p-protective layer extending from the first trench and the second trench to the side of the n+ electrode layer away from the p-well layer;

[0036] Depositing a hard mask on the p-protective layer, and performing resist coating, exposure, development, and etching processes on the hard mask so that the hard mask covers at least a portion of the side surface of the first trench on at least one side of the cell region, and forms an opening on at least a portion of the side surface of the second trench on at least one side of the cell region;

[0037] Under the shielding of the hard mask, the p-protective layer at the opening of the hard mask is removed by Cl2 thermal chemical etching or capacitively coupled plasma etching, so that the p-protective layer includes a connection portion covering at least a portion of the side surface of the first groove on at least one side of the cell area, and a blank connection portion is provided on at least a portion of the side surface of the second groove on at least one side of the cell area.

[0038] In some embodiments, in the above-mentioned manufacturing method provided by the embodiment of the present disclosure, the square cell region includes an edge region adjacent to the first groove and an intermediate region located between the edge regions, the intermediate region includes a first subregion adjacent to the second groove and a second subregion located between the first subregions, and the second subregion includes an electrode contact region; the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion located between the edge region, the first subregion, and the edge region and the electrode contact region, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the electrode contact region; the bottom surface of the groove includes a first bottom surface connected to the side surface of the groove, and a second bottom surface located between the first bottom surfaces;

[0039] The hard mask covers at least a portion of the side surface of the first trench on at least one side of the cell region, and forms an opening on at least a portion of the side surface of the second trench on at least one side of the cell region, including:

[0040] The hard mask at most covers the first trench, the edge region, the second trench between the edge regions, the second bottom surface of the second trench between the first sub-regions, and the second sub-regions, and forms an opening at least at the first bottom surface of the second trench between the first sub-regions and the first sub-regions;

[0041] The p-protection layer includes a connection portion covering at least a portion of the side surface of the first groove on at least one side of the square cell region and provided blank on at least a portion of the side surface of the second groove on at least one side of the square cell region, specifically including:

[0042] The p-protective layer includes a connecting portion, a bottom, a first table portion and a second table portion, wherein the connecting portion covers the side surfaces of the first groove on both sides of the edge area, and the side surfaces of the second groove on both sides of the edge area, and is blankly arranged on the side surfaces of the second groove on both sides of the first partition; the bottom covers the first bottom surface and the second bottom surface of the first groove, and covers the first bottom surface and the second bottom surface of the second groove, and the thickness of the bottom at the first bottom surface of the second groove between the first partitions is less than or equal to the thickness of the bottom outside the first bottom surface of the second groove between the first partitions; the first table portion covers the n+ electrode layer of the edge area, the second table portion covers at least the second n+ electrode portion of the first partition, the thickness of the second table portion is less than or equal to the thickness of the first table portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion.

[0043] In some embodiments, in the above manufacturing method provided by the embodiment of the present disclosure, the hard mask at most covers the first trench, the edge area, the second trench between the edge areas, the second bottom surface of the second trench between the first subareas, and the second subareas, and forms an opening at least at the first bottom surface of the second trench between the first subareas and the first subareas, specifically comprising:

[0044] The hard mask covers the first trench, the edge region, the second trench between the edge regions, and the second sub-region, and forms openings at the first sub-region, the first bottom surface of the second trench between the first sub-region, and the second bottom surface;

[0045] The thickness of the bottom at the first bottom surface of the second groove between the first partitions is less than or equal to the thickness of the bottom outside the first bottom surface of the second groove between the first partitions, specifically including:

[0046] The thickness of the bottom between the first partitions is smaller than the thickness of the bottom outside the first partitions;

[0047] The second mesa portion at least covers the second n+ electrode portion of the first partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including:

[0048] The second table portion covers the second n+ electrode portion of the first partition and is set blank at the first n+ electrode portion of the first partition. The thickness of the second table portion is equal to the thickness of the first table portion. The thickness of the first n+ electrode portion on the side where the second table portion is located is less than the thickness of the second n+ electrode portion.

[0049] In some embodiments, in the above manufacturing method provided by the embodiment of the present disclosure, the hard mask at most covers the first trench, the edge area, the second trench between the edge areas, the second bottom surface of the second trench between the first subareas, and the second subareas, and forms an opening at least at the first bottom surface of the second trench between the first subareas and the first subareas, specifically comprising:

[0050] The hard mask covers the first trench, the edge region, and the second trench between the edge regions, and forms openings in the first sub-region, the first bottom surface and the second bottom surface of the second trench between the first sub-regions, and the second sub-region;

[0051] The thickness of the bottom at the first bottom surface of the second groove between the first partitions is less than or equal to the thickness of the bottom outside the first bottom surface of the second groove between the first partitions, specifically including:

[0052] The thickness of the bottom between the first partitions is smaller than the thickness of the bottom outside the first partitions;

[0053] The second mesa portion at least covers the second n+ electrode portion of the first partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including:

[0054] The second mesa portion covers the first n+ electrode portion and the second n+ electrode portion of the first partition, the thickness of the second mesa portion is smaller than the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is equal to the thickness of the second n+ electrode portion.

[0055] On the other hand, an embodiment of the present disclosure provides an electronic device, including the above-mentioned silicon carbide device provided by an embodiment of the present disclosure.

[0056] The beneficial effects of the present disclosure are as follows:

[0057] The silicon carbide device, the manufacturing method thereof and the electronic device provided by the embodiments of the present disclosure include an n+ substrate, wherein the off-angle of the n+ substrate is less than 0.5°; a first n-drift layer, located on one side of the n+ substrate; a second n-type doped drift layer, located on the side of the first n-drift layer away from the n+ substrate; a p-well layer, located on the side of the second n-doped drift layer away from the first n-drift layer; an n+ electrode layer, located on the side of the p-well layer away from the second n-doped drift layer; a groove, penetrating the n+ electrode layer, the p-well layer and the second n-doped drift layer, the groove including a direction of [11 _ 20] crystal orientation of the first trench, and the orientation of [ _ 1100] A second groove in the crystal direction, the first groove and the second groove define a plurality of square cell regions; a p-protection layer, including a connecting portion, the connecting portion covers at least part of the side surface of the first groove on at least one side of the square cell region, and is blankly arranged on at least part of the side surface of the second groove on at least one side of the square cell region. In the present disclosure, the groove side surface without the connecting portion is used as the main conductive area, and the groove side surface covered by the connecting portion is used as the secondary conductive area, which can effectively improve the conduction capability, radiation resistance and reverse withstand voltage capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 A top view of a silicon carbide device provided in an embodiment of the present disclosure;

[0059] Figure 2 For along Figure 1 A cross-sectional view of the line I-I';

[0060] Figure 3 For along Figure 1 Another cross-sectional view of the line I-I';

[0061] Figure 4 For along Figure 1 Another cross-sectional view of the line I-I';

[0062] Figure 5 For along Figure 1 A cross-sectional view of the line II-II';

[0063] Figure 6 For along Figure 1 Another cross-sectional view of line II-II';

[0064] Figure 7 For along Figure 1 Another cross-sectional view of line II-II';

[0065] Figure 8 Another top view of a silicon carbide device provided in an embodiment of the present disclosure;

[0066] Fig. 9 A curve characterizing the radiation resistance characteristics of a silicon carbide device provided in an embodiment of the present disclosure;

[0067] Fig.10 A flow chart of a method for manufacturing a silicon carbide device provided in an embodiment of the present disclosure;

[0068] Fig.11 A schematic diagram of an opening structure of a hard mask provided in an embodiment of the present disclosure;

[0069] Fig.12 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0070] Fig.13 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0071] Fig.14 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0072] Fig.15 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0073] Fig.16 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0074] Fig.17 for Fig.11 and Fig.12 A cross-sectional view along line III-III' after removing the connecting portion at the opening;

[0075] Fig.18 For along Figures 11 to 16 Sectional view of line IV-IV';

[0076] Fig.19 for Fig.13 and Fig.14 A cross-sectional view along line V-V' after removing the connecting portion at the opening;

[0077] Fig. 20 for Fig.15 and Fig.16 A cross-sectional view along line VI-VI' after removing the connecting portion at the opening;

[0078] Fig.21 A schematic diagram of a structure of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0079] Fig. 22 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0080] Fig.23 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0081] Fig.24 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0082] Fig.25 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0083] Fig.26 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0084] Fig. 27 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0085] Fig.28 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0086] Fig.29 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0087] Fig.30 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0088] Fig.31 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0089] Fig.32 Another schematic diagram of the structure of the silicon carbide device during the manufacturing process provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in the drawings, the thickness of the layer, film, panel, area, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shape of the area shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes are not intended to illustrate the exact shape of the area, do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0091] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0092] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0093] In some embodiments, the gate oxide layer covering the trench in the silicon carbide device is subjected to a large electric field stress, which causes the gate oxide layer on the bottom surface of the trench to be easily broken down, resulting in reduced reliability of the silicon carbide device. In order to improve reliability, a protective layer can be added between the trench and the gate oxide layer, but the protective layer on the side of the trench affects the conduction ability of the silicon carbide device to a certain extent.

[0094] In order to improve the above technical problems, the present disclosure provides a silicon carbide device, such as Figures 1 to 7 As shown, it may include:

[0095] n+ substrate 101, the off-axis angle of n+ substrate 101 is less than 0.5°, and the off-axis angle is the angle between the normal direction of the wafer and the

[0001] crystal direction of silicon carbide during the process of cutting the wafer from the silicon carbide ingot. In the present disclosure, the off-axis angle of n+ substrate 101 is close to 0°, which can maximally suppress the difference between different trench crystal directions of silicon carbide devices when the p-protection layer 106 mentioned later is made by silicon carbide epitaxial backfilling, and the orientation is improved to [ _ 1100] Backfill symmetry of the connection portion on the trench side surface in the crystal direction.

[0096] The first n-drift layer 102 is located on one side of the n+ substrate 101 . In some embodiments, the first n-drift layer 102 may be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process.

[0097] The second n-type doped drift layer 103 is located on a side of the first n- drift layer 102 away from the n+ substrate 101; the second n-type doped drift layer 103 may be Figures 2 to 5 As shown, the first n-drift layer 101 is integrally arranged, for example, the doping concentration of both is 1e 14 / cm 3 ~1e 16 / cm 3Alternatively, the second n-type doped drift layer 103 may also be Figure 6 The n+ drift layer (high nitrogen doping layer) is shown to form a super junction structure and charge balance with the p-protection layer 106; optionally, the doping concentration of the first n-drift layer 101 is 1e 14 / cm 3 ~1e 16 / cm 3 , the second n-type doped drift layer 103 is 1e 16 / cm 3 ~5e 17 / cm 3 In some embodiments, the second n-type doped drift layer 103 may be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process.

[0098] The p-well layer 104 is located on a side of the second n-type doped drift layer 103 away from the first n-drift layer 102 . In some embodiments, the p-well layer 104 may be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process.

[0099] The n+ electrode layer 105 is located on the side of the p-well layer 104 away from the second n-type doped drift layer 103; in some embodiments, the n+ electrode layer 105 can be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process. Figures 2 to 6 The MOSFET device shown can also be Figure 7 In the IGBT device shown, the n+ electrode layer 105 may be an n+ source layer of a MOSFET device or an n+ emitter layer of an IGBT device.

[0100] The trench T penetrates the n+ electrode layer 105, the p-well layer 104 and the second n-type doped drift layer 103, and the trench T includes a direction of [11 _ 20] crystal orientation of the first trench T1, and the direction of [ _ 1100] The second trench T2 of the crystal direction, the first trench T1 and the second trench T2 define a plurality of square cell regions S, Figure 1 The schematic diagram shows 9 square cell areas S. In a specific implementation, the total number of square cell areas S may be less than 9 or greater than 9, and the present disclosure does not limit this. In some embodiments, a trench T may be formed by dry etching. The trench T may be a U-shaped trench. Considering the influence of process, measurement and other factors, the direction is [11 _ The first trench T1 in the crystal direction of 20] can be understood as the direction of the first trench T1 and [11 _ 20] The deviation of the crystal direction is within 0.2°, and the direction is [ _ The second trench T2 with a crystal orientation of 1100] can be understood as the direction of the second trench T2 and [_ 1100] The deviation of the crystal direction is within 0.2°.

[0101] The p-protective layer 106 includes a connecting portion pc, which covers at least a portion of the side surface of the first trench T1 on at least one side of the cell region S, and is provided blank on at least a portion of the side surface of the second trench T2 on at least one side of the cell region S. The inventors have found that when the connecting portion pc covers the sides of the first trench T1 on both sides of the cell region S and the sides of the second trench T2 on both sides of the cell region S at the same time, the thickness symmetry of the connecting portion pc on the side surface of the first trench T1 is good, but the thickness of the connecting portion pc on the side surface of the second trench T2 may be asymmetric with one side thick and the other side thin. The thicker connecting portion pc will affect the conduction capability of the device. The present disclosure can improve the conduction capability of the silicon carbide device by removing the connecting portion c on at least a portion of the side surface of the second trench T2 on at least one side of the cell region S. The present disclosure uses an n+ substrate 101 with an off-axis angle (off-axis) less than 0.5° to improve the conduction capability of the device. _ 1100] The backfill symmetry of the connection part pc on the side of the second trench T2 in the crystal direction, therefore, when etching to remove the connection parts pc on the two sides of the second trench T2, it can be ensured that the connection parts pc on both sides are etched away at the same time, to prevent the occurrence of unilateral over-etching and damage to the side wall of the trench, affecting the conduction capability of the device. And because the conduction capability of the silicon carbide device disclosed in the present invention is good, the thickness of the connection part pc does not need to be thin (for example, not limited to less than 40nm), thereby taking into account the reverse withstand voltage capability and radiation resistance of the silicon carbide device and reducing the process difficulty of the connection part pc. In addition, at voltage levels below 1200V, the specific on-resistance of the MOSFET silicon carbide device is in the range of about 3mΩ·cm 2 ~6mΩ·cm 2 The channel resistance accounts for a high proportion of the on-resistance, accounting for a large proportion of the conduction loss, contributing ~0.5mΩ·cm 2 The present invention uses the

[1120] and

[1100] crystal planes of silicon carbide to obtain a mobility 2 to 3 times higher than that of the

[0001] and

[0001] crystal planes, thereby effectively reducing the specific on-resistance of silicon carbide devices.

[0102] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figure 1 , Figure 2 and Figure 5As shown, the cell region S may include an edge region S1 adjacent to the first trench T1, and a middle region S2 located between the edge region S1, and the connection portion pc may cover the side surfaces of the first trench T1 on both sides of the cell region S, and cover the side surfaces of the second trench T2 on both sides of the edge region S1, and the connection portion pc is blankly disposed on the side surfaces of the second trench T2 on both sides of the middle region S2. By removing the connection portion pc on the side surfaces of the second trench T2 on both sides of the middle region S2 and retaining the connection portion pc on the side surfaces of the second trench T2 on both sides of the edge region S1, in the process of removing the connection portion pc on the side surfaces of the second trench T2 on both sides of the middle region S2, the error etching of the connection portion pc on the side surfaces of the first trench T1 at the corner of the cell region S caused by factors such as process errors can be avoided.

[0103] It should be understood that, in some embodiments, the connection portion pc may also only cover the side of the first trench T1 on one side of the cell region S, and be blank on the side of the first trench T1 on the other side of the cell region S. The connection portion pc may also be blank on the side of the second trench T2 on one side of the middle region S2, and cover the side of the second trench T1 on the other side of the middle region S2, and the side of the second trench T2 on both sides of the edge region S1. Therefore, in the four sides of a cell region S of the present disclosure, at most one side of the upper and lower sides can be conductive, and at least one side of the left and right sides can be conductive, so that while improving the conductive capability of the silicon carbide device, the gate oxide reliability and radiation resistance of the silicon carbide device can be taken into account.

[0104] In some embodiments, Figure 3 As shown, in the process of etching the connecting portion pc on the side of the second trench T2 on both sides of the middle area S2, the present disclosure may simultaneously etch off a certain thickness of the bottom pb on the first bottom surface b1, but has no etching effect on the bottom pb on the second bottom surface b2. Therefore, the bottom pb in the second trench T2 is raised in the middle and low on both sides. In other words, in the second trench T2, the thickness h3 of the bottom pb at the second bottom surface b2 is greater than its thickness h1 at the first bottom surface b1. In other embodiments, such as Figure 2 and Figure 4 As shown, in the process of etching the connecting portion pc on the side of the second trench T2 on both sides of the middle area S2, the present disclosure may simultaneously etch away a certain thickness of the bottom pb on the first bottom surface b1 and the second bottom surface b2. Therefore, in the second trench T2, the thickness h3 of the bottom pb at the second bottom surface b2 is equal to the thickness h1 of the bottom pb at the first bottom surface b1. In other embodiments, such as Figure 5 As shown, the present disclosure does not etch the connection portion pc on the side of the first trench T1 , so the thickness h2 of the bottom pb of the first trench T1 at the first bottom surface b1 may be equal to the thickness h3 thereof at the second bottom surface b2 . Figure 5 The thickness h3 of the bottom pb at the second bottom surface b2 in the first trench T1 is greater than Figure 2 , Figure 4 The bottom pb has a thickness h3 at the second bottom surface b2 in the first trench T1, and Figure 5 The thickness h3 of the bottom pb at the second bottom surface b2 in the first trench T1 is equal to Figure 3 The bottom portion pb is shown to have a thickness h3 at the second bottom surface b2 in the first trench T1.

[0105] Based on this, in some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figures 2 to 5 As shown, the bottom surface b of the groove T includes a first bottom surface b1 connected to the side surface of the groove T, and a second bottom surface b2 located between the first bottom surface b1, and the side surface of the groove T includes a first side surface w1 covering the connection portion pc, and a second side surface w2 not covering the connection portion pc; the p-protection layer 106 may also include a bottom pb located in the groove T, the bottom pb has a first thickness h1 at the first bottom surface b1 connected to the second side surface w2 of the groove T not covering the connection portion pc, the bottom pb has a second thickness h2 at the first bottom surface b1 connected to the first side surface w1 of the groove T covering the connection portion pc, and the bottom pb has a third thickness h3 at the second bottom surface b2, the first thickness h1 is less than the second thickness h2, and the second thickness h2 is greater than or equal to the third thickness h3.

[0106] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figure 1 , Figure 2 and Figure 5 As shown, the second partition S22 includes an electrode contact region ECT, the n+ electrode layer 105 includes a first n+ electrode portion n1 and a second n+ electrode portion n2 connected to each other, the first n+ electrode portion n2 is adjacent to the trench T, and the second n+ electrode portion n2 is located between the first n+ electrode portion n1 and the electrode contact region ECT, and optionally, the first n+ electrode portion n1 and the second n+ electrode portion n2 are arranged between the edge region S1, the first partition S21, and the edge region S1 and the electrode contact region ECT. The p-protection layer 106 may also include a first mesa portion pm1 and a second mesa portion pm2, the first mesa portion pm1 covers the first n+ electrode portion n1 and the second n+ electrode portion n2 adjacent to the first side w1, and the second mesa portion pm2 covers the first n+ electrode portion n1 and the second n+ electrode portion n2 adjacent to the second side w2.

[0107] In some embodiments, during the process of etching away the connection portion pc on the second side w2, a portion of the second terrace portion pm2 may be etched away, while the connection portion pc on the first side w1 is not etched, so the thickness of the first terrace portion pm1 will not be affected by the etching of the connection portion pc. Figure 2 and Figure 5As shown, the thickness h4 of the first platform portion pm1 can be greater than the thickness h5 of the second platform portion pm2; and thanks to the protection of the first platform portion pm1 and the second platform portion pm2, the thickness of the n+ electrode layer 105 is protected from the etching effect of removing the connecting portion pc on the first side w1, which means that the thickness h6 of the first n+ electrode portion n1 and the thickness h7 of the second n+ electrode portion n2 can be equal.

[0108] In some embodiments, during the process of etching away the connection portion pc on the second side surface w2, the edge of the second terrace portion pm2 close to the second side surface w2 may be etched away, but the thickness of the remaining portion of the second terrace portion pm2 remains unchanged, while the connection portion pc on the first side surface w1 is not etched, so the thickness of the first terrace portion pm1 will not be affected by the etching of the connection portion pc. Figures 3 to 5 As shown, the first table portion pm1 can cover the first n+ electrode portion n1 and the second n+ electrode portion n2 adjacent to the first side w1, the second table portion pm2 covers the second n+ electrode portion n2 connected to the first n+ electrode portion n1 adjacent to the second side w2, and is left blank at the first n+ electrode portion n1 adjacent to the second side w2, and the thickness h5 of the second table portion pm2 is equal to the thickness h4 of the first table portion pm1; thanks to the protection of the first table portion pm1 and the second table portion pm2, the thickness h6 of the first n+ electrode portion n1 on the side where the first side w1 is located, the thickness h7 of the second n+ electrode portion n2, and the thickness h7 of the second n+ electrode portion n2 on the side where the second side w2 is located will not be affected by the etching of removing the connecting portion pc on the first side w1, which means that the thickness h6 of the first n+ electrode portion n1 on the side where the first side w1 is located, the thickness h7 of the second n+ electrode portion n2, and the thickness h7 of the second n+ electrode portion n2 on the side where the second side w2 is located can be equal and greater than the thickness h6 of the first n+ electrode portion n1 on the side where the second side w2 is located.

[0109] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figure 1 As shown, multiple square cell regions S can be [11 _ 20] crystal orientation and [ _ 1100] are arranged in an array in the crystal direction. Or Figure 8 As shown, multiple square cell regions S can also be [11 _ 20] crystal orientation and / or [ _ 1100] The first trench T1 and the second trench T2 are staggered in the crystal direction to reduce the electric field concentration at the intersection center of the first trench T1 and the second trench T2.

[0110] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figures 1 to 6As shown, it may also include a gate oxide layer 107, a gate 108 (for example, the gate 108 is made of polysilicon), a dielectric layer 109, a first metal layer 110, a p+ structure 111, a second metal layer 112 and an n-buffer layer 113; wherein the gate 108 and the first metal layer 110 are passivated and isolated by the dielectric layer 109, the dielectric layer 109, the gate oxide layer 107, and the p-protection layer 106 include contact holes that are connected and arranged, and the first metal layer 110 can be filled into the n+ electrode layer 105 or the p-well layer 104 through the contact holes. When the first metal layer 110 is filled into the n+ electrode layer 105 through the contact holes, the bottom pb is connected to the n+ electrode layer 105 through the connection part pc and the first mesa part pm1 to form an electric field shielding for the gate oxide layer 107. When the first metal layer 110 is filled into the p-well layer 104 through the contact hole, when the device is in the off state (reverse withstand voltage state), the parasitic PMOS clamps the bottom pb region of the device, and the bottom pb can directly form a connection with the n+ electrode layer 105 through the parasitic PMOS and the p-well layer 104 in sequence, thereby achieving a better electric field shielding effect on the gate oxide layer 107.

[0111] In addition, when the device withstands reverse voltage, the silicon carbide device forms an equivalent PMOS clamp transistor (accumulation type device, the conductive channel is realized by the connection part pc) at the bottom pb, the second n-type doped drift layer 103 and the p-well layer 104 along II-II' (secondary conductive area). Since the gate 108 is grounded, the potential of the second n-type doped drift layer 103 in the area below the p-well layer 104 is relatively high, and the PMOS clamp transistor is turned on, so that the bottom pb can be grounded through the parasitic PMOS designed here, increasing the protection of the corner of the gate oxide layer 107 and improving the gate oxide reliability. The silicon carbide device etches the connection part pc along the I-I' direction to improve the conductivity, so that the I-I' direction is the main conductive area.

[0112] The present disclosure also performs 2D TCAD radiation resistance simulation on the cross section along line II-II', such as Fig. 9 As shown. Among them, Fig. 9 The conditions corresponding to the black inverted triangle simulation curve are: Figure 5 In the cross section shown, the incident point of the irradiated particles is x0=5 μm (corresponding to the incident point at the interface between the gate oxide layer 107 and the connecting portion pc in the model), the voltage VD of the second metal layer 112 is 500 V, and the thickness of the connecting portion pc is Depend on Fig. 9 It can be seen that the device lattice temperature at the peak of the black inverted triangle simulation curve is as high as 1770 K. The difference between the conditions of the blue diamond simulation curve and the black inverted triangle simulation curve is that the thickness of the connection part pc is The peak temperature of the blue diamond simulation curve is 1616K, which is 8.7% lower than that of the black inverted triangle simulation curve. The conditions corresponding to the brown cross simulation curve are: cross section of a classic trench gate device (not including the p-protective layer 106 disclosed in the present invention and the thickness of the gate oxide layer 107 is uniform), the VD voltage is 500V, and the peak temperature of the brown cross simulation curve is greater than 2000K. The difference between the conditions of the black equilateral triangle simulation curve and the black inverted triangle simulation curve is that the voltage VD of the second metal layer 112 is 400V, and its peak temperature is 1336K. The difference between the conditions of the brown asterisk simulation curve and the conditions of the brown cross simulation curve is that the VD voltage is 400V, and the peak temperature of the brown asterisk simulation curve is 1548K.

[0113] It can be seen that, assuming that the SEU failure peak temperature of the silicon carbide device is 1500K, Figure 5 The thickness of the connecting part pc is When the SEU is 1500K, the VSEB is ~500V; for the classic trench gate 2-D device, the VSEB is ~400V when the SEU failure peak temperature is 1500K. The present disclosure increases the SEB voltage threshold of the device for single particle irradiation by more than 20%. In addition, increasing the thickness of the connection part pc can enhance the radiation resistance of the device. The conductive part of the present disclosure can improve the conduction capability in the I-I' direction, and the II-II' direction can mainly provide gate oxide protection and enhance the radiation resistance as a protective structure, so there is no need to limit the thickness of the connection part pc to less than 40nm. In other words, the thickness of the connection part pc of the present disclosure can be greater than or equal to 40nm to improve the radiation resistance.

[0114] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figure 7 As shown, a p+ collector 114 may also be included, thereby retaining Figures 2 to 6The device structure of the MOSFET shown in the figure realizes the structure and function of the IGBT at the same time. When the IGBT device is in the off state, the voltage of the top of the second n-type doped drift layer 103 and the contact area of ​​the p-well layer 104 is relatively high. At this time, the base voltage of the parasitic PMOS (accumulation type) is higher than the gate 108, thereby clamping the bottom pb area of ​​the device. This clamped bottom pb area reflects a strong electric field shielding effect, which greatly improves the reliability of the gate oxide layer 107 in the reverse withstand voltage scenario. Furthermore, when the device is forward-conducted and works in the saturation region, the VCE is low, and there is a parasitic transistor PNP structure formed by the p+ collector 114 (parasitic PNP transistor emitter), the second n-doped drift layer 103 and the n-buffer layer 113 (parasitic PNP transistor base) under the trench T, and the bottom pb (parasitic PNP transistor collector). When the gate 108 injects a large number of electrons into the second n-type doped drift layer 103, the parasitic transistor PNP emitter injects a large number of holes. The holes are blocked by the bottom pb. At the same time, due to the low VCE, the parasitic PMOS at the edge of the gate 108 is also in the off state, resulting in a large number of holes in the bottom pb area (charge storage effect), which reduces Von. The above mechanism explains Figure 1 Both the secondary conductive region in the II-II' direction and the primary conductive region in the II-I' direction are established.

[0115] Based on the same inventive concept, the present disclosure provides a method for manufacturing the above-mentioned silicon carbide device, such as Fig.10 As shown, the following steps may be included:

[0116] S1001, providing an n+ substrate with an off-angle of less than 0.5°;

[0117] S1002, forming a first n-drift layer, a second n-type doped drift layer, a p-well layer and an n+ electrode layer stacked in sequence, and etching to form a groove penetrating the n+ electrode layer, the p-well layer and the second n-type doped drift layer, wherein the groove includes a direction of [11 _ 20] crystal orientation of the first trench, and the orientation of [ _ 1100] a second trench in the crystal direction, the first trench and the second trench define a plurality of square cell regions;

[0118] S1003, epitaxially forming a p-protective layer, the p-protective layer comprising a connecting portion, the connecting portion covers at least a portion of the side surface of the first groove on at least one side of the square cell region, and is blankly arranged on at least a portion of the side surface of the second groove on at least one side of the square cell region.

[0119] In some embodiments, in the above-mentioned manufacturing method provided by the embodiment of the present disclosure, the above-mentioned step S1003 forms a p-protective layer by epitaxial growth, and the p-protective layer includes a connecting portion, and the connecting portion covers at least a portion of the side surface of the first groove on at least one side of the square cell region, and is blankly arranged on at least a portion of the side surface of the second groove on at least one side of the square cell region, which can be specifically implemented in the following manner:

[0120] First, silane, propane, hydrogen, hydrogen chloride and trimethylaluminum are used to epitaxially form a p-protective layer extending from the first trench and the second trench to the side of the n+ electrode layer away from the p-well layer. At this time, the p-protective layer covers the first trench and the second trench.

[0121] Then, a hard mask is deposited on the p-protective layer, and a coating, exposure, development, and etching process are performed on the hard mask so that the hard mask covers at least a portion of the side surface of the first groove on at least one side of the cell area, and an opening is formed on at least a portion of the side surface of the second groove on at least one side of the cell area.

[0122] Finally, under the shielding of the hard mask, the p-protective layer at the opening of the hard mask is removed by Cl2 thermal chemical etching or capacitively coupled plasma (CCP) etching, so that the p-protective layer includes a connection portion covering at least a portion of the side surface of the first groove on at least one side of the cell area, and a blank setting on at least a portion of the side surface of the second groove on at least one side of the cell area.

[0123] In some embodiments, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, in order to completely etch away the connecting portions on the two side surfaces of the second trench T2 between the middle area S2, the above-mentioned hard mask covers at least part of the side surfaces of the first trench on at least one side of the cell area, and forms an opening on at least part of the side surfaces of the second trench on at least one side of the cell area. Specifically, the hard mask hm at most covers the first trench T1, the edge area S1, the second trench T2 between the edge areas S1, the second bottom surface b2 of the second trench T2 between the first partitions S21, and the second partition S22, and forms an opening O at least at the first bottom surface S1 of the second trench T2 between the first partition S21 and the first partition S21.

[0124] For example, Fig.11 and Fig.12 In the embodiment, the hard mask hm covers the first trench T1, the edge area S1, the second trench T2 between the edge area S1, the second bottom surface b2 of the second trench T2 between the first partitions S21 and the second partition S22, and forms an opening O at the first bottom surface S1 of the second trench T2 between the first partitions S21 and the first partition S21. Fig.13 , Fig.14 and Fig.11 , Fig.12In comparison, the opening O of the hard mask hm is enlarged, and the specific difference is that the hard mask hm does not cover the second bottom surface b2 of the second trench T2 between the first partitions S21, but forms the opening O at the second bottom surface b2 of the second trench T2 between the first partitions S21. Fig.15 , Fig.16 and Fig.13 , Fig.14 In comparison, the opening O of the hard mask hm is further enlarged, and the specific difference is that the hard mask hm does not cover the second subarea S22, but forms an opening O at the second subarea S22. A larger opening O can effectively reduce the difficulty of the opening process.

[0125] Since the p-protective layer 106 at the opening O is etched away, the p-protective layer includes a connection portion that covers at least part of the side surface of the first groove on at least one side of the cell area, and is blankly arranged on at least part of the side surface of the second groove on at least one side of the cell area, which can be: the p-protective layer 106 includes a connection portion pc, a bottom pb, a first terrace portion pm1, and a second terrace portion pm2, wherein the connection portion pc covers the side surfaces of the first groove T1 on both sides of the cell area S, and the side surfaces of the second groove T2 on both sides of the edge area S1, and is blankly arranged on the side surfaces of the second groove T2 on both sides of the first partition S21; the bottom pb covers the first bottom surface b1 and the second bottom surface b2 of the first groove T1, and covers the second groove T2; The first bottom surface b1 and the second bottom surface b2, and the thickness h1 of the bottom pb at the first bottom surface b1 of the second trench T2 between the first partitions S21 is less than or equal to the thickness h2 and h3 of the bottom pb outside the first bottom surface b1 of the second trench T21 between the first partitions S21; the first terrace portion pm1 covers the n+ electrode layer 104 (including the first n+ electrode portion n1 and the second n+ electrode portion n2) of the edge area S1, the second terrace portion pm2 at least covers the second n+ electrode portion n2 of the first partition S21, the thickness h5 of the second terrace portion pm2 is less than or equal to the thickness h4 of the first terrace portion pm1, and the thickness h6 of the first n+ electrode portion n1 is less than or equal to the thickness h7 of the second n+ electrode portion n2.

[0126] For example, in the etching process, Fig.11 and Fig.12 After the p-protection layer 106 at the opening O is formed, Fig.17 and Fig.18As shown, the connection portion pc of the p-protection layer 106 covers the side surfaces of the first trench T1 on both sides of the edge region S1, and the side surfaces of the second trench T2 on both sides of the edge region S1, and is blankly arranged on the side surfaces of the second trench T2 on both sides of the first partition S21; the bottom portion pb covers the first bottom surface b1 and the second bottom surface b2 of the first trench T1, and covers the first bottom surface b1 and the second bottom surface b2 of the second trench T2, and the thickness h1 of the bottom portion pb at the first bottom surface b1 of the second trench T2 between the first partitions S21 is less than the thickness h2 of the bottom portion pb at the first bottom surface b1 of the first trench T21, and the thickness h2 of the bottom portion pb at the first bottom surface b1 of the first trench T21 may be equal to the thickness h3 of the bottom portion pb at the second bottom surface b2 of the first trench T1 and the second bottom surface b2 of the second trench T2; the first terrace portion pm1 The first n+ electrode portion n1 and the second n+ electrode portion n2 on both sides of the first trench T1 are covered, the second mesa portion pm2 covers the second n+ electrode portion n2 of the first partition S21 on both sides of the second trench T2, but does not cover the first n+ electrode portion n1 of the first partition S21 on both sides of the second trench T2, the thickness h5 of the second mesa portion pm2 is equal to the thickness h4 of the first mesa portion pm1; the thickness h6 of the first n+ electrode portion n1 on both sides of the first trench T1 is the same as the thickness h7 of the second n+ electrode portion n2, the thickness h6 of the first n+ electrode portion n1 in the first partition S21 on both sides of the second trench T2 is less than the thickness h7 of the second n+ electrode portion n2, and the thickness h7 of the second n+ electrode portion n2 in the first partition S21 on both sides of the second trench T2 is the same as the thickness h7 of the second n+ electrode portion n2 on both sides of the first trench T1. In this embodiment, the bottom pb thickness at the second bottom surface b2 of the second trench T2 is relatively large, which ensures a better hole extraction capability and can improve the reverse withstand voltage capability of the device.

[0127] In etching removal Fig.13 , Fig.14 Device cross section after the p-protection layer 106 at the opening O is removed by etching Fig.11 , Fig.12 In the device cross section after the p-protection layer 106 at the opening O, the transverse cross sections are different but the longitudinal cross sections are the same. Fig.19 For etching removal Fig.13 , Fig.14 The transverse cross section behind the p-protection layer 106 at the opening O, Fig.17 For etching removal Fig.11 , Fig.12 Transverse cross section after the p-protection layer 106 at the opening O. Fig.17 and Fig.19 visible, Fig.19 The thickness h1 of the bottom pb at the first bottom surface b1 of the second trench T2 between the first partitions S21 and the thickness h3 of the bottom pb at the second bottom surface b2 of the second trench T2 between the first partitions S21 are the same, and both are less than Fig.17 The bottom portion pb has a thickness h2 at the first bottom surface b1 of the first trench T21 .

[0128] In etching removal Fig.15 , Fig.16 Device cross section after the p-protection layer 106 at the opening O is removed by etching Fig.13 , Fig.14 In the device cross section after the p-protection layer 106 at the opening O, the transverse cross sections are different but the longitudinal cross sections are the same. Fig. 20 For etching removal Fig.15 , Fig.16 The transverse cross section behind the p-protection layer 106 at the opening O, Fig.19 For etching removal Fig.13 , Fig.14 Transverse cross section after the p-protection layer 106 at the opening O. Fig.19 and Fig. 20 visible: Fig. 20 The second mesa portion pm2 covers the first n+ electrode portion n1 and the second n+ electrode portion n2 of the first partition S21 on both sides of the second trench T2, and the thickness h5 of the second mesa portion pm2 is less than Fig.19 The thickness h4 of the first mesa portion pm1 in the second trench T2 is equal to the thickness h6 of the first n+ electrode portion n1 in the first partition S21 on both sides of the second trench T2, and is equal to the thickness h7 of the second n+ electrode portion n2. Fig.19 The thickness h7 of the second n+ electrode portion n2 on both sides of the first trench T1.

[0129] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, the "same", "equal" and "equal to" in the present disclosure may be completely equivalent, or there may be some deviations. Therefore, the relationship of "same", "equal" and "equal to" between the above features, as long as the error is allowed, belongs to the protection scope of the present disclosure.

[0130] In order to better understand the above-mentioned production method provided by the present disclosure, the following Figure 1 , Figure 2 and Figure 5 The manufacturing process of the silicon carbide device shown in FIG. 1 is described in detail as an example. In some embodiments, Figure 1 , Figure 2 and Figure 5 The manufacturing process of the MOSFET silicon carbide device shown may include the following steps:

[0131] The first step, such as Fig.21As shown, an n-buffer layer 113, an n-drift layer (including the first n-drift layer 102 and the second n-drift layer 103), a p-well layer 104, and an n+ electrode layer 105 (for example, an n+ source layer) stacked from top to top are formed by multiple epitaxy on an n+ substrate 101 with a bias angle approaching 0°. In some embodiments, the n-buffer layer 113, the n-drift layer (including the first n-drift layer 102 and the second n-drift layer 103), the p-well layer 104, and the n+ electrode layer 105 can also be formed by an ion implantation process or an ion implantation process superimposed on an epitaxial process. In some embodiments, a P+ structure 111 that penetrates the n+ electrode layer 105 and is at least partially embedded in the p-well layer 105 can also be formed. In some embodiments, the p+ structure 111 may not be provided, and the present disclosure does not specifically limit it.

[0132] The second step is, Fig. 22 As shown, a groove T can be etched on the surface of the device by dry etching, and the surface CD of the groove T is 0.5μm to 2μm, and the depth is 5μm to 25μm. The groove T includes a direction of [11 _ 20] crystal orientation of the first trench T1, and the direction of [ _ The second trench T2 has a

[1100] crystal orientation, wherein the deviation between the first trench T1 and the

[1120] crystal orientation is within 0.2°, and the deviation between the second trench T2 and the

[1100] crystal orientation is within 0.2°.

[0133] In the third step, the first trench T1 and the second trench T2 are backfilled with p-type silicon carbide by secondary epitaxy to obtain the initial pattern of the p-protective layer 106. At this time, the backfill morphology of the p-protective layer 106 in the first trench T1 is as follows: Fig.18 As shown, the backfill morphology of the p-protection layer 106 in the second trench T2 is similar to that in the first trench T1 (mainly manifested in that the side of the second trench T2 in this step also has a connection portion pc). For details, please refer to Fig.18 . In some embodiments, epitaxial backfill uses a standard silicon carbide epitaxial process: silane, propane, and hydrogen are used as carrier gases. Trimethylaluminum (TMA) is used as a source gas for p-type doping, and the silicon:carbon ratio of the source gas is 1:1; the growth temperature and pressure are 1650°C and 60kPa, respectively, and the growth time is 3h to 6h. The gas flow rates of silane, propane, hydrogen chloride (HCl), and H2 are 36sccm, 12sccm, 1.8slm, and 40slm, respectively. Silane, propane, and hydrogen are used as carrier gases, and trimethylaluminum is used as a source gas for p-type doping. The addition of hydrogen chloride is to have a certain etching effect on the surface of the trench T during the epitaxial process to prevent the trench from closing prematurely during the backfill process, while keeping the p-protective layer 106 thinner on the side of the trench T and the n+ electrode layer 105.

[0134] The fourth step is Fig.15 As shown, a hard mask hm is deposited on the p-protection layer 106, and the hard mask hm is subjected to the processes of coating, exposure, development, and etching, so that the hard mask hm covers the first trench T1, the edge area S1, and the second trench T2 between the edge areas S1, and forms an opening O in the first partition S21, the first bottom surface b1 of the second trench T2 between the first partitions S21, the second bottom surface b2 of the second trench T2 between the first partitions S21, and the second partition S22.

[0135] Step 5: Under the shielding of the hard mask hm, the p-protective layer 106 at the opening O of the hard mask hm is removed by thermal chemical etching of Cl2 or by using CCP etching to form the final pattern of the p-protective layer 106. Under the protection of the hard mask hm, the morphology of the p-protective layer 106 in the first trench T1 region is maintained. Fig.18 The morphology shown in FIG. 1 remains unchanged, and the connection portions pc on the side surfaces of the second trenches T2 on both sides of the edge region S1 are not etched; while the connection portions pc on the side surfaces of the second trenches T2 on both sides of the first subregion S21 and located in the opening O are etched away, as shown in FIG. Fig. 20 As shown. At the same time, during the etching process, Fig. 20 The bottom pb of the second trench T2 and the second mesa portion pm2 of the middle area S2 on both sides of the second trench T2 are partially etched, so that the thickness of the bottom pb of the second trench T2 is reduced (ie, less than Fig.18 The thickness of the bottom pb of the first trench T1 shown in the figure is also reduced (ie, less than the thickness of the second terrace portion pm2 of the middle area S2 on both sides of the second trench T2). Fig.18 The thickness of the first terrace portion pm1 in the edge regions S1 on both sides of the first trench T1 is shown).

[0136] In some embodiments, the thermal chemical etching process can use OX as a hard mask and Cl2 as an etching gas to achieve isotropic chemical etching. The process temperature is 900°C, and Cl2 reacts on the surface with the SiC material connection part pc located in the opening O on the side of the second trench T2 to generate C and SiCl4. The generated C reacts with O2 to become CO2 gas. SiCl4 (boiling point 56.8°C) and CO2 become gas at high temperature and leave the surface of the second trench T2. The etching reaction time needs to be controlled within 15 minutes to ensure that the etching thickness is low and will not have a significant impact on the morphology of the second trench T2. At the same time, the sub-trench structure that may be generated by the above-mentioned third step etching can be repaired. In a normal pressure chlorine environment, at a temperature of 900°C, hot etching is performed for 15 minutes, and the lateral etching depth of the sidewall caused by etching is about 0.2μm, and the bottom etching depth is about 0.7μm. If the etching of the corresponding 40nm thick connection part pc is taken as an example, the etching time is 3 minutes. The CCP etching conditions are preferably: 0.4 mbar, 10 sccm, SF6, 100 W, 450°C.

[0137] Step 6: Fig.23 and Fig.24 As shown, the gate oxide layer 107 is deposited by LPCVD, using tetraethyl orthosilicate (TEOS, Si(OC2H5)4) and oxygen as reactive gaseous precursors, and 50nm to 100nm of silicon dioxide is deposited at 700℃ to 800℃, followed by high-temperature annealing at 1150℃ in a nitric oxide environment (PDA) for 1.5h.

[0138] Step 7: Fig.25 and Fig.26 As shown, polysilicon is deposited by LPCVD, and SiH4 is used as a source gas at a low temperature (600°C) to deposit the polysilicon layer. A thermal chemical vapor deposition method can also be used to deposit the polysilicon layer, and then dry etching is performed so that the polysilicon layer is only retained in the first trench T1 and the second trench T2 as the gate 108. In addition, from the perspective of the device structure, the horizontal position of the bottom surface of the gate 108 is lower than the horizontal position of the bottom surface of the p-well layer 104.

[0139] Step 8: Fig. 27 and Fig.28 As shown, an oxide layer (eg, silicon dioxide) is deposited on the surface of the device as a dielectric layer 109 , so as to achieve passivation isolation between the gate 108 and the subsequent first metal layer 110 through the dielectric layer 109 .

[0140] Step 9: Fig.29 and Fig.30 As shown, the electrode contact area ECT on the surface of the device is defined by the "resin coating-exposure-development" method on the surface of the dielectric layer 109; further, etching is performed in two steps, the first step is to remove the dielectric layer 109 and the gate oxide layer 107 in the ECT area, and the second step is to etch the silicon carbide epitaxial layer in the ECT area. The etching depth must penetrate the first terrace pm1 and the second terrace pm2 of the surface layer according to the by time mode, and reach (or penetrate) the n+ electrode layer 105. The lateral CD of the first terrace pm1 and the second terrace pm2 must be greater than the lateral opening CD of the etching. Further, polysilicon is interconnected at the bottom of the dielectric layer 109 and gathered in the polysilicon pad and the polysilicon bar; the openings of the polysilicon pad and the polysilicon bar can also be obtained on the surface of the dielectric layer 109 by the "resin coating-exposure-development" method, and further interconnected with the surface gate metal pad in the subsequent process.

[0141] Step 10: Fig.31 and Fig.32As shown, a first metal layer 110 (e.g., a source metal layer) is deposited, and the first metal layer 110 is filled into the electrode contact area ECT etched in the previous step, and annealing is performed to achieve ohmic contact between the first metal layer 110 and the n+ electrode layer 105. Then, the source pad and gate pad of the device are defined by dry etching of the surface.

[0142] Step 11: Figure 1 , Figure 2 and Figure 5 As shown, on the back side of the device, the n+ substrate 101 is subjected to CMP thinning, back side metallization and laser annealing to form an ohmic contact second metal layer 112 (eg, drain ohmic metal layer), thereby completing the device manufacturing.

[0143] against Figure 7 The IGBT silicon carbide device shown, based on the above-mentioned MOSFET silicon carbide device manufacturing process, can form a p+ collector 114 on the n+ substrate 101 through a standard epitaxial process / flipped wafer process before epitaxially forming an n-buffer layer 113 on the n+ substrate 101 in the first step, and in the eleventh step, in order to enhance the ohmic contact effect, the n+ substrate 101 can be thinned or even removed through CMP, so that the p+ collector 114 directly forms an ohmic contact with the second metal layer 112 (for example, the collector metal layer).

[0144] It should be noted that in the above-mentioned manufacturing method provided in the embodiment of the present invention, the patterning process involved in forming each layer structure may include not only deposition, photoresist coating, masking, exposure, development, etching, photoresist stripping and other partial or complete process, but also other process, which is subject to the pattern of the required composition formed in the actual manufacturing process and is not limited here. For example, a post-baking process may also be included after development and before etching.

[0145] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, including the above-mentioned silicon carbide device provided by the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the above-mentioned silicon carbide device, the implementation of the electronic device provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned silicon carbide device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0146] In some embodiments, the electronic device of the disclosed embodiment may be an on-board chip of different specifications such as 650V, 750V, 1200V, etc. Further, the silicon carbide device designed based on this scheme can also be applied to high-voltage solid-state transformers of high-speed railways, power grids (distribution and transmission grids), high-voltage photovoltaics, and other scenarios. The electronic devices include but are not limited to: AC motors, inverters, switching power supplies, lighting circuits, etc.

[0147] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A silicon carbide device, characterized in that: include: An n+ substrate, wherein the off-angle of the n+ substrate is less than 0.5°; A first n-drift layer, located on one side of the n+ substrate; a second n-type doped drift layer, located on a side of the first n- drift layer away from the n+ substrate; A p-well layer, located on a side of the second n-type doped drift layer away from the first n-drift layer; An n+ electrode layer is located on a side of the p-well layer away from the second n-type doped drift layer; A groove, which penetrates the n+ electrode layer, the p-well layer and the second n-type doped drift layer, and the groove includes a direction of [11 _ 20] crystal orientation of the first trench, and the orientation of [ _ 1100] a second trench in a crystal direction, wherein the first trench and the second trench define a plurality of square cell regions; The p-protection layer includes a connection portion, which covers at least a portion of the side surface of the first groove on at least one side of the square cell region and is blankly disposed on at least a portion of the side surface of the second groove on at least one side of the square cell region.

2. The silicon carbide device according to claim 1, characterized in that: The connecting portion covers a side surface of the first groove at one side of the square cell region.

3. The silicon carbide device according to claim 1, characterized in that: The connecting portion covers the side surface of the first groove on the other side of the square cell area, or the connecting portion is left blank on the side surface of the first groove on the other side of the square cell area.

4. The silicon carbide device according to claim 1, characterized in that: The square cell region includes an edge region adjacent to the first groove and a middle region located between the edge regions, and the connecting portion is disposed blank on a side of the second groove at one side of the middle region.

5. The silicon carbide device according to claim 4, characterized in that: The connecting portion is disposed blankly on the side surface of the second groove on the other side of the middle area, or the connecting portion covers the side surface of the second groove on the other side of the middle area.

6. The silicon carbide device according to claim 4 or 5, characterized in that: The connecting portion covers side surfaces of the second groove at two sides of the edge region.

7. The silicon carbide device according to any one of claims 1 to 5, characterized in that: The bottom surface of the groove includes a first bottom surface connected to the side surfaces of the groove, and a second bottom surface located between the first bottom surfaces; the side surfaces of the groove include a first side surface covered by the connecting portion, and a second side surface not covered by the connecting portion; The p-protective layer also includes a bottom located in the groove, the bottom having a first thickness at the first bottom surface connected to the second side surface, the bottom having a second thickness at the first bottom surface connected to the first side surface, and the bottom having a third thickness at the second bottom surface, the first thickness is less than the second thickness, and the second thickness is greater than or equal to the third thickness.

8. The silicon carbide device according to any one of claims 1 to 5, characterized in that: The side surface of the groove includes a first side surface covered by the connecting portion and a second side surface not covered by the connecting portion, the square cell region includes an electrode contact region, the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion connected to each other, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the electrode contact region; The p-protective layer also includes a first terrace portion and a second terrace portion, the first terrace portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the first side surface, the second terrace portion at least covers the second n+ electrode portion on the side where the second side surface is located, and the thickness of the second terrace portion is less than or equal to the thickness of the first terrace portion.

9. The silicon carbide device according to claim 8, characterized in that: The second mesa portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the second side surface, and a thickness of the second mesa portion is smaller than a thickness of the first mesa portion.

10. The silicon carbide device according to claim 9, characterized in that: The thickness of the first n+ electrode portion adjacent to the second side surface is equal to the thickness of the second n+ electrode portion connected thereto.

11. The silicon carbide device according to claim 8, characterized in that: The second mesa portion covers the second n+ electrode portion on the side where the second side surface is located, and is left blank at the first n+ electrode portion adjacent to the second side surface. The thickness of the second mesa portion is equal to the thickness of the first mesa portion.

12. The silicon carbide device according to claim 11, characterized in that: The thickness of the first n+ electrode portion adjacent to the second side surface is smaller than the thickness of the second n+ electrode portion connected thereto.

13. The silicon carbide device according to claim 9 or 11, characterized in that: The thickness of the first n+ electrode portion adjacent to the first side surface is equal to the thickness of the second n+ electrode portion connected thereto, and the thickness of the second n+ electrode portion on the side where the first side surface is located is equal to the thickness of the second n+ electrode portion on the side where the second side surface is located.

14. The silicon carbide device according to any one of claims 1 to 5 and 9 to 12, characterized in that: The multiple square cell regions are in [11 _ 20] crystal orientation and [ _ 1100] are arranged in an array in the crystal direction.

15. The silicon carbide device according to any one of claims 1 to 5 and 9 to 12, characterized in that: The multiple square cell regions are in [11 _ 20] crystal orientation and / or [ _ 1100] The crystals are arranged in a staggered manner.

16. The silicon carbide device according to any one of claims 1 to 5 and 9 to 12, characterized in that: The n+ electrode layer is an n+ source layer or an n+ emitter layer.

17. A method for manufacturing a silicon carbide device according to any one of claims 1 to 16, characterized in that: include: Providing an n+ substrate with an off-angle of less than 0.5°; A first n-drift layer, a second n-type doped drift layer, a p-well layer and an n+ electrode layer are stacked in sequence, and a trench penetrating the n+ electrode layer, the p-well layer and the second n-type doped drift layer is formed by etching, wherein the trench includes a direction of [11 _ 20] crystal orientation of the first trench, and the orientation of [ _ 1100] a second trench in a crystal direction, wherein the first trench and the second trench define a plurality of square cell regions; A p-protective layer is formed by epitaxial growth, wherein the p-protective layer includes a connecting portion, which covers at least a portion of the side surface of the first groove on at least one side of the square cell region and is blankly disposed on at least a portion of the side surface of the second groove on at least one side of the square cell region.

18. The method of claim 17, wherein: Epitaxially forming a p-protective layer, the p-protective layer comprising a connecting portion, the connecting portion covering at least a portion of the side surface of the first trench on at least one side of the square cell region, and being blankly arranged on at least a portion of the side surface of the second trench on at least one side of the square cell region, specifically comprising: Using silane, propane, hydrogen, hydrogen chloride and trimethylaluminum, epitaxially forming a p-protective layer extending from the first trench and the second trench to the side of the n+ electrode layer away from the p-well layer; Depositing a hard mask on the p-protective layer, and performing resist coating, exposure, development, and etching processes on the hard mask so that the hard mask covers at least a portion of the side surface of the first trench on at least one side of the cell region, and forms an opening on at least a portion of the side surface of the second trench on at least one side of the cell region; Under the shielding of the hard mask, the p-protective layer at the opening of the hard mask is removed by Cl2 thermal chemical etching or capacitively coupled plasma etching, so that the p-protective layer includes a connection portion covering at least a portion of the side surface of the first groove on at least one side of the cell area, and a blank connection portion is provided on at least a portion of the side surface of the second groove on at least one side of the cell area.

19. The method of claim 18, wherein: The square cell region includes an edge region adjacent to the first groove and an intermediate region between the edge regions, the intermediate region includes a first subregion adjacent to the second groove and a second subregion between the first subregions, the second subregion includes an electrode contact region; the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion located between the edge region, the first subregion, and the edge region and the electrode contact region, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the electrode contact region; the bottom surface of the groove includes a first bottom surface connected to the side surface of the groove, and a second bottom surface located between the first bottom surfaces; The hard mask covers at least a portion of the side surface of the first trench on at least one side of the cell region, and forms an opening on at least a portion of the side surface of the second trench on at least one side of the cell region, including: The hard mask at most covers the first trench, the edge region, the second trench between the edge regions, the second bottom surface of the second trench between the first sub-regions, and the second sub-regions, and forms an opening at least at the first bottom surface of the second trench between the first sub-regions and the first sub-regions; The p-protection layer includes a connection portion covering at least a portion of the side surface of the first groove on at least one side of the square cell region and provided blank on at least a portion of the side surface of the second groove on at least one side of the square cell region, specifically including: The p-protective layer includes a connecting portion, a bottom, a first table portion and a second table portion, wherein the connecting portion covers the side surfaces of the first groove on both sides of the edge area, and the side surfaces of the second groove on both sides of the edge area, and is blankly arranged on the side surfaces of the second groove on both sides of the first partition; the bottom covers the first bottom surface and the second bottom surface of the first groove, and covers the first bottom surface and the second bottom surface of the second groove, and the thickness of the bottom at the first bottom surface of the second groove between the first partitions is less than or equal to the thickness of the bottom outside the first bottom surface of the second groove between the first partitions; the first table portion covers the n+ electrode layer of the edge area, the second table portion covers at least the second n+ electrode portion of the first partition, the thickness of the second table portion is less than or equal to the thickness of the first table portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion.

20. The method of claim 19, wherein: The hard mask at most covers the first trench, the edge region, the second trench between the edge regions, the second bottom surface of the second trench between the first sub-regions, and the second sub-region, and forms an opening at least at the first bottom surface of the second trench between the first sub-region and the first sub-region, specifically comprising: The hard mask covers the first trench, the edge region, the second trench between the edge regions, and the second sub-region, and forms openings at the first sub-region, the first bottom surface of the second trench between the first sub-region, and the second bottom surface; The thickness of the bottom at the first bottom surface of the second groove between the first partitions is less than or equal to the thickness of the bottom outside the first bottom surface of the second groove between the first partitions, specifically including: The thickness of the bottom between the first partitions is smaller than the thickness of the bottom outside the first partitions; The second mesa portion at least covers the second n+ electrode portion of the first partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including: The second table portion covers the second n+ electrode portion of the first partition and is set blank at the first n+ electrode portion of the first partition. The thickness of the second table portion is equal to the thickness of the first table portion. The thickness of the first n+ electrode portion on the side where the second table portion is located is less than the thickness of the second n+ electrode portion.

21. The method of claim 19, wherein: The hard mask at most covers the first trench, the edge region, the second trench between the edge regions, the second bottom surface of the second trench between the first sub-regions, and the second sub-region, and forms an opening at least at the first bottom surface of the second trench between the first sub-region and the first sub-region, specifically comprising: The hard mask covers the first trench, the edge region, and the second trench between the edge regions, and forms openings in the first sub-region, the first bottom surface and the second bottom surface of the second trench between the first sub-regions, and the second sub-region; The thickness of the bottom at the first bottom surface of the second groove between the first partitions is less than or equal to the thickness of the bottom outside the first bottom surface of the second groove between the first partitions, specifically including: The thickness of the bottom between the first partitions is smaller than the thickness of the bottom outside the first partitions; The second mesa portion at least covers the second n+ electrode portion of the first partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including: The second mesa portion covers the first n+ electrode portion and the second n+ electrode portion of the first partition, the thickness of the second mesa portion is smaller than the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is equal to the thickness of the second n+ electrode portion.

22. An electronic device, characterized in that: A silicon carbide device comprising any one of claims 1 to 16.

Images