Quantum dot structure

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to quantum dot structures and methods of manufacture. The structure includes: a plurality of barrier gates; a plurality of spin quantum bit gates interleaved with the plurality of barrier gates; and access gates located on opposite sides of the plurality of barrier gates.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to quantum dot structures and methods of fabrication. Background Art

[0002] Spin qubit quantum computers are quantum computers based on controlling the spin of charge carriers (electrons and electron holes) in semiconductor devices. Spin qubit quantum computers use the intrinsic free spin of a single electron confined in a quantum dot as a quantum bit, also known as a qubit. Quantum dots are tiny semiconductor structures that can be used as quantum bits, with quantum information stored in the spin state or charge state of the confined electron. Therefore, a quantum bit or qubit is the basic unit of information in a quantum computer.

[0003] Spin qubits have been realized by locally depleting the two-dimensional electron gas in semiconductor materials such as gallium arsenide, silicon and germanium. Spin qubits have also been realized in graphene. But the limited coherence time of these qubits greatly limits their potential applications. Summary of the invention

[0004] In one aspect of the present disclosure, a structure includes: a plurality of barrier gates; a plurality of spin qubit gates interleaved with the plurality of barrier gates; and an access gate located on opposite sides of the plurality of barrier gates.

[0005] In one aspect of the present disclosure, a structure includes: spin qubit gates; self-aligned barrier gates that are interleaved with the plurality of spin qubit gates; access gates that are located on opposite sides of the barrier gates; source and drain regions that are adjacent to the access gates; and a liner material that separates the spin qubit gates, the self-aligned barrier gates, and the access gates from each other, and separates the access gates from the source and drain regions.

[0006] In one aspect of the disclosure, a method includes forming a plurality of barrier gates; forming a plurality of spin qubit gates interleaved with the plurality of barrier gates; and forming access gates on opposite sides of the plurality of barrier gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0008] Figure 1 The structure and corresponding manufacturing process according to some aspects of the present disclosure are shown.

[0009] Figure 2 Structures according to additional aspects of the present disclosure are shown.

[0010] Figures 3A-3G A corresponding manufacturing process according to some aspects of the present disclosure is shown.

[0011] Figures 4A-4D A corresponding manufacturing process according to additional aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0012] The present disclosure relates to semiconductor structures, and more specifically, to quantum dot structures and methods of fabrication. More specifically, the structures described herein include self-aligned barrier gates that include polysilicon or metal fillers located between spin qubit gates. In this way, the polysilicon or metal fillers include self-aligned barrier gates that are interlaced with the spin qubit gates. Advantageously, self-alignment of the barrier gates is a low complexity process that provides improved alignment while reducing spin qubit gate variations. Additionally, the process flow is compatible with current CMOS processes.

[0013] In a more specific embodiment, the structure provided herein can be implemented in a quantum dot device (e.g., a spin qubit quantum computer). The structure includes a plurality of barrier gates, and a spin qubit gate interlaced with the plurality of barrier gates. The barrier gate can be symmetrically positioned between the access gate and the spin qubit gate. The barrier gate can also be separated or electrically isolated from the gate dielectric material of the spin qubit gate by a conformal liner (e.g., a barrier liner). The spin qubit gate can be, for example, a polysilicon or high-k metal gate structure. On the other hand, the barrier gate can be a conductive material. The access gate can be disposed on opposite sides of a string of gates, for example, the barrier gate is located at the end of the string of gates. In an embodiment, the access gate can have a larger size than the spin qubit gate or the barrier gate. An elevated source region and a drain region can be disposed adjacent to the access gate. A semiconductor transistor on an insulator can be disposed adjacent to a quantum dot device.

[0014] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on top of the wafer by means of a photolithography process. Specifically, the manufacture of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0015] Figure 1 The structure and corresponding manufacturing process according to some aspects of the present disclosure are shown. Specifically, Figure 1 The structure 10 shown includes a plurality of barrier gates 12 alternating with a plurality of spin qubit gates 14. In an embodiment, the plurality of barrier gates 12 may be interleaved with the plurality of spin qubit gates 14. The plurality of barrier gates 12 may also be symmetrically positioned relative to the plurality of spin qubit gates 14 and the access gate 16. The plurality of barrier gates 12 may be self-aligned barrier gates 12 comprising a metal fill material, as further described herein. The access gate 16 may be disposed adjacent to the plurality of barrier gates 12, at opposite ends of the plurality of barrier gates 12 alternating with the plurality of spin qubit gates 14. In an embodiment, the plurality of barrier gates 12 may be electrically and physically isolated from the spin qubit gates 14, wherein each of the gates 12, 14, 16 can be independently biased.

[0016] Still reference Figure 1 In an embodiment, the structure 10 further includes a semiconductor substrate 18. The semiconductor substrate 18 may be, for example, a semiconductor-on-insulator substrate, which includes a handle substrate 18a, an insulator layer 18b located on top of the handle substrate 18a, and a semiconductor layer 18c located on top of the insulator layer 18b. The handle substrate 18a provides mechanical support for the buried insulator layer 18b and the top semiconductor layer 18c. The gates 12, 14, 16 are formed on the top semiconductor layer 18c.

[0017] The handling substrate 18a and the semiconductor substrate 18c may be composed of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, alloys, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. In an embodiment, the semiconductor substrate 18c may include any suitable single crystal orientation (e.g., (100), (110), (111) or (001) crystal orientation). The top semiconductor layer 18c may be formed by a deposition process such as CVD or PECVD. Alternatively, the top semiconductor layer 18c may be formed using a smart cut process, in which two semiconductor wafers are bonded together with an insulator therebetween.

[0018] The insulator layer 18b includes any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and / or combinations thereof. An exemplary insulator layer may be a buried oxide layer (BOX). The insulator layer 18b may be formed by any suitable process, such as isolation by implanted oxygen (SIMOX), oxidation, deposition, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition CVD (PECVD) or physical vapor deposition (PVD), and / or other suitable processes.

[0019] Still reference Figure 1 A shallow trench isolation structure 26 may be formed adjacent to the access gate 16, and more specifically, the elevated source and drain regions 22. In an embodiment, the shallow trench isolation structure 26 may be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art, such as those described in detail with respect to FIG. Figure 3A Further described.

[0020] A plurality of barrier gates 12 that alternate (e.g., interlaced) with a plurality of spin qubit gates 14 are formed on a semiconductor substrate 18. An access gate 16 may be disposed at both ends of a string of alternating barrier gates 12 and spin qubit gates 14, also on the semiconductor substrate 18. In an embodiment, the plurality of barrier gates 12 may be self-aligned barrier gates 12 that include a metal fill material 12a surrounded by a dielectric material 12b. The metal fill material 12a may be any conductive material, including, for example, tungsten, and the dielectric material 12b may be, for example, an oxide material. The oxide material 12b may electrically and physically isolate the barrier gate 12 (e.g., the metal fill material 12) from the spin qubit gate 14. The access gate 16 may have a different size, for example, larger than the barrier gate 12 or the spin qubit gate 14.

[0021] An optional barrier layer 20 may line the barrier gate 12, the spin qubit gate 14, and the access gate 16. In an embodiment, the barrier layer 20 may be a nitride material that electrically and physically isolates the barrier gate 12 from the spin qubit gate 14 and the access gate 16. For example, the barrier layer 20 may act as a sidewall spacer between the barrier gate 12, the spin qubit gate 14, and the access gate 16. In addition, the barrier layer 20 may isolate the access gate 16 from the source and drain regions 22. The barrier layer 20 may also serve as an etch stop liner.

[0022] In an embodiment, the source and drain regions 22 may be elevated regions formed by in-situ doping processes and epitaxial growth processes known in the art, and therefore no further explanation is required to fully understand the present disclosure. An annealing process may be performed to drive dopants into the semiconductor material. Silicide contacts 24 may be formed over the source and drain regions 22. Those skilled in the art will appreciate that silicide contacts will not be required on the metal gate structure; however, as described with respect to Figure 2 As further described, such silicide contacts are contemplated herein for use with polysilicon gate structures.

[0023] In an embodiment, the plurality of spin qubit gates 14 may include a gate dielectric material 14a, a gate metal material 14b, and a cap material 14c located on the gate metal material 14b. Similarly, the access gate 16 may include a gate dielectric material 16a, a gate metal material 16b, and a cap material 14c located on the gate metal material 14b. The gate dielectric materials 14a, 16a may be low-k dielectric materials (e.g., SiON) or high-k dielectric materials. For example, the high-k dielectric material may be, for example, HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations including multilayers thereof. The gate metal materials 14b, 16b may be work function materials, such as Ti, TiAl, Al, TaN, TaAlC, TiN, TiC, Co, TaC, or other known work function metals. The work function material and the dielectric material may be the same material and fabricated in the same process used for the access gate 16 and the spin qubit gate 14 .

[0024] The work function material and the gate dielectric material may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. The cap material 14c, 16c may be an oxide material; although other capping materials may be considered herein. It will be appreciated by those skilled in the art that the plurality of barrier gates 12 will not contact the spin qubit gate 14, and more specifically, will be electrically isolated from at least the gate dielectric material 14a.

[0025] In an alternative embodiment, for example, the spin qubit gate 14 includes a polysilicon material. In addition, in this embodiment, the spin qubit gate 14 may also include a silicide contact (which may be indicated by reference numeral 14c). However, it should be understood that silicide (e.g., silicide contact) is optional because no large current flows through the qubit gate structure.

[0026] In operation, a single electron is "injected" into the spin qubit gate 14 by the access gate 16. The electron will be confined below the spin qubit gate 14 (e.g., a quantum dot) using the potential generated by the barrier gate 12. Under high magnetic fields, the electrons exhibit spin. The entanglement of adjacent electrons is controlled by the potential generated by the barrier gate 12 (e.g., a qubit). Using the structure described herein, it is now possible to minimize the qubit gate area so that a single electron is located below one gate, i.e., the minimum active area (RX) and the shortest gate length. In addition, using the structure described herein, the gate pitch can also be minimized to optimize the entanglement between adjacent qubits.

[0027] An optional barrier layer 28 may be formed over structures 12, 14, 16. An interlayer dielectric material 30 may be formed over the optional barrier layer 28. In an embodiment, the optional barrier layer 28 may be part of the interlayer dielectric material 30. For example, the interlayer dielectric material 30 may be an oxide or nitride material, or may be alternating layers of oxide and nitride materials. A transistor 32 may be integrated into the structure using conventional CMOS technology. For example, the transistor 32 may be a high-k metal gate formed on a semiconductor-on-insulator substrate 18c.

[0028] In addition to the source and drain regions 22, contacts 34 may be formed to the gate structures 12, 14, 16, and 32. In an embodiment, the contacts 34 may be staggered to ensure proper electrical isolation from each other. The contacts 34 allow each of the gate structures 12, 14, 16, 32 to be biased individually. The contacts 34 may be formed by conventional CMOS processes as described in more detail herein.

[0029] Figure 2 shows a structure according to additional aspects of the present disclosure. Figure 1 The structure 10, Figure 2 The structure 10a includes a plurality of barrier gates 12' alternating with a plurality of spin qubit gates 14. However, in this embodiment, the plurality of barrier gates 12' comprises polysilicon material. In an embodiment, the use of polysilicon may result in a tighter pitch of the self-aligned barrier gates 12'. In addition, the barrier gates 12' may include silicide contacts (which may be indicated by reference numeral 12c). The remaining structure is the same as Figure 1 The structure 10 is similar.

[0030] Figures 3A-3G The corresponding manufacturing process according to some aspects of the present disclosure is shown. In an embodiment, Figures 3A-3G shows a back-polished Figure 2 Generally, these figures show the patterning of the spin qubit gate (e.g., Figure 3A ), including a filling process of an interlayer dielectric material, a subsequent back-polishing process (e.g., Figure 3D ), openings formed in the interlayer dielectric material (e.g., Figure 3E ), then forming a barrier gate and performing a back polishing process (eg, planarization) (eg, Figure 3F ). Silicidation of source / drain access gates and spin qubit gates using cap material is also provided simultaneously on the barrier gate (e.g., Figure 3G ). In this process flow, contacts are placed on silicided contacts (e.g., NiSi) for the source / drain access gates, spin qubit gate, and barrier gate.

[0031] More specifically, Figure 3A A semiconductor substrate 18 having a shallow trench isolation structure 26 and a plurality of materials formed above the semiconductor substrate 18 is shown. The shallow trench isolation structure 26 can be formed by conventional CMOS processes. For example, a resist formed above the semiconductor substrate 18 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), is used to transfer the pattern from the photoresist layer to the semiconductor substrate 18 to form one or more trenches in the semiconductor substrate 18 through the openings of the resist. After the resist is removed by a conventional oxygen ashing process or other known strippers, an insulator material (e.g., SiO2) can be deposited by any conventional deposition process, such as a chemical vapor deposition (CVD) process. Any residual material on the surface of the semiconductor substrate 18 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0032] The multiple materials may include, for example, a gate oxide material 36 (e.g., gate dielectric material 14a, 16a), a gate metal 38 (e.g., gate metal material 14b, 16b), and a sacrificial mask material (e.g., hard mask) 40. The different materials may be deposited by conventional deposition processes (e.g., CVD, PECVD), and then an etching process is performed to form a material stack (e.g., stack 42). In an embodiment, stack 42 will be used to form multiple spin qubit gates 14 and access gates 16. The etching process may be conventional reactive ion etching (RIE) with selective chemistry.

[0033] exist Figure 3B In the embodiment, a barrier liner (e.g., an etch stop layer) 20 may be formed over the stack 42 and the exposed portion of the semiconductor substrate 18. In an embodiment, the barrier layer 20 may be deposited by a conventional blanket deposition process. For example, the barrier layer 20 may be a nitride material formed by a CVD process.

[0034] The barrier layer 20 in the source and drain regions 22 may be removed using conventional photolithography and etching processes. In an embodiment, a hard mask used for the photolithography process will cover (e.g., protect) the stack 42 during the etching process (e.g., where the gates (e.g., gates 12, 14, 16) are formed). In this way, the barrier layer 20 may be removed to expose the underlying semiconductor substrate 18 and the shallow trench isolation structures 26. After conventional stripping and cleaning processes, the elevated source and drain regions 22 will be epitaxially grown on the exposed underlying semiconductor substrate 18, as already described herein.

[0035] exist Figure 3CIn the embodiment of the present invention, an optional nitride liner 20a may be deposited on the exposed surfaces of the stack 42, the source and drain regions 22, and the shallow trench isolation structures 26. The optional nitride liner 20a may be formed by a conventional CVD process.

[0036] exist Figure 3D In the embodiment of the present invention, an oxide fill 30a may be deposited between the stack 42, over the source and drain regions 22 and the shallow trench isolation structure 26. The oxide fill 30a may be subjected to a chemical mechanical planarization (CMP) process. The CMP process will also planarize (e.g., remove) a portion of the sacrificial mask 40 of the stack 42.

[0037] exist Figure 3E In the embodiment of the present invention, openings 44 are formed in the regions between selected stacks 42 by removing oxide filler 30a. More specifically, oxide filler 30a can be removed at the location where the barrier gate will be formed, thereby forming, for example, opening 44. Oxide filler 30a can be removed by conventional photolithography and etching processes. The etching process will stop at barrier liner 20 (e.g., etch stop layer).

[0038] exist Figure 3F In the embodiment of the present invention, the polysilicon gate structure 12 is formed in the opening 44 and then a planarization process is performed. The structure is planarized to remove the remaining portion of the sacrificial mask 40 and the upper portion of the oxide fill 30a and the polysilicon material. In this way, the gates 12, 14, 16 are now formed.

[0039] exist Figure 3G , silicide contacts 24 can be formed on the source and drain regions 22 and the barrier gate 12, and in this embodiment, on a spin qubit gate comprising a polysilicon material. Those skilled in the art will appreciate that the silicide process begins with depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over a fully formed and patterned semiconductor device (e.g., source and drain regions 22). After the material is deposited, the structure is heated, allowing the transition metal to react with exposed silicon (or other semiconductor materials described herein) in the active regions (e.g., source and drain regions) of the semiconductor device to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device. Those skilled in the art will appreciate that silicide contacts are not required on the metal gate structure; however, as described with respect to Figure 2 As further described, such silicide contacts are contemplated herein for use with polysilicon gate structures.

[0040] Return to reference Figure 2, a contact 34 to each of the gates 12, 14, 16 and the source and drain regions 22 can be formed. The contact 34 can be formed by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, the photolithography and etching process forms a via or trench through the interlayer dielectric material 30, exposing the underlying structure (e.g., the gates 12, 14, 16 and the source and drain regions 22). A metal material can be deposited in the trench to contact the underlying structure. The metal material can be, for example, aluminum, copper, tungsten, etc. lined with a material such as TaN or Tin (as an example). Any residual material can be removed from the interlayer dielectric material 30 by a conventional CMP process.

[0041] Figures 4A-4D The corresponding manufacturing process according to the additional aspects of the present disclosure is shown. In an embodiment, Figures 4A-4D Shows Figure 1 A general manufacturing process scheme of structure 10 is shown. In this process scheme, for example, a silicidation process can be performed before a barrier gate fill process. In addition, in this process flow, contacts fall on metal barrier gates and on silicide (e.g., NiSi) contacts on spin qubit gates and access gates. In addition, a silicidation process is performed before a barrier gate fill process.

[0042] from Figure 3B The structure shown starts with and refers to Figure 4A , the hard mask material 40 can be removed by a wet etching process. After removing the hard mask material, silicide contacts 24 can be formed on the source and drain regions 22, as already described herein. Where appropriate, a cap material or additional silicide contacts 15 can be formed over the remaining material stacks for forming the spin qubit gate 14 and the access gate 16, respectively.

[0043] exist Figure 4B In the embodiment, an oxide filler 30a is formed over the source and drain regions 22. In an embodiment, the oxide filler 30a can be deposited by a conventional CVD process and then a CMP process is performed. The CMP process will stop on the silicide contact or cap material 15. The oxide filler 30a between the spin qubit gates 14 and between the spin qubit gates 14 and the access gates 16 will be removed, leaving the barrier layer 20 on the semiconductor substrate 18 within the opening 44. The oxide filler 30a can be removed by conventional photolithography and masking materials.

[0044] like Figure 4CAs shown, an insulator liner 12b and a metal material 48 may be deposited within the opening 44 to form a barrier gate 12 between the spin qubit gates 14 and between the spin qubit gates 14 and the access gate 16. In an embodiment, the metal material 48 may be tungsten (W) and the insulator liner 12b may be an oxide, both of which may be deposited by conventional deposition processes (e.g., CVD). Figure 4D In the process, the metal material 48 and the insulator liner 12b may undergo a planarization process, such as CMP, to form the barrier gate 12. The process may then return to Figure 1 , for example to form contact 34 .

[0045] These structures can be exploited in system-on-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies a much smaller area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0046] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die or in a packaged form. In the latter case, the chip is installed in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having surface interconnects or buried interconnects, or both surface interconnects and buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0047] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: multiple barrier gates; a plurality of spin qubit gates interlaced with the plurality of barrier gates; as well as An access gate is located on an opposite side of the plurality of barrier gates.

2. The structure according to claim 1, wherein: The plurality of barrier gates are self-aligned barrier gates physically isolated from the plurality of spin qubit gates.

3. The structure according to claim 1, wherein: The plurality of barrier gates, the plurality of spin qubit gates, and the access gate are contacted to be independently biased.

4. The structure according to claim 1, wherein: The plurality of barrier gates include a metal material surrounded by an insulator material that isolates the plurality of barrier gates from the plurality of spin qubit gates.

5. The structure according to claim 1, wherein: The plurality of barrier gates include a polysilicon material surrounded by an insulator material that isolates the plurality of barrier gates from the plurality of spin qubit gates.

6. The structure of claim 1 further comprising a liner material disposed between the plurality of barrier gates and the plurality of spin qubit gates and the access gate.

7. The structure according to claim 1, wherein: The access gate is larger than the plurality of barrier gates and the plurality of spin qubit gates.

8. The structure of claim 1 further comprising a source region and a drain region adjacent to the access gate.

9. The structure according to claim 1, wherein: The barrier gate is symmetrically positioned relative to the plurality of spin qubit gates and the access gate.

10. The structure according to claim 1, wherein: The plurality of spin qubit gates include polysilicon.

11. The structure according to claim 1, wherein: The plurality of spin qubit gates include a high-k metal gate structure.

12. The structure according to claim 1, wherein: The plurality of spin qubit gates, the access gate, and the plurality of barrier gates are disposed on a semiconductor-on-insulator (SOI) substrate.

13. A structure comprising: Spin qubit gates; a self-aligned barrier gate interleaved with the plurality of spin qubit gates; an access gate located on an opposite side of the barrier gate; a source region and a drain region adjacent to the access gate; as well as A liner material separates the spin qubit gate, the self-aligned barrier gate, and the access gate from each other, and separates the access gate from the source and drain regions.

14. The structure according to claim 13, wherein: The self-aligned barrier gate is symmetric about the plurality of qubit gates.

15. The structure according to claim 13, wherein: The spin qubit gate comprises polysilicon, wherein a silicide is located on top of the spin qubit gate.

16. The structure of claim 13, wherein: The spin qubit gate includes a high-k metal gate structure.

17. The structure of claim 13, wherein: The self-aligned barrier gate includes a metal material surrounded by an insulator material.

18. The structure of claim 13, wherein: The self-aligned barrier gate includes a polysilicon material surrounded by an insulator material.

19. The structure of claim 13, wherein: The self-aligned barrier gate and the spin qubit gate are contacted to be independently biased.

20. A method comprising: forming a plurality of barrier gates; forming a plurality of spin qubit gates interlaced with the plurality of barrier gates; as well as Access gates are formed on opposite sides of the plurality of barrier gates.

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