Semiconductor element arrangement structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor element arrangement structure and a manufacturing method thereof. The semiconductor element arrangement structure comprises a carrier, a plurality of semiconductor elements and an adhesive layer. The plurality of semiconductor elements are separated from each other on the carrier, and each semiconductor element includes an electrode. The adhesive layer is disposed between the carrier and the plurality of semiconductor elements, and the plurality of semiconductor elements are attached to the adhesive layer. And the adhesive layer is of a continuously distributed single-layer structure. The adhesive layer includes a plurality of unselected regions and a selected region, the unselected regions are respectively covered by the plurality of semiconductor elements, and the selected region is not covered by the plurality of semiconductor elements. The adhesive layer further comprises a recessed trace, the recessed trace is located on the selected area, in a section view or a top view, the contour of the recessed trace is a scaled view of the contour of the electrode, and the depth of the recessed trace is smaller than the thickness of the electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor element arrangement structure, and in particular to a semiconductor element arrangement structure in which semiconductor elements are adhered to a carrier board and a manufacturing method thereof. Background Art

[0002] Semiconductor components such as light-emitting diodes (LEDs) have the advantages of low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed, and good photoelectric properties (such as stable light emission wavelength). Therefore, they are widely used in electronic devices such as household appliances, equipment indicator lights, and displays.

[0003] In order to manufacture different electronic devices, a large number of light-emitting diodes need to be transferred between different substrates. The steps usually include transferring a plurality of light-emitting diodes from a growth substrate to a temporary substrate, and fixing the plurality of light-emitting diodes thereon through an adhesive layer on the temporary substrate. Afterwards, an etching process is used to remove the adhesive layer between adjacent light-emitting diodes, and after the etching process is performed, an adhesive layer still exists between the surface of the light-emitting diode (for example, the front side including the electrode) and the temporary substrate. Subsequently, the light-emitting diode can be further transferred to a target substrate, so that the back side of the light-emitting diode faces the target substrate, and the front side of the light-emitting diode is away from the target substrate. Then, an etching process is performed to remove the adhesive layer on the front side of the light-emitting diode, further exposing the electrode of the light-emitting diode for subsequent electrical connection with the outside.

[0004] However, in the above-mentioned etching processes, in order to completely remove the adhesive layer between adjacent LEDs or the adhesive layer on the front of each LED, the etching process often takes a long etching time, and the heat energy generated by the etching process may also cause some LEDs to be skewed in a direction perpendicular to the substrate surface or offset in a direction horizontal to the substrate surface. This not only causes the manufacturing process to be time-consuming and have a low yield, but is also not conducive to subsequent manufacturing processes. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a semiconductor device arrangement structure and a manufacturing method thereof to overcome the technical problems encountered in the prior art.

[0006] According to one embodiment of the present invention, a semiconductor element arrangement structure is provided, comprising a carrier, a plurality of semiconductor elements, and an adhesive layer. The plurality of semiconductor elements are separated from each other and located on the carrier, and each semiconductor element comprises an electrode. The adhesive layer is disposed between the carrier and the plurality of semiconductor elements, and the plurality of semiconductor elements are attached to the adhesive layer. The adhesive layer is a continuously distributed single-layer structure, and comprises a plurality of unselected areas and a selected area, wherein the plurality of unselected areas are respectively covered by a plurality of semiconductor elements, and the selected area is not covered by the semiconductor element. The adhesive layer further comprises a surface where a concave mark is located in the selected area, wherein in a cross-sectional view, the contour of the concave mark is a scaled view of the contour of the electrode, and the depth of the concave mark is less than the thickness of the electrode.

[0007] According to one embodiment of the present invention, a method for manufacturing a semiconductor element arrangement structure is provided, comprising: providing a carrier, wherein an adhesive layer is disposed on the surface of the carrier, and the adhesive layer is a single-layer structure, and its material is, for example, an elastomer; attaching the semiconductor element to a selected area of ​​the adhesive layer; providing a target substrate, having a surface facing the semiconductor element and not contacting the semiconductor element; and enabling the selected area of ​​the adhesive layer to allow the semiconductor element to detach from the adhesive layer and transfer to the surface of the target substrate, wherein when the selected area of ​​the adhesive layer is enabled, the selected area of ​​the adhesive layer is still attached to the carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. The specific embodiments of the present invention are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the sizes of some features in some drawings may be deliberately enlarged or reduced.

[0009] Figure 1 is a top view and a partial area enlarged view of a semiconductor element arrangement structure according to an embodiment of the present invention;

[0010] Figure 2 An embodiment of the present invention is along the Figure 1 a cross-sectional view depicted along section line AA';

[0011] Figure 3 An embodiment of the present invention Figure 2 An enlarged view of a local area R2;

[0012] Figure 4 is an enlarged view of a local area of ​​a semiconductor element arrangement structure according to another embodiment of the present invention;

[0013] Figure 5 is an enlarged view of a local area of ​​a semiconductor element arrangement structure according to another embodiment of the present invention;

[0014] Figure 6 is a top view of a semiconductor element arrangement structure according to an embodiment of the present invention;

[0015] Figure 7 An embodiment of the present invention is along the Figure 6 a cross-sectional view depicted along section line BB';

[0016] Figure 8 An embodiment of the present invention Figure 7 An enlarged view of a local area R3;

[0017] Fig. 9 is a cross-sectional view of different stages of a manufacturing process for transferring a plurality of semiconductor elements from a first supporting substrate to a second supporting substrate according to an embodiment of the present invention;

[0018] Fig.10 is a cross-sectional view of different stages of a manufacturing process of transferring a plurality of semiconductor elements from a second supporting substrate to a third supporting substrate according to an embodiment of the present invention;

[0019] Fig.11 It is a cross-sectional view of different manufacturing process stages of transferring a plurality of semiconductor components from a second supporting substrate to a third supporting substrate according to another embodiment of the present invention.

[0020] Explanation of symbols

[0021] 100, 612…carrier

[0022] 102, 110a, 402, 502, 602…front

[0023] 104, 110b, 404, 504, 604…back

[0024] 110…Semiconductor components

[0025] 110-1 ... first semiconductor element

[0026] 110-2 ... second semiconductor element

[0027] 110-3…third semiconductor element

[0028] 110-4 ... fourth semiconductor element

[0029] 120…Component body

[0030] 122…Electrode

[0031] 200…Adhesive layer

[0032] 202…Shield

[0033] 204…Exposure

[0034] 210…Adhesive part

[0035] 220…Dent marks

[0036] 232…Selected area

[0037] 234…No region selected

[0038] 240…Expansion area

[0039] 400…first supporting substrate

[0040] 500…Second supporting substrate

[0041] 600…third supporting substrate

[0042] 614…Adhesion layer

[0043] 1000…Semiconductor element arrangement structure

[0044] AA', BB'...Section line

[0045] D1…First Depth

[0046] D2…Second Depth

[0047] E1…Stimulus

[0048] E2…Light Source

[0049] L1…Length

[0050] R1, R2, R3…local area

[0051] S102, S104, S106, S108, S110, S111, S112, S114...steps

[0052] S1…Shortest distance

[0053] T1, T2, T31...Thickness

[0054] T21…First thickness

[0055] T22…Second thickness

[0056] W1…Width DETAILED DESCRIPTION

[0057] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only to illustrate, not to limit in any way. Various embodiments in the present invention may use repeated reference symbols and / or text notes. The use of these repeated reference symbols and notes is to make the description more concise and clear, rather than to indicate the relevance between different embodiments and / or configurations.

[0058] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "down", "above", "on", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the orientation of each element during use and operation. As the orientation of each element is different (rotated 90 degrees or other orientations), the related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0059] Although the present invention uses the terms first, second, third, etc. to describe elements, components, regions, layers, and / or blocks (Section), it should be understood that these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not imply or represent any previous ordinal number of the element, nor do they represent the order of arrangement of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0060] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0061] The terms "coupling", "coupling", and "electrical connection" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0062] Although the invention of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of ordinary technicians in the relevant technical field.

[0063] Figure 1 FIG. 1 is a top view of a semiconductor device arrangement structure according to an embodiment of the present invention and an enlarged view of a local area. Figure 1 As shown, the semiconductor device arrangement structure 1000 includes a carrier 100, an adhesive layer 200, and a plurality of semiconductor devices 110. The adhesive layer 200 is continuously distributed on the surface of the carrier 100 and is disposed between the carrier 100 and the semiconductor devices 110, so that the semiconductor devices 110 can be attached to the adhesive layer 200. The plurality of semiconductor devices 110 are separated from each other and can be arranged in a regular or irregular pattern.

[0064] According to one embodiment of the present invention, the carrier 100 is used to support the semiconductor element 110 disposed on its surface, so the carrier 100 and the adhesive layer 200 can constitute a supporting substrate (or called a second supporting substrate). According to one embodiment of the present invention, the carrier 100 can be a non-epitaxial material or a non-growth substrate, for example, it can be a ceramic substrate, a metal substrate, a glass substrate, a thermal release tape (Thermal Release Tape), a UV Release Tape, a chemical release tape (Chemical Release Tape), a heat-resistant tape, a blue tape (Blue Tape), or a tape with a dynamic release layer (Dynamic Release Layer; DRL). According to one embodiment of the present invention, the carrier 100 can be a glass substrate, a sapphire substrate, or a quartz substrate. The carrier 100 is a substrate that can be penetrated by laser or incoherent light, so that the semiconductor element 110 can be separated from the carrier 100 by a laser lift-off (Laser Lift-Off; LLO) manufacturing process. According to one embodiment, when performing a laser lift-off process, if the adhesive layer 200 is disposed on the front side of the carrier 100, the laser can be incident into the carrier 100 from the back side of the carrier 100, irradiate the adhesive layer 200, and then penetrate out from the front side of the carrier 100. After being irradiated by the laser, the adhesive layer 200 will partially expand, thereby pushing the semiconductor element 110 to separate from the carrier 100. In addition, the carrier 100 is electrically insulated from the semiconductor element 110, so that electrical signals will not be transmitted between the carrier 100 and the semiconductor element 110.

[0065] The semiconductor element 110 may include a light emitting element or a non-light emitting element. The light emitting element is, for example, a light emitting diode or a laser diode. The non-light emitting element is, for example, a transistor. The plurality of semiconductor elements 110 may have different, identical or similar structures and sizes. According to one embodiment, each semiconductor element 110 has a projected area of ​​about 50 μm in the Z direction. 2 Up to 5000μm 2 Adjacent semiconductor elements 110 are separated from each other, and in the same row or column, the shortest distance between two adjacent semiconductor elements 110 is 1 μm to 50 μm.

[0066] Referring to the enlarged view of the local area R1, two semiconductor elements 110 (e.g., the first semiconductor element 110-1 and the second semiconductor element 110-2) are adjacent to each other and each has a length L1 and a width W1. The length L1 is greater than the width W1, and the length L1 is 10 μm to 50 μm, and the width W1 is 5 μm to 30 μm. The shortest distance S1 between the first semiconductor element 110-1 and the second semiconductor element 110-2 is less than the width W1 of the first semiconductor element 110-1 and the second semiconductor element 110-2, and the shortest distance S1 is greater than 1 / 5 of the width W1.

[0067] Figure 2 An embodiment of the present invention is along the Figure 1 The cross-sectional view shown by the section line AA'. In the cross-sectional view, the carrier 100 has a front side 102 and a back side 104 opposite to each other. The adhesive layer 200 is disposed on the front side 102 of the carrier 100 and is a continuously distributed single-layer structure. The exposed surface of the adhesive layer 200 (i.e., the area not shielded by the semiconductor element) has a uniform thickness T1, for example, 50nm to 2μm, and the thickness variation value between any two points on the exposed surface of the adhesive layer 200 is not greater than 15%. For example, the thickness variation value can be obtained by the following formula (1):

[0068]

[0069] Wherein, t1 and t2 are the thicknesses of any two points on the exposed surface of the adhesive layer 200 .

[0070] In addition, for the exposed surface of the adhesive layer 200, the adhesive layer 200 does not include any cutting marks. According to one embodiment, the adhesive layer 200 is a single-layer elastomer that does not have fluidity at room temperature (e.g., 25°C) and normal pressure (1 atmosphere), and still has appropriate adhesion. Therefore, when other components are disposed on the exposed surface of the adhesive layer 200, the components can be attached to the adhesive layer 200.

[0071] In the present invention, "elastomer" refers to a polymer that exhibits elasticity. "Elastic" or "elastomeric" means that when a tensile force is applied to a material, its overall length can be increased and has an elongated length, which is at least about 160% of the original length of the material without breaking or rupturing. When the applied tensile force is released, the overall length of the material may have a recovered length, which is at least about 65% of its elongated length, so the recovered length is 103% to 120% of the original length or any value therein. In addition, in all directions, after being subjected to an external force, when the elastic force is restored, the ratio of the recovered length of the elastomer to the original length is substantially equal. The adhesive layer 200 may include silicone resin or photodegradable adhesive, such as ultraviolet light degradable adhesive.

[0072] The adhesive layer 200 includes a selected area 232 and an unselected area 234. The physical and chemical properties of the selected area 232 and the unselected area 234 are substantially the same, that is, the adhesion, light transmittance, degree of crosslinking, and composition of the selected area 232 and the unselected area 234 are substantially the same. However, the so-called selected area 232 refers to an area that will be activated by a stimulus (such as a light source or a heat source) at a certain point in the manufacturing process, and the unselected area 234 refers to an area that will not be activated by the stimulus at that point in the manufacturing process. According to one embodiment, at a certain point in the manufacturing process, some areas of the adhesive layer 200 will belong to the unselected area 234, but at other points in the manufacturing process, these areas may belong to the selected area 232, depending on actual needs. The carrier 100 is used to support the semiconductor device 110 disposed on its surface, so the carrier 100 and the adhesive layer 200 together constitute a supporting substrate 500.

[0073] The semiconductor element 110 is attached to the surface of the adhesive layer 200. The semiconductor element 110 includes a first semiconductor element 110-1 to a fourth semiconductor element 110-4, wherein the first semiconductor element 110-1 to the third semiconductor element 110-3 are attached to the unselected region 234 of the adhesive layer 200. The fourth semiconductor element 110-4 is attached to the selected region 232 of the adhesive layer 200. According to an embodiment of the present invention, the semiconductor elements 110 located in the unselected region 234, such as the first semiconductor element 110-1 to the third semiconductor element 110-3, may be referred to as unselected semiconductor elements, and the semiconductor elements 110 located in the selected region 232, such as the fourth semiconductor element 110-4, may be referred to as selected semiconductor elements. In a subsequent transfer manufacturing process, the fourth semiconductor element 110-4 in the selected region 232 will be transferred to a target substrate, while the first semiconductor element 110-1 to the third semiconductor element 110-3 in the unselected region 234 remain on the original carrier 100. According to one embodiment, all unselected regions 234 become selected regions 232 at different manufacturing process points, so all semiconductor devices 110 can be transferred to other target substrates simultaneously or sequentially. Depending on actual needs, these semiconductor devices 110 can be transferred to the same or different target substrates.

[0074] The front side 110a of the semiconductor element 110 faces the adhesive layer 200, and the back side 110b of the semiconductor element 110 is away from the adhesive layer 200. Each semiconductor element 110 includes an element body 120 and at least one electrode 122, for example, two electrodes 122. The element body 120 includes a semiconductor layer through which electrons or holes can flow. The electrodes 122 face and adhere to the adhesive layer 200, and a portion of each electrode 122 may be sunken into the adhesive layer 200. The electrode 122 may include a single-layer or multi-layer metal structure, and the electrode 122 includes at least one material selected from the group consisting of chromium (Cr), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), and copper (Cu).

[0075] According to one embodiment of the present invention, the semiconductor element 110 is a semiconductor light-emitting element, and the element body 120 of the first semiconductor element 110 includes a semiconductor stack. The semiconductor stack may include a plurality of recessed areas away from the carrier 100. The opening diameter of each recessed area is 1 μm to 4 μm, and the depth is 300 nm to 2 μm. The recessed areas have a repeated shape and are distributed on the back side 110b of the semiconductor element 110 (distributed along the XY plane). By providing the recessed areas, the luminous efficiency of the semiconductor element 110 can be increased or the profile of the light distribution curve can be adjusted. The semiconductor stack of the element body 120 can be electrically connected to the electrode 122. The semiconductor stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer in sequence, wherein the first semiconductor layer and the second semiconductor layer respectively include dopants of different conductive types, such as n-type dopants and p-type dopants, so that the first semiconductor layer and the second semiconductor layer can supply electrons and holes respectively.

[0076] The structure of each semiconductor element 110 is not limited to Figure 2 According to the structure shown in one embodiment, each semiconductor element 110 includes a growth substrate (not shown) disposed on the back side of the element body 120, and a redistribution layer (RDL) (not shown) disposed on the bottom surface of the element body 120. The redistribution layer includes conductive interconnects, vias, and conductive pads. The conductive pads may have a specific layout pattern, and in the subsequent manufacturing process, the conductive pads may be electrically connected to the external circuit. In addition, according to one embodiment, each semiconductor element 110 may include a fan-out package structure, so that the element body 120 includes at least one semiconductor element and a molding material surrounding the chip, but is not limited thereto.

[0077] Figure 3 An embodiment of the present invention Figure 2 A magnified view of a local area. Figure 3 As shown, in the local area R2, the entirety of each electrode 122 of each semiconductor element 110 has an average thickness T2, for example, 200nm to 2μm. A portion of each electrode 122 is buried in the adhesive layer 200 and has a first thickness T21 (or depth), which is 0.02-0.5μm. The other portion of each electrode 122 is exposed from the adhesive layer 200 and has a second thickness T22, which is 0.04-1.55μm.

[0078] The surface of the adhesive layer 200 includes a recessed area for accommodating the electrode 122, and the first depth D1 of the recessed area is the same as the thickness T21 (or depth) of the electrode 122 buried in the adhesive layer 200. The adhesive layer 200 may have shielding portions 202 and exposed portions 204 that are alternately arranged. The shielding portions 202 may be shielded by the semiconductor element 110, and the exposed portions 204 are exposed from the semiconductor element 110. The physical and chemical properties of the shielding portions 202 and the exposed portions 204 are substantially the same, that is, the adhesion, light transmittance, cross-linking degree, and composition of the shielding portions 202 and the exposed portions 204 are substantially the same. However, since the surface of the shielding portion 202 includes a recessed area for accommodating the electrode 122, the average thickness of the shielding portion 202 may be slightly less than or substantially equal to the average thickness of the exposed portion 204.

[0079] Taking the shielding portion 202 and the exposed portion 204 corresponding to the first semiconductor element 110-1 as an example, the shielding portion 202 and the exposed portion 204 are located in the unselected area of ​​the adhesive layer 200, and the corresponding shielding portion 202 is shielded by the first semiconductor element 110-1 and has a first average thickness. In a top view, the corresponding shielding portion 202 can be surrounded by the adjacent exposed portion 204, and the adjacent exposed portion 204 has a second average thickness. The ratio of the first average thickness of the shielding portion 202 to the second average thickness of the exposed portion 204 is 0.96 to 1.00.

[0080] According to one embodiment, the adhesive layer 200 is silicone resin or ultraviolet light debonding adhesive. When a laser beam of a specific wavelength (e.g., a wavelength of 193nm) is irradiated to a selected area or an unselected area of ​​the adhesive layer 200, the irradiated adhesive layer 200 will be heated and expanded, for example, 10% to 30% in the longitudinal direction. This expansion will reduce the volume of the recessed area on the surface of the adhesive layer 200, thereby reducing the contact area between the electrode 122 of the corresponding semiconductor element 110 and the adhesive layer 200, thereby reducing the adhesion between the two. On the other hand, since the irradiated adhesive layer 200 is heated rapidly in a very short time (e.g., less than 2 seconds), it will expand rapidly and can generate a thrust on the corresponding semiconductor element 110, such as a thrust greater than or equal to 25gf, so that the semiconductor element 110 is separated from the adhesive layer 200. The value of this thrust is only for example, and its actual value will vary depending on the laser energy and the material of the adhesive layer 200, so the thrust size can be further adjusted according to actual needs.

[0081] Figure 4 Another embodiment of the present invention corresponds to Figure 2 A magnified view of a local area. Figure 4 The structure is similar to Figure 3 The main difference between the structures shown is that Figure 4The back side 110b of the semiconductor element 110 faces the adhesive layer 200, so that a portion of the element body 120 is buried in the adhesive layer 200, and the thickness T31 (or depth) of the portion is 0.02-0.5 μm, and the front side 110a (this surface includes the electrode 122) of the semiconductor element 110 is away from the adhesive layer 200. The surface of the adhesive layer 200 includes a recessed area for accommodating the element body 120 of the semiconductor element 110, and the first depth D1 of the recessed area is the same as the thickness T31 (or depth) of the element body 120 buried in the adhesive layer 200.

[0082] Figure 5 Another embodiment of the present invention corresponds to Figure 2 A magnified view of a local area. Figure 5 The structure is similar to Figure 3 The main difference between the structures shown is that Figure 5 The back side 110b of the semiconductor element 110 is covered by the adhesive portion 210. According to different embodiments, the adhesive portion 200 is composed of a cross-linked and cured polymer, such as polyimide (PI), epoxy (EPO), polybenzoxazole (PBO), silicone (Polysiloxane), cycloolefin (COP), or benzocyclobutane (BCB), but is not limited thereto.

[0083] Figure 6 FIG. 1 is a top view of a semiconductor device arrangement structure according to an embodiment of the present invention. Figure 6 As shown, Figure 6 The structure shown is similar to Figure 1 The main difference of the structure shown is that the semiconductor device 110 originally located on the selected area 232 of the adhesive layer 200 has been transferred to another supporting substrate (or target substrate), so that the selected area 232 of the adhesive layer 200 is exposed.

[0084] Figure 7 An embodiment of the present invention is along the Figure 6 The cross-sectional view shown by the section line BB'. Figure 2 and Figure 7 , Figure 7 The structure shown is similar to Figure 2The main difference of the structure shown is that the fourth semiconductor element 110-4 originally located on the selected area 232 of the adhesive layer 200 is transferred to another target substrate, so that the selected area 232 of the adhesive layer 200 is exposed. At this time, the surface of the selected area 232 includes a concave mark 220, such as a concave mark 220 corresponding to the electrode 122.

[0085] Figure 8 An embodiment of the present invention Figure 7 The enlarged view of the local area R3. Figure 3 and Figure 8 , the concave mark 220 is located on the surface of the selected area 232 of the adhesive layer 200. The second depth D2 of the concave mark 220 is smaller than the thickness T2 of the electrode 122, and also smaller than the first thickness T21 (or depth) of the electrode 122 buried in the adhesive layer 200. The cross-sectional profile of the concave mark 220 is a scaled copy of the cross-sectional profile of the electrode 122.

[0086] In more detail, according to one embodiment, when a laser beam of a specific wavelength (e.g., a wavelength of 193 nm) is irradiated to a selected area of ​​the adhesive layer 200, the irradiated adhesive layer 200 will be heated and expanded, so that the selected semiconductor element will be separated from the adhesive layer 200. Subsequently, when the laser is removed, a recessed mark 220 after elastic recovery will remain on the surface of the adhesive layer 200. According to the above description, in all directions, after being subjected to an external force, when the elastic force is restored, the ratio of the restored length of the elastic body to the original length is substantially equal. Therefore, the cross-sectional profile of the recessed mark 220 will be similar to the cross-sectional profile of the embedded area of ​​the electrode 122, but the size of the cross-sectional profile of the recessed mark 220 will be smaller than the size of the cross-sectional profile of the embedded area of ​​the electrode 122.

[0087] In order to enable those skilled in the art to implement the invention, the method for manufacturing the semiconductor element arrangement structure of the invention is further described in detail below.

[0088] Fig. 9 1 is a cross-sectional view of different stages of a manufacturing process for transferring a plurality of semiconductor elements from a first supporting substrate to a second supporting substrate according to an embodiment of the present invention. Fig. 9As shown, in step S102, a first supporting substrate 400 and a plurality of semiconductor elements 110 are provided, and the semiconductor elements 110 are arranged on the front side 402 of the first supporting substrate 400. According to one embodiment of the present invention, the first supporting substrate 400 is a growth substrate, and the semiconductor elements 110 are grown on the growth substrate. The growth substrate includes an epitaxial material, such as silicon (Si), germanium (Ge), lithium aluminate (LiAlO2), zinc oxide (ZnO), silicon carbide (SiC), sapphire (Sapphire), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium phosphide (InP), but is not limited thereto. According to one embodiment, the first supporting substrate 400 includes a non-epitaxial material or a non-growth substrate. When the first supporting substrate 400 includes a non-epitaxial material or a non-growth substrate, an adhesive portion (e.g. Figure 5 The adhesive portion 210 is shown in FIG. 1 . The adhesive portion is used to fix the semiconductor device 110 to the first supporting substrate 400 , and the adhesive portions are separated from each other.

[0089] Continuing with reference to step S102, the semiconductor element 110 on the first supporting substrate 400 is then placed facing the second supporting substrate 500, so that the electrode 122 of the semiconductor element 110 faces the adhesive layer 200 of the second supporting substrate 500. According to one embodiment, the second supporting substrate 500 has a front side 502 and a back side 504 opposite to each other, the front side 502 faces the first supporting substrate 400, and the back side 504 is away from the first supporting substrate 400. The second supporting substrate 500 can be a non-epitaxial material or a non-growth substrate. According to one embodiment, the second supporting substrate 500 includes a carrier 100 and an adhesive layer 200. The carrier 100 has sufficient mechanical strength to support the adhesive layer 200. The adhesive layer 200 is a single-layer structure and has sufficient adhesion to fix the components pressed onto its surface. According to one embodiment, the adhesive layer 200 of the second supporting substrate 500 is manufactured by, for example, spin coating to apply liquid adhesive material to the front surface 102 of the carrier 100, and then soft-baking and hard-baking to form an adhesive layer 200 without fluidity and having a cross-linked structure.

[0090] In step S104, at least one of the first support substrate 400 and the second support substrate 500 is moved so that the semiconductor element 110 contacts the second support substrate 500 and is fixed to the adhesive layer 200. According to one embodiment, the semiconductor element 110 can be fixed to the adhesive layer 200 of the second support substrate 500 by a pressing process or a heating process. A portion of the electrode 122 is buried in the adhesive layer 200, and the depth of the electrode 122 buried in the adhesive layer 200 is 0.02 to 0.5 μm. When performing step S104, the electrode 122 applies pressure to the adhesive layer 200. If the adhesive layer 200 is an elastomer, it will elastically deform when subjected to an external force, so that the electrode 122 is conformally buried in the adhesive layer 200, thereby relieving the pressure from the electrode 122.

[0091] In step S104 and step S106, a separation process is performed to separate the first support substrate 400 from the semiconductor element 110, thereby exposing the back side 110b of the semiconductor element 110. According to one embodiment, when the support substrate 400 is a growth substrate, a laser lift-off process can be used to irradiate a laser from the back side 404 of the first support substrate 400 to the front side 402 to decompose the semiconductor material between the semiconductor element 110 and the first support substrate 400, such as gallium nitride, aluminum nitride, aluminum gallium nitride, or other compound semiconductor materials. In addition, when the support substrate 400 is a non-growth substrate, a laser lift-off process can also be used to irradiate a laser from the back side 404 of the first support substrate 400 to the front side 402 to decompose or vaporize the adhesive portion between the semiconductor element 110 and the first support substrate 400, thereby separating the semiconductor element 110 from the first support substrate 400. When step S106 is completed, a portion of the semiconductor elements 110 (e.g., the first semiconductor element 110 - 1 and the third semiconductor element 110 - 3 ) will be attached to the unselected region 234 of the adhesive layer 220 , and another portion of the semiconductor elements 110 (e.g., the fourth semiconductor element 110 - 4 ) will be attached to the selected region 232 of the adhesive layer 220 .

[0092] Next, referring to step S108, the first support substrate 400 is removed, and when the first support substrate 400 is a growth substrate, a cleaning process may be performed on the semiconductor element 110 to remove semiconductor residues or metal residues, such as gallium-containing particles, remaining on the back surface 110b of the semiconductor element 110. Therefore, it is possible to prevent the semiconductor element 110 from being affected in light extraction efficiency by residues with low light transmittance. According to one embodiment, the back surface 110b of the semiconductor element 110 may be covered by the adhesive portion 210, and may appear similar to Figure 5 The structure shown.

[0093] Through implementation Fig. 9In step S106 to step S108, the plurality of semiconductor elements 110 are transferred from the first support substrate 400 to the second support substrate 500. The plurality of semiconductor elements 110 are located on the second support substrate 500 and are separated from each other. According to one embodiment, the arrangement of the semiconductor elements 110 on the first support substrate 400 is similar or the same as the arrangement of the semiconductor elements 110 on the second support substrate 500. According to one embodiment, the structure of the local area R3 may be similar to Figures 3 to 5 The structure of the local area R2.

[0094] After completing the arrangement structure shown in step S108, the selected semiconductor elements 110 on the second support substrate 500 can be further selectively transferred to another support substrate (or target substrate) to group the semiconductor elements 110 with similar or identical electrical or optical specifications. The steps are similar to those shown in FIG. Fig.10 shown.

[0095] Fig.10 It is a cross-sectional schematic diagram of different manufacturing process stages of transferring a semiconductor element from a second supporting substrate to a third supporting substrate according to an embodiment of the present invention. In step S110, the semiconductor element 110 on the carrier 100 is facing the third supporting substrate 600 (or referred to as the target substrate). According to one embodiment, the third supporting substrate 600 has a front side 602 and a back side 604 relative to each other, the front side 602 faces the carrier 100, and the back side 604 is away from the carrier 100. According to one embodiment, the third supporting substrate 600 includes a carrier 612 and an adhesion layer 614. The carrier 612 can be a non-epitaxial material or a non-growth substrate, which has sufficient mechanical strength to support the adhesion layer 614. The adhesion layer 614 has sufficient adhesion to fix the components pressed to its surface. The material of the adhesion layer 614 can be the same as or different from the material of the carrier 612. Fig. 9 The material of the adhesive layer 200 shown depends on actual needs.

[0096] Next, in step S112, when the semiconductor element 110 is not in contact with the surface of the third supporting substrate 600, the selected area 232 of the adhesive layer 200 is enabled by the stimulus source E1, so that the volume of the selected area 232 rapidly expands, thereby reducing the adhesion between the fourth semiconductor element 110-4 (or the selected semiconductor element) and the adhesive layer 200. In addition, the selected area 232 of the adhesive layer 200 may also generate a thrust on the fourth semiconductor element 110-4 during the rapid expansion process. According to one embodiment, the "stimulus source" is, for example, a light source or a heat source, and the "enabling" refers to irradiating the adhesive layer 200 with the stimulus source E1, so that the volume of the irradiated area of ​​the adhesive layer 200 expands.

[0097] According to one embodiment, in step S112, the stimulus source E1 is a laser beam having a specific wavelength (e.g., a wavelength of 193 nm, or a lower value). By irradiating the selected area 232 of the adhesive layer 200 with the above-mentioned laser beam, the irradiated selected area 232 can be heated up and expanded, for example, by 10% to 30% in the longitudinal direction. This expansion reduces the volume of the recessed area on the surface of the selected area 232, thereby reducing the contact area between the electrode 122 of the fourth semiconductor element 110-4 and the adhesive layer 200. When the contact area between the electrode 122 and the adhesive layer 200 is reduced, the adhesion between the electrode 122 and the adhesive layer 200 is reduced. When the fourth semiconductor element 110-4 is subjected to an external force (e.g., gravity), it can be separated from the selected area 232.

[0098] In step S112 and step S114, the irradiated adhesive layer 200 can heat up and expand rapidly in a very short time (for example, less than 2 seconds), and generate a thrust, for example, a thrust of 25 gf, on the fourth semiconductor element 110-4 attached to the selected area 232, so that the fourth semiconductor element 110-4 is separated from the selected area 232 of the adhesive layer 200 and transferred to the surface 602 of the third supporting substrate 600. It should be noted that the above thrust value is only an example, and its actual value will vary depending on the laser energy and the material of the adhesive layer 200, so the thrust size can be further adjusted according to actual needs. After the fourth semiconductor element 110-4 is transferred to the surface 602 of the third supporting substrate 600, the structure of the local area R2 can be similar to Figure 8 At this time, the surface of the selected area 232 of the adhesive layer 200 may have a similar Figure 8 The recessed trace 220 is shown. In contrast, since the unselected area 234 is not enabled, the first semiconductor device 100 - 1 and the third semiconductor device 100 - 3 can still be attached to the unselected area 234 of the adhesive layer 200 without being transferred to the surface 602 of the third supporting substrate 600 .

[0099] Since the adhesive layer 200 is a single-layer elastic body, when the temperature of the selected area 232 is increased, it is easy to deform accordingly, so that the interior of the selected area 232 is not easy to be delaminated or cracked, and no cavity is generated between the selected area 232 and the carrier 100. Therefore, even if the above-mentioned enabling manufacturing process is implemented, the selected area 232 can still be attached to the carrier 100, thereby avoiding contamination caused by cracking or peeling of the adhesive layer 200.

[0100] According to one embodiment, in a subsequent manufacturing process, other semiconductor elements 110 (for example, the first semiconductor element 110-1 and the third semiconductor element 110-3) can continue to be transferred from the second supporting substrate 500 to other supporting substrates or target substrates, and the transfer manufacturing process can be repeated until all the semiconductor elements 110 located on the second supporting substrate 500 are transferred to the selected same and / or different supporting substrates or target substrates.

[0101] According to one embodiment, the back surface 110b of each semiconductor element 110 may be provided with an adhesive portion (eg Figure 5 The adhesive portion 210 is shown in the figure, so that the adhesive portion is located between each semiconductor element 110 and the third supporting substrate 600 and is attached to the surface of the adhesive layer 614. Since the electrode 122 is not covered by the adhesive portion, the electrical performance of the semiconductor element 110 is not affected even if it is not removed.

[0102] Fig.11 It is a cross-sectional schematic diagram of different manufacturing process stages of transferring a semiconductor element from a second supporting substrate to a third supporting substrate according to another embodiment of the present invention. Fig.11 The production process steps are similar to Fig.10 The main difference of the manufacturing process steps shown is that the adhesive layer 200 is a photo-degradable adhesive, and between the execution time points of step S110 and step S112, step S111 may be additionally performed to irradiate the entire adhesive layer 200 (including the selected area 232 and the unselected area 234) with a light source E2, such as ultraviolet light, to reduce the overall adhesion of the adhesive layer 200, so that the fourth semiconductor element 100-4 located on the selected area 232 is more easily transferred to the third supporting substrate 600 via the subsequent step S112. According to one embodiment, the adhesive layer 200 is a UV-degradable adhesive. The UV-degradable adhesive may be a block copolymer containing acrylic acid, such as a block copolymer of methyl methacrylate-acrylate-methyl methacrylate (MAM). The main chain of the block copolymer includes crosslinkable functional groups. When the UV-sensitive adhesive is irradiated with ultraviolet light, adjacent crosslinkable functional groups undergo a crosslinking reaction, thereby increasing the Young's modulus of the UV-sensitive adhesive and reducing the adhesiveness of the UV-sensitive adhesive.

[0103] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device arrangement structure, comprising: Carrier; A plurality of semiconductor elements are separated from each other and are located on the carrier, and each of the semiconductor elements comprises an electrode; and An adhesive layer is disposed between the carrier and the semiconductor elements, and the semiconductor elements are attached to the adhesive layer, wherein: The adhesive layer is a continuously distributed single-layer structure and comprises: A selected area and a plurality of unselected areas, the unselected areas are respectively covered by the semiconductor elements, and the selected area is not covered by the semiconductor elements; as well as A concave mark is located on the surface of the selected area. In the cross-sectional view, the outline of the concave mark is a scaled view of the outline of the electrode, and the depth of the concave mark is less than the thickness of the electrode.

2. The semiconductor device arrangement structure according to claim 1, wherein: The semiconductor elements at least include a first semiconductor element and a second semiconductor element. The first semiconductor element and the second semiconductor element each have a width. The first semiconductor element and the second semiconductor element are adjacent to each other. The shortest distance between the first semiconductor element and the second semiconductor element is less than the width and greater than 1 / 5 of the width.

3. The semiconductor device arrangement structure according to claim 1, wherein: A portion of the electrode is buried in the adhesive layer, and the depth of the portion is 0.02-0.5 μm.

4. The semiconductor device arrangement structure according to claim 1, wherein: The adhesive layer comprises: a shielding portion located in one of the unselected regions and shielded by the corresponding semiconductor element, the shielding portion having a first average thickness; and an exposed portion located in the one of the unselected regions, surrounding the shielding portion and exposed from the corresponding semiconductor element, the exposed portion having a second average thickness, Wherein, the ratio of the first average thickness to the second average thickness is 0.96-1.

00.

5. The semiconductor device arrangement structure according to claim 1, wherein: When the unselected area of ​​the adhesive layer is irradiated with a laser having a wavelength of 193 nm, the volume of the irradiated unselected area of ​​the adhesive layer expands, thereby generating a thrust greater than or equal to 25 gf on the corresponding semiconductor elements.

6. A method for manufacturing a semiconductor device arrangement structure, comprising: Providing a carrier, wherein an adhesive layer is disposed on the surface of the carrier, wherein the adhesive layer is a single-layer elastomer; attaching a semiconductor device to a selected area of ​​the adhesive layer; providing a target substrate having a surface facing the semiconductor element and not contacting the semiconductor element; as well as The selected area of ​​the adhesive layer is enabled to release the semiconductor element from the adhesive layer and transfer it to the surface of the target substrate, wherein when the selected area of ​​the adhesive layer is enabled, the selected area of ​​the adhesive layer is still attached to the carrier.

7. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: When the adhesive layer is the UV-degradable adhesive, before enabling the selected area of ​​the adhesive layer, the method further comprises: The ultraviolet light-debonding adhesive is irradiated with ultraviolet light to reduce the adhesiveness of the ultraviolet light-debonding adhesive.

8. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: The semiconductor element comprises at least one electrode, a part of which is buried in the adhesive layer, and the depth of the part is 0.02-0.5 μm.

9. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: When enabling the selected area of ​​the adhesive layer, the method includes irradiating the selected area of ​​the adhesive layer with a laser.

10. The method for manufacturing the semiconductor device arrangement structure according to claim 6, further comprising: Before providing the target substrate, attaching another semiconductor device to the unselected area of ​​the adhesive layer; and After enabling the selected area of ​​the adhesive layer, the other semiconductor device is still attached to the unselected area of ​​the adhesive layer.

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