Gate and method of making same

Abstract

The present disclosure relates to a gate tube and a manufacturing method thereof. The gate tube comprises a first electrode, a gate layer disposed on the first electrode, a bottom surface of the gate layer being in contact with the first electrode, a second electrode disposed on the gate layer, a top surface of the gate layer being in contact with the second electrode, and a passivation layer covering at least a sidewall of the gate layer, a thermal conductivity of the passivation layer being less than that of the gate layer, and an electrical conductivity of the passivation layer being less than that of the gate layer. The passivation layer can hinder heat transfer from the gate tube to the external environment, so that the gate layer can be heated up faster, the gate tube can reach an opening temperature faster, the gate tube opening time is shortened, the gate tube opening voltage is reduced, the gate tube reading voltage is also reduced, which is beneficial to reduce the leakage current of the gate tube; the passivation layer has low thermal conductivity and good insulation performance, which can further reduce the risk of leakage of the gate tube, avoid current flowing between different devices, and thus avoid electrical crosstalk between devices.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a gating tube and a manufacturing method thereof. BACKGROUND

[0002] Under the background of the big data era, the vigorous development of smart cities and other frontier technologies such as autonomous driving has put forward more stringent requirements for data storage devices, including faster data access speed, lower energy consumption, and higher storage capacity. However, the current traditional storage technology is facing many challenges and is difficult to meet these needs. The traditional storage is difficult to match the data processing speed of the processor in terms of read and write speed, which has become a key factor restricting the overall performance improvement of the system. The traditional storage such as DRAM needs to refresh the charge continuously when working, which not only leads to high energy consumption, but also increases the complexity and maintenance cost of the system. In addition, with the continuous shrinking of process nodes, the production cost and process complexity of the storage are rising sharply, which further limits the improvement of storage density.

[0003] As a kind of nonlinear threshold switch device, the gating tube has attracted much attention due to its simple structure, low energy consumption, easy integration and flexible design. When the gating tube forms a storage unit with the storage and realizes three-dimensional integration, it provides a new solution for storage and neuromorphic computing systems.

[0004] However, although the gating tube has the advantages of low power consumption, high switching speed and high-density integration, it will have a leakage current of uA level in the non-conductive state. This leakage current problem not only leads to a significant increase in energy consumption in large-scale integrated circuits, but also may affect the non-volatile characteristics of the storage, causing the storage to lose stored data without power supply. In addition, in order to reduce the leakage current, more complex manufacturing processes may be required, which will undoubtedly increase the production cost and process complexity, thereby limiting the development and application of the gating tube. SUMMARY

[0005] Therefore, it is necessary to provide a gating tube and a manufacturing method thereof to solve the problems of leakage current, high production cost and process complexity of the gating tube in the prior art.

[0006] In a first aspect, the present disclosure provides a gating tube, comprising:

[0007] a first electrode;

[0008] a gating layer disposed on the first electrode, a bottom surface of the gating layer being in contact with the first electrode;

[0009] a second electrode disposed on the gating layer, a top surface of the gating layer being in contact with the second electrode;

[0010] A passivation layer covering at least sidewalls of the gating layer, the passivation layer having a thermal conductivity less than that of the gating layer and an electrical conductivity less than that of the gating layer.

[0011] Optionally, the passivation layer also covers a top surface of the gating layer not covered by the second electrode.

[0012] Optionally, the passivation layer also covers a bottom surface of the gating layer not covered by the first electrode.

[0013] Optionally, the passivation layer has a thermal conductivity of 0.1 W / m·K-25 W / m·K; and an electrical conductivity of 10 - 8 S / m to 10 -16 S / m;

[0014] The material of the passivation layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

[0015] Optionally, the gating tube is disposed on a substrate, a top surface of the substrate being covered with a first dielectric layer.

[0016] The first electrode is disposed in the first dielectric layer, the first electrode extending from a top surface of the first dielectric layer to a top surface of the substrate; the gating layer and the second electrode are sequentially stacked on a side of the first electrode away from the substrate.

[0017] Optionally, a side of the first dielectric layer away from the substrate is provided with an insulating layer covering sidewalls of the gating layer and sidewalls of the second electrode, the insulating layer being separated from the gating layer by the passivation layer.

[0018] In a second aspect, the disclosure provides a method for manufacturing a gating tube, comprising:

[0019] Providing a substrate, a top surface of the substrate being covered with a first dielectric layer;

[0020] Forming a first hole in the first dielectric layer, and forming a first electrode in the first hole;

[0021] Forming a gating layer on the first electrode layer, a bottom surface of the gating layer being in contact with the first electrode;

[0022] Forming a passivation layer covering at least sidewalls of the gating layer and a top surface of the gating layer; the passivation layer having an electrical conductivity less than that of the gating layer;

[0023] Removing at least part of the passivation layer on the top surface of the gating layer to expose at least part of the top surface of the gating layer;

[0024] forming a second electrode covering exposed top surfaces of the gating layer, the second electrode being in contact with the top surfaces of the gating layer.

[0025] Optionally, before forming the first hole, a first passivation layer is formed covering top surfaces of the first dielectric layer, the first passivation layer and the first dielectric layer are etched to form the first hole; part of bottom surfaces of the gating layer is connected with the first passivation layer, the gating layer is separated from the first dielectric layer by the first passivation layer.

[0026] After forming the gating layer, a second passivation layer is formed covering sidewalls and top surfaces of the gating layer.

[0027] Optionally, the method further comprises:

[0028] forming an insulating layer covering the gating layer, the insulating layer being separated from the gating layer by the passivation layer.

[0029] exposing part of top surfaces of the gating layer by etching the insulating layer, forming a second hole, and forming the second electrode in the second hole.

[0030] Optionally, the passivation layer has a thermal conductivity of 0.1 W / m·K-25 W / m·K; the passivation layer has an electrical conductivity of 10 - 8 S / m to 10 -16 S / m.

[0031] The material of the passivation layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

[0032] The gating tube and the manufacturing method thereof of the present disclosure set the passivation layer on the sidewalls of the gating layer. On the one hand, the passivation layer has a smaller thermal conductivity than the gating layer, the passivation layer can hinder heat transfer from the gating tube to the external environment, so that the gating layer can be heated faster, the gating tube can reach the opening temperature faster, and the gating tube opening time is shortened. At the same time, since the heat is not easily dissipated, the gating tube can reach the opening condition at a lower voltage, the opening voltage of the gating tube is reduced, and the reading voltage of the gating tube is also reduced, which is beneficial to reduce the leakage current of the gating tube. On the other hand, the passivation layer has a low thermal conductivity and good insulation performance, which can further reduce the risk of leakage of the gating tube and avoid current flowing between different devices, thereby avoiding electrical crosstalk between devices. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to make the technical solutions in the embodiments of the present disclosure or the prior art clearer, the accompanying drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim to some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained from these accompanying drawings without any creative effort.

[0034] Figure 1 Structure diagram of a gate control tube provided in an embodiment;

[0035] Figure 2 Structure diagram of a gate control tube provided in another embodiment;

[0036] Figure 3 Structure diagram of a gate control tube provided in another embodiment;

[0037] Figure 4 Process flow diagram of a manufacturing method of a gate control tube provided in an embodiment;

[0038] Figure 5 Structure diagram of a substrate provided in an embodiment;

[0039] Figure 6 Structure diagram after forming a first passivation layer provided in an embodiment;

[0040] Figure 7 Structure diagram after forming a first hole provided in an embodiment;

[0041] Figure 8 Structure diagram after forming a first electrode in the first hole provided in an embodiment;

[0042] Figure 9 Structure diagram after forming a gate layer on the first electrode provided in an embodiment;

[0043] Figure 10 Structure diagram after forming a second passivation layer provided in an embodiment;

[0044] Figure 11 Structure diagram after forming an insulating layer provided in an embodiment;

[0045] Figure 12 Structure diagram after forming a second hole provided in an embodiment.

[0046] Explanation of reference signs:

[0047] 10, gate; 11, first electrode; 12, gate layer; 13, second electrode; 14, passivation layer; 141, first passivation layer; 142, second passivation layer; 15, insulation layer; 151, first insulation layer; 152, second insulation layer; 20, substrate; 20a, front device layer; 30, first dielectric layer; 101, first hole; 102, second hole. DETAILED DESCRIPTION

[0048] For the purpose of promoting an understanding of the disclosure, the disclosure will now be described more fully with reference to the associated drawings. The preferred embodiments of the disclosure are shown in the drawings. However, the disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

[0050] According to an exemplary embodiment, the disclosure provides a gate 10, as shown in Figure 1 , Figure 2 or Figure 3 , the gate 10 includes a first electrode 11, a gate layer 12 and a second electrode 13; the gate layer 12 is arranged on the first electrode 11, the bottom surface of the gate layer 12 is in contact with the first electrode 11; the second electrode 13 is arranged on the gate layer 12, the top surface of the gate layer 12 is in contact with the second electrode 13; the passivation layer 14 covers at least the sidewall of the gate layer 12, the thermal conductivity of the passivation layer 14 is less than the thermal conductivity of the gate layer 12, the electrical conductivity of the passivation layer 14 is less than the electrical conductivity of the gate layer 12.

[0051] The gate 10 of the embodiment, the passivation layer 14 is arranged on the sidewall of the gate layer 12, on the one hand, the passivation layer 14 has smaller thermal conductivity than the gate layer 12, the passivation layer 14 can hinder heat transfer from the gate 10 to the external environment, so that the gate layer 12 can be heated up faster, the gate 10 can reach the opening temperature faster, and the opening time of the gate 10 is shortened; at the same time, due to the difficulty of heat dissipation, the gate 10 can reach the opening condition at a lower voltage, the opening voltage of the gate 10 is reduced, and the reading voltage of the gate 10 is also reduced, which is beneficial to reduce the leakage current of the gate 10; on the other hand, the passivation layer 14 has low thermal conductivity and good insulation performance, which can further reduce the risk of leakage of the gate 10, avoid the flow of current between different devices, and thus avoid the electrical crosstalk between devices.

[0052] In some embodiments, with reference toFigure 1 , Figure 2 or Figure 3 As shown, the passivation layer 14 also covers the top surface of the gate layer 12 that is not covered by the second electrode 13. Thus, the passivation layer 14 can prevent heat transfer from the top surface of the gate layer 12 outwards, further limiting heat dissipation of the gate layer 12, thereby further increasing the heating rate of the gate layer 12, shortening the turn-on time of the gate transistor 10, reducing the turn-on voltage and read voltage of the gate transistor 10, reducing the leakage current of the gate transistor 10, and optimizing the switching performance of the gate transistor 10. Simultaneously, the passivation layer 14 covering the top surface of the gate layer 12 also enhances the protection effect of the passivation layer 14 on the gate layer 12, further reducing the risk of electrical crosstalk or short circuits between the gate layer 12 and other devices.

[0053] In some embodiments, refer to Figure 2 or Figure 3 As shown, the passivation layer 14 also covers the bottom surface of the gate layer 12 that is not covered by the first electrode 11. In this way, the passivation layer 14 can provide more comprehensive protection for the gate layer 12, optimize the thermal management of the gate layer 12, further optimize the switching performance of the gate transistor 10, and at the same time, the passivation layer 14 can reduce the risk of electrical crosstalk or short circuit between the gate layer 12 and other devices.

[0054] In some embodiments, the thermal conductivity of the passivation layer 14 is 0.1 W / m·K to 25 W / m·K; for example, the thermal conductivity of the passivation layer 14 can be 0.1 W / m·K, 1 W / m·K, 3 W / m·K, 5 W / m·K, 8 W / m·K, 10 W / m·K, 12 W / m·K, 13 W / m·K, 15 W / m·K, 18 W / m·K, 20 W / m·K, 22 W / m·K, or 25 W / m·K.

[0055] The conductivity of passivation layer 14 is 10. -8 S / m to 10 -16 S / m. For example, the conductivity of passivation layer 14 can be 10. -8 S / m, 10 -9 S / m, 10 -10 S / m, 10 -11 S / m, 10 -12 S / m, 10 -13 S / m, 10 -14 S / m, 10 -15 S / m or 10 -16 S / m.

[0056] In some embodiments, the material of the passivation layer 14 includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

[0057] It can be understood that the passivation layer 14 can include a single-layer structure or a multi-layer structure laminated on the surface of the gating layer 12.

[0058] In one example, the passivation layer 14 includes a silicon oxide layer. In another example, the passivation layer 14 includes a silicon oxide layer and a silicon nitride layer successively covering the surface of the gating layer 12. In yet another example, the passivation layer 14 includes a silicon oxide layer, a silicon nitride layer and a silicon carbide layer successively covering the surface of the gating layer 12.

[0059] In some embodiments, the material of the gating layer 12 can include at least one of niobium oxide (NbOx), vanadium oxide (VOx), OTS materials such as aluminum telluride, boron telluride, germanium selenide, germanium sulfide, antimony telluride, GeSeAsIn, GeSeAsN, GeSeCN.

[0060] The material of the first electrode 11 can include at least one of vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), ruthenium (Ru), ruthenium oxide (RuO), iridium (Ir), iridium oxide (IrO2), indium tin oxide (ITO), aluminum titanium nitride (TiAlN), aluminum nitride (AlNx), aluminum titanium nitride (TiAlN), hafnium (Hf) or copper (Cu).

[0061] The selection range of the material of the second electrode 13 is the same as that of the material of the first electrode 11, which will not be described here.

[0062] In some embodiments, as shown in Figure 1 , Figure 2 or Figure 3 , the gating tube 10 is arranged on a substrate 20, and the top surface of the substrate 20 is covered with a first dielectric layer 30. The first electrode 11 is arranged in the first dielectric layer 30, and the first electrode 11 extends from the top surface of the first dielectric layer 30 to the top surface of the substrate 20; the gating layer 12, the second electrode 13 are successively laminated on the side of the first electrode 11 away from the substrate 20.

[0063] Among them, the substrate 20 can be a semiconductor substrate, which is made of a semiconductor material, which can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); It can also be silicon on insulator (SOI), germanium on insulator (GOI); Or it can also be other materials with semiconductor properties, such as gallium arsenide and other III-V compounds.

[0064] Referring to Figure 1 , Figure 2 or Figure 3As shown, the substrate 20 includes one or more stacked front device layers 20a, which can be formed in or disposed on the substrate 20. Each of the front device layers 20a can include a plurality of semiconductor devices and a plurality of metal interconnect structures. The semiconductor devices can include at least one of a metal oxide semiconductor field effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode, an optical device, etc. A first dielectric layer 30 is disposed above the substrate 20, covering the front device layers 20a formed on the substrate 20.

[0065] In the present embodiment, the substrate 20 includes a memory formed thereon, which can be a resistive random access memory (RRAM), a dynamic random access memory (DRAM), a static random-access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a phase change random access memory (PCRAM), a magnetic random-access memory (MRAM), or other types of memory.

[0066] In some embodiments, the pass-gate transistor 10 is disposed one-to-one corresponding to the memory on the substrate 20, the first electrode 11 of the pass-gate transistor 10 extends from the top surface of the first dielectric layer 30 toward the substrate 20, and the first electrode 11 of the pass-gate transistor 10 is electrically connected to the corresponding memory. The pass-gate transistor 10 and the corresponding memory are integrated to form a memory cell of the 1S1R architecture. For example, the pass-gate transistor 10 can be connected in series with a new type of memory such as a resistive random access memory (RRAM), a phase change random access memory (PCRAM), a magnetic random-access memory (MRAM), and a ferroelectric random access memory (FeRAM) to form a memory cell.

[0067] In some embodiments, the memory is arranged in a plurality of columns in a direction perpendicular to the substrate 20, and the pass-gate transistor 10 is disposed one-to-one corresponding to the plurality of columns of memory on the substrate 20. The first electrode 11 of the pass-gate transistor 10 extends from the top surface of the first dielectric layer 30 toward the substrate 20, and the first electrode 11 of the pass-gate transistor 10 is connected to the selection wire of the corresponding column of memory. The pass-gate transistor 10 is used to control the selection of the corresponding column of memory. For example, the pass-gate transistor 10 can be connected in series with a NAND string to control the selection of a string of NAND strings.

[0068] In some embodiments, reference is made to Figure 1 ,Figure 2 or Figure 3 As shown, an insulating layer 15 is disposed on the side of the first dielectric layer 30 away from the substrate 20. The insulating layer 15 covers the sidewall of the gate layer 12 and the sidewall of the second electrode 13, and the insulating layer 15 is separated from the gate layer 12 by a passivation layer 14. The insulating layer 15 fills the spaces between adjacent gates 10 for electrical insulation between adjacent gates 10, preventing electrical crosstalk or short circuits between adjacent gates 10.

[0069] For example, the material of insulating layer 15 may include low-K materials with low dielectric constants such as porous silicon oxide, porous silicon oxyhydride, silicate glass, borosilicate glass, or silicon carbonitride.

[0070] For example, the insulating layer 15 may include a single-layer or multi-layer structure.

[0071] In some embodiments, refer to Figure 3 As shown, the insulating layer 15 includes a first insulating layer 151 and a second insulating layer 152 sequentially stacked on the first dielectric layer 30. The first insulating layer 151 fills the space between the selection layers 12 of adjacent selection tubes 10, and the second insulating layer 152 fills the space between the second electrodes 13 of adjacent selection tubes 10.

[0072] In some embodiments, the passivation layer 14 is further disposed between the insulating layer 15 and the first dielectric layer 30 to enhance the electrical insulation effect between the devices.

[0073] According to an exemplary embodiment, this disclosure provides a method for manufacturing a gated tube, such as... Figure 4 As shown, the manufacturing method of the selector tube includes the following steps:

[0074] Step S10: Provide a substrate 20, on which a first dielectric layer 30 is covered;

[0075] Step S20: A first hole 101 is formed on the first dielectric layer 30, and a first electrode 11 is formed in the first hole 101;

[0076] Step S30: A selection layer 12 is formed on the first electrode 11 layer, and the bottom surface of the selection layer 12 is in contact with the first electrode 11;

[0077] Step S40: Form a passivation layer 14, which at least covers the sidewalls of the gate layer 12 and the top surface of the gate layer 12; the conductivity of the passivation layer 14 is less than the conductivity of the gate layer 12.

[0078] Step S50: Remove at least a portion of the passivation layer 14 on the top surface of the gate layer 12 to expose at least a portion of the top surface of the gate layer 12;

[0079] Step S60: forming a second electrode 13, the second electrode 13 covers the exposed top surface of the gating layer 12, and the second electrode 13 is in contact with the top surface of the gating layer 12.

[0080] The manufacturing method of the gating tube in this embodiment, by forming the passivation layer 14 covering the sidewall of the gating layer 12, on the one hand, the passivation layer 14 has smaller thermal conductivity relative to the gating layer 12, the passivation layer 14 can hinder the heat transfer from the gating tube 10 to the external environment, so that the gating layer 12 can be heated up faster, the gating tube 10 can reach the opening temperature faster, and the gating tube 10 opening time is shortened; at the same time, due to the difficulty of heat dissipation, the gating tube 10 can reach the opening condition at a lower voltage, the opening voltage of the gating tube 10 is reduced, and the reading voltage of the gating tube 10 is also reduced, which is beneficial to reduce the leakage current of the gating tube 10; on the other hand, the passivation layer 14 has low thermal conductivity, and the passivation layer 14 has good insulation performance, which can further reduce the risk of leakage of the gating tube 10, avoid the current flowing between different devices, and avoid the electrical crosstalk between devices.

[0081] In step S10, referring to Figure 5 , the substrate 20 can be a semiconductor substrate made of a semiconductor material, which can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials with semiconductor properties, such as gallium arsenide and other group III-V compounds.

[0082] The substrate 20 includes one or more layers of stacked front device layers 20a, which can be formed in or on the substrate 20. Each semiconductor device layer can include a variety of semiconductor devices and a variety of metal interconnection structures. The semiconductor devices can include at least one of a metal oxide semiconductor field effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode, and an optical device. The first dielectric layer 30 is disposed above the substrate 20, and the first dielectric layer 30 covers the front device layer 20a formed on the substrate 20.

[0083] In this embodiment, the substrate 20 is formed with a memory, which can be RRAM, DRAM, SRAM, flash EPROM, FeRAM, PCRAM, MRAM or other types of memory.

[0084] In step S20, referring to Figure 6 , Figure 7First, a photoresist layer is formed on the top surface of the first dielectric layer 30, and a photoresist layer is exposed and developed to pattern the photoresist layer to define a pattern of the first electrode 11. The first dielectric layer 30 is etched according to the patterned photoresist layer to form a first hole 101 exposing a top surface of a corresponding memory of the front device layer 20a.

[0085] Then, referring to Figure 8 The conductive material can be deposited by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD), an atomic layer deposition (ALD), or an electroplating process, the conductive material filling the first hole 101 and covering the top surface of the first dielectric layer 30.

[0086] Then, a chemical mechanical polishing (CMP) is used to remove the conductive material on the first dielectric layer 30 to form the first electrode 11 in the first hole 101.

[0087] The material of the first electrode 11 can include at least one of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, ruthenium, ruthenium oxide, iridium, iridium oxide, indium tin oxide, aluminum titanium nitride, aluminum nitride, aluminum titanium nitride, hafnium, or copper.

[0088] For example, the thickness of the first electrode 11 is 10 nm-500 nm.

[0089] In step S30, a PVD, a CVD, or an ALD is used to deposit a gate material layer covering the top surface of the first dielectric layer 30 and the first electrode 11. Then, a photoresist layer is formed on the gate material layer, and the photoresist layer is patterned to define a pattern of the gate layer 12. The gate material layer is etched according to the patterned photoresist layer to form the gate layer 12 in contact with the top surface of the first electrode 11. Figure 9

[0090] In this embodiment, referring to Figure 9 The projection of the gate layer 12 on the substrate 20 covers the projection of the first electrode 11 on the substrate 20, and the gate layer 12 also covers a portion of the first dielectric layer 30 around the first electrode 11.

[0091] ​The material of the gating layer 12 can include at least one of niobium oxide, vanadium oxide, OTS material such as aluminum telluride, boron telluride, germanium selenide, germanium sulfide, antimony telluride, GeSeAsIn, GeSeAsN, GeSeCN.

[0092] In some embodiments, the thickness of the gating layer 12 is 5nm-200nm.

[0093] In step S40, referring to Figure 10 The passivation layer 14 can be deposited by air pressure chemical vapor deposition (APCVD), PECVD, low pressure chemical vapor deposition (LPCVD) to cover the sidewall and top surface of the gating layer 12.

[0094] In some embodiments, the thermal conductivity of the passivation layer 14 is 0.1W / m·K-25W / m·K; for example, the thermal conductivity of the passivation layer 14 can be 0.1W / m·K, 1W / m·K, 3W / m·K, 5W / m·K, 8W / m·K, 10W / m·K, 12W / m·K, 13W / m·K, 15W / m·K, 18W / m·K, 20W / m·K, 22W / m·K or 25W / m·K.

[0095] The electrical conductivity of the passivation layer 14 is 10 -8 S / m to 10 -16 S / m. For example, the electrical conductivity of the passivation layer 14 can be 10 -8 S / m, 10 -9 S / m, 10 -10 S / m, 10 -11 S / m, 10 -12 S / m, 10 -13 S / m, 10 -14 S / m, 10 -15 S / m or 10 -16 S / m.

[0096] In some embodiments, the material of the passivation layer 14 includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, tantalum oxide.

[0097] In this embodiment, after step S40, before step S50, the following steps are further performed:

[0098] Referring to Figure 11 , step S40-1: forming an insulating layer 15, the insulating layer 15 covers the gating layer 12, and the insulating layer 15 is separated from the gating layer 12 by the passivation layer 14.

[0099] The insulating material can be deposited by APCVD, PECVD or LPCVD to cover the passivation layer 14 and fill the region between the gate layers 12, forming an insulating layer 15.

[0100] For example, the material of the insulating layer 15 can include porous silicon oxide, porous silicon carbon oxygen hydride, silicate glass, boron phosphorus silicon glass or silicon carbonitride, etc. low-K material with low dielectric constant.

[0101] For example, the insulating layer 15 can include a single layer or a multi-layer structure.

[0102] In some embodiments, referring to Figure 3 The first insulating layer 151 is formed on the first dielectric layer 30 to fill the region between the gate layers 12 of adjacent gate tubes 10, and the second insulating layer 152 is formed above the gate layer 12.

[0103] In step S50, referring to Figure 12 At least part of the passivation layer 14 on the top surface of the gate layer 12 is removed to expose at least part of the top surface of the gate layer 12, which can be implemented as follows:

[0104] A photoresist layer is formed on the top surface of the insulating layer 15, and the photoresist layer is patterned to define the pattern of the second electrode 13. The insulating layer 15 is etched according to the patterned photoresist layer.

[0105] The insulating layer 15 is etched to expose part of the top surface of the gate layer 12, forming a first hole 101, and the second electrode 13 is formed in the first hole 101. Specifically, after etching the insulating layer 15 according to the patterned photoresist layer, the passivation layer 14 exposed by the first hole 101 is etched to extend the first hole 101 to the top surface of the gate layer 12, so that the second electrode 13 formed in the first hole 101 is connected to the top surface of the gate layer 12.

[0106] In step S60, referring to Figure 2 The conductive material can be deposited by PVD, CVD, PECVD, ALD or electroplating process to fill the first hole 101 and cover the top surface of the insulating layer 15. The top surface of the insulating layer 15 is removed by CMP to form the second electrode 13.

[0107] The material of the second electrode 13 is selected from the same range as the material of the first electrode 11, which will not be described here.

[0108] For example, the thickness of the second electrode 13 is 10nm-500nm.

[0109] In the embodiment, the projection of the second electrode 13 formed on the substrate 20 falls inside the projection of the gating layer 12 formed on the substrate 20, and part of the top surface of the gating layer 12 is covered by the first passivation layer 141.

[0110] In some embodiments, referring to Figure 6 and combining with Figure 2 , Figure 10- Figure 12 , before forming the first hole 101, the first passivation layer 141 is formed to cover the top surface of the first dielectric layer 30, and the first passivation layer 141 and the first dielectric layer 30 are etched to form the first hole 101; part of the bottom surface of the gating layer 12 is connected with the first passivation layer 141, and the gating layer 12 is separated from the first dielectric layer 30 by the first passivation layer 141; after forming the gating layer 12, the second passivation layer 142 is formed to cover the sidewall and the top surface of the gating layer 12.

[0111] In this way, part of the bottom surface of the gating layer 12, except the part in contact with the first electrode 11, is connected with the first passivation layer 141, and the gating layer 12 is separated from the first dielectric layer 30 by the first passivation layer 141, so that the passivation layer 14 can provide more comprehensive protection for the gating layer 12 and optimize the thermal management of the gating layer 12, thereby further optimizing the switching performance of the gating tube 10, and at the same time, the passivation layer 14 can reduce the risk of electrical crosstalk or short circuit between the gating layer 12 and other devices.

[0112] The gating tube provided by the present disclosure is additionally provided with a passivation layer covering the sidewall of the gating layer, the passivation layer can reduce the leakage current of the gating tube in the high resistance state, the passivation layer can isolate or weaken the abnormal flow path of the current of the gating tube, and the passivation layer significantly improves the current control ability of the device in the off state, thereby reducing unnecessary energy consumption; at the same time, the passivation layer has good thermal insulation properties, can hinder the heat of the gating layer from being transferred to the external environment, and improves the thermal stability of the gating layer, so that the heat inside the gating layer is more effectively retained inside the gating layer when the gating tube is turned on, so as to accelerate the temperature rise rate of the gating layer, so that the gating tube can reach its threshold voltage for turning on more quickly, thereby significantly improving the response speed of the gating tube. The gating tube provided by the present disclosure can realize faster switching speed and lower power consumption while ensuring high switching ratio. This is of great significance to improve the efficiency and performance of the entire electronic system, and can meet the demand for new generation of electronic devices along the development process of Moore's Law in the integrated circuit field.

[0113] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present disclosure.

[0114] The above-described embodiments are merely illustrative of several embodiments of the present disclosure, which are described in a relatively specific and detailed manner, but should not be construed as limiting the scope of the patent application. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A method for manufacturing a selector tube, characterized in that, include: A substrate is provided, on which a first dielectric layer is coated; A first hole is formed on the first dielectric layer, and a first electrode is formed in the first hole; A gate layer is formed on the first electrode layer, and the bottom surface of the gate layer is in contact with the first electrode. A passivation layer is formed, the passivation layer at least covering the sidewalls of the gate layer and the top surface of the gate layer; The conductivity of the passivation layer is less than that of the gate layer; Remove at least a portion of the passivation layer on the top surface of the gate layer to expose at least a portion of the top surface of the gate layer; A second electrode is formed, which covers the exposed top surface of the gate layer and is in contact with the top surface of the gate layer.

2. The method for manufacturing the selection tube according to claim 1, characterized in that, The passivation layer includes a first passivation layer and a second passivation layer; before forming the first hole, the first passivation layer is formed, the first passivation layer covers the top surface of the first dielectric layer, and the first passivation layer and the first dielectric layer are etched to form the first hole; A portion of the bottom surface of the gate layer is connected to the first passivation layer, and the gate layer is separated from the first dielectric layer by the first passivation layer; After the gate layer is formed, a second passivation layer is formed to cover the sidewalls and top surface of the gate layer.

3. The method for manufacturing the selection tube according to claim 2, characterized in that, Removing at least a portion of the passivation layer on the top surface of the gate layer to expose at least a portion of the top surface of the gate layer includes: An insulating layer is formed to cover the second passivation layer; The insulating layer and the second passivation layer below it are etched to expose a portion of the top surface of the gate layer, forming a second hole; The second electrode is formed in the second hole.

4. The method for manufacturing the selection tube according to claim 1, characterized in that, The thermal conductivity of the passivation layer is 0.1 W / m·K - 25 W / m·K; the electrical conductivity of the passivation layer is 10. -8 S / m to 10 -16 S / m; The passivation layer is made of at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

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