Package comprising acoustic device and polymer cap layer

Abstract

A package comprises: an acoustic device (102); a polymer frame (105) coupled to the acoustic device (102); a plurality of frame interconnects (142) in the polymer frame (105), wherein the plurality of frame interconnects (142) are coupled to the acoustic device (102); a polymeric cap layer (104) coupled to the acoustic device (102) through the polymeric frame (105), wherein the polymeric cap layer (104) is configured as a cap for the acoustic device (102); a plurality of cap interconnects (242) in the polymeric cap layer (104), wherein the plurality of cap interconnects (242) are coupled to the plurality of frame interconnects (142); and a cavity (103) between the acoustic device (102) and the polymeric capping layer (104). The acoustic device (102) includes a substrate (120) and an acoustic element (121) coupled to the substrate (120).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 948,984 filed in the United States Patent and Trademark Office on September 20, 2022, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0003] field

[0004] Various features relate to packages including acoustic devices. Background Art

[0005] Acoustic devices can be used to filter out unwanted signals. For example, acoustic devices can be used to filter out signals of various frequencies while passing signals of specific frequencies. These acoustic devices can be implemented in packages, which in turn can be implemented in devices. As devices become smaller and smaller, there is a need to provide packages for acoustic devices with better form factors and smaller sizes.

[0006] Overview

[0007] Various features relate to packages including acoustic devices.

[0008] One example provides a package including: an acoustic device; a polymer frame coupled to the acoustic device; a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; a polymer cover layer coupled to the acoustic device through the polymer frame, wherein the polymer cover layer is configured as a cover for the acoustic device; a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects; and a cavity between the acoustic device and the polymer cover layer. The acoustic device includes a substrate and an acoustic element coupled to the substrate.

[0009] Another example provides a device, the device comprising: an acoustic device; a polymer frame coupled to the acoustic device; a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; a polymer cover layer coupled to the acoustic device through the polymer frame, wherein the polymer cover layer is configured as a cover for the acoustic device; a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects; and a cavity between the acoustic device and the polymer cover layer. The acoustic device comprises a substrate and an acoustic element coupled to the substrate.

[0010] Another example provides a method for manufacturing a package. The method provides an acoustic device including a substrate and an acoustic element coupled to the substrate. The method couples a polymer frame to the acoustic device. The method couples a polymer cover layer to the acoustic device through the polymer frame. Coupling the polymer cover layer forms a cavity between the acoustic device and the polymer cover layer. The polymer cover layer is configured as a cover for the acoustic device. The method forms a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device. The method forms a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0013] Figure 1 A cross-sectional cutaway view of an exemplary package including an acoustic device and a polymer cover for the acoustic device is illustrated.

[0014] Figure 2 A cross-sectional cutaway view of another exemplary package including an acoustic device, a polymer cover for the acoustic device, and an encapsulation layer having passive components is illustrated.

[0015] Figure 3 A cross-sectional cutaway view of another exemplary package including an acoustic device, a polymer cover for the acoustic device, an encapsulation layer with passive devices, and a capacitor is illustrated.

[0016] Figure 4 A cross-sectional profile view of another exemplary package including a substrate, an acoustic device, a polymer cover for the acoustic device, and an encapsulation layer with passive devices is illustrated.

[0017] Figure 5 A cross-sectional profile view of another exemplary package including a substrate, an acoustic device, a polymer cover for the acoustic device, and an encapsulation layer with passive devices is illustrated.

[0018] Figure 6 A cross-sectional profile view of another exemplary package including a substrate, an acoustic device, and a polymer cover for the acoustic device is illustrated.

[0019] Figure 7 A cross-sectional cutaway view of another exemplary package including a substrate, an acoustic device, a polymer cover for the acoustic device, and a magnetic material is illustrated.

[0020] Figure 8Illustrated is a view of an exemplary package including a substrate, an acoustic device, and a polymer cover for the acoustic device.

[0021] Fig. 9 Illustrated is a view of an exemplary package including a substrate, an acoustic device, and a polymer cover for the acoustic device.

[0022] Fig.10 A cross-sectional cutaway view of an exemplary acoustic device is illustrated.

[0023] Fig.11 A cross-sectional cutaway view of another exemplary acoustic device is illustrated.

[0024] Fig.12 An exemplary process for manufacturing an acoustic device is illustrated.

[0025] Fig.13 An exemplary process for manufacturing an acoustic device is illustrated.

[0026] Fig.14 An exemplary flow chart illustrating a method of manufacturing an acoustic device.

[0027] Figures 15A-15J An exemplary process for making a package including an acoustic device and a polymer cover for the acoustic device is illustrated.

[0028] Figures 16A-16B An exemplary process for making a package including an acoustic device and a polymer cover for the acoustic device is illustrated.

[0029] Fig.17 An exemplary flow chart of a method of making a package including an acoustic device and a polymer cover for the acoustic device is illustrated.

[0030] Fig.18 Various electronic devices are illustrated into which the dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein may be integrated.

[0031] Detailed Description

[0032] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0033] The present disclosure describes a package comprising: an acoustic device; a polymer frame coupled to the acoustic device; a plurality of frame interconnects located in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; a polymer cover layer coupled to the acoustic device through the polymer frame, wherein the polymer cover layer is configured as a cover for the acoustic device; a plurality of cover interconnects located in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects; and a cavity located between the acoustic device and the polymer cover layer. The acoustic device comprises a substrate and an acoustic element coupled to the substrate. In some implementations, the package further comprises: an encapsulation layer coupled to the polymer cover layer and a plurality of encapsulation interconnects located at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects. At least some of the encapsulation interconnects from the plurality of encapsulation interconnects are configured to operate as inductors (such as solenoid inductors). The configuration of the package provides a package with a smaller footprint and a more compact form factor. For example, stacking a polymer cover layer over an acoustic device may reduce the footprint and / or lateral dimensions of the package while still providing a relatively thin package for a relatively low cost.

[0034] Exemplary package including an acoustic device and a polymer cover layer

[0035] Figure 1 A cross-sectional cutaway view of a package 100 including an acoustic device and a polymer cover layer is illustrated. The package 100 is coupled to a board 106 via a plurality of solder interconnects 107. The package 100 and board 106 can be part of an assembly. In some implementations, the package 100 can be coupled to a substrate (e.g., a laminate substrate, a cored substrate, an embedded trace substrate, an interposer, a package substrate).

[0036] The package 100 includes an acoustic device 102, a polymer cover layer 104, and a polymer frame 105. The polymer frame 105 is coupled to the acoustic device 102 and the polymer cover layer 104. The polymer cover layer 104 is coupled to the acoustic device 102 through the polymer frame 105. The polymer cover layer 104 is coupled to the board 106 through a plurality of solder interconnects 107. The package 100 includes a cavity 103 located between the acoustic device 102 and the polymer cover layer 104. The cavity 103 may be defined by at least the acoustic device 102, the polymer cover layer 104, and the polymer frame 105.

[0037] The acoustic device 102 includes a substrate 120, an acoustic element 121, and a plurality of interconnects 122. The plurality of interconnects 122 may be coupled to the acoustic element 121. The acoustic element 121 may include several acoustic elements. The substrate 120 may include a piezoelectric substrate. The substrate 120 may include a piezoelectric material. In some implementations, the substrate 120 may be entirely a piezoelectric material. In some implementations, the piezoelectric material may be formed on the surface of the substrate 120. The substrate 120 may be an acoustic device substrate. The plurality of interconnects 122 are coupled to the acoustic element 121. Examples of acoustic elements include transducers. The acoustic device 102 may be configured to operate as a filter (e.g., an RF filter). For example, the acoustic element 121 (e.g., a transducer) of the acoustic device 102 may be configured to operate as a filter. When the acoustic element 121 includes several acoustic elements, the acoustic device 102 may be configured to operate as several filters. The acoustic device 102 may be configured to operate as a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter. More specific examples of acoustic devices and / or filter devices are described below in at least Fig.10 and Fig.11 Further described in .

[0038] The polymer cover layer 104 includes a polymer layer 140 and a plurality of interconnects 142. The plurality of interconnects 142 may be located in the polymer layer 140 and located above the first surface of the polymer layer 140. At least some of the interconnects from the plurality of interconnects 142 may be located in the polymer frame 105. One or more interconnects from the plurality of interconnects 142 located in the polymer frame 105 may be part of a plurality of frame interconnects. One or more interconnects from the plurality of interconnects located in the polymer layer 140 may be part of a plurality of cover interconnects. A plurality of cover interconnects may be coupled to a plurality of frame interconnects. A plurality of interconnects 142 are coupled to a plurality of interconnects 122. The polymer cover layer 104 is located between the acoustic device 102 and the board 106. The polymer cover layer 104 may be configured as a cover for the acoustic device 102. The polymer layer 140 may be configured as a cover for an acoustic element 121 of the acoustic device 102. The polymer cover layer 104 may be configured as a top for the acoustic device 102. The polymer layer 140 may be configured as a top for the acoustic element 121 of the acoustic device 102. The polymer cap layer 104 may be a polymer top layer.

[0039] The polymer cover layer 104 is coupled to the acoustic device 102 so that the cavity 103 is located between the polymer cover layer 104 and the acoustic device 102. The cavity 103 may be located between the acoustic element 121 and the polymer layer 140. The cavity may be at least one area without solid material. The cavity may be occupied by a gas (e.g., air). The cavity 103 may be located above the acoustic element 121. The polymer frame 105 may laterally surround the cavity 103. The cavity 103 may be located above the acoustic element 121. In some implementations, the cavity 103 may include several cavities. For example, as will be further described below, the cavity 103 may include several cavities defined by a cabin formed and / or defined according to the polymer frame 105. In some implementations, the cavity 103 may have a minimum height of about 4 microns. In some implementations, the cavity 103 may have a minimum height of about 8 microns. The height of the cavity 103 may be the distance and / or spacing between the bottom surface of the polymer layer 140 and the top surface of the acoustic device 102. The height of the cavity 103 may be a distance and / or spacing between a bottom surface of the polymer layer 140 and a top surface of the acoustic element 121 of the acoustic device 102 .

[0040] As mentioned above, some interconnects from the plurality of interconnects 142 may be located in the polymer frame 105 and / or the polymer cover layer 104. The plurality of interconnects 142 may extend through the thickness of the polymer layer 140. The plurality of interconnects 142 may extend through the polymer frame 105. The plurality of interconnects 142 may be coupled to the plurality of interconnects 122. For example, a plurality of frame interconnects from the plurality of interconnects 142 may be coupled to the plurality of interconnects 122. The plurality of interconnects 144 may be coupled to the plurality of interconnects 142. For example, the plurality of interconnects 144 may be coupled from the plurality of interconnects 142 to the plurality of cover interconnects. The plurality of interconnects 144 may include tin (Sn). The plurality of interconnects 144 may include silver (Ag). The plurality of interconnects 144 may include nickel (Ni). The plurality of interconnects 144 may include palladium (Pd). The plurality of interconnects 144 may include gold (Au). The plurality of interconnects 142 may include copper (Cu). The package 100 may include a seed layer (not shown) located between the plurality of interconnects 142 and the polymer layer 140. The seed layer may be located between the plurality of interconnects 142 and the polymer frame 105. The seed layer may be located between the plurality of interconnects 142 and the plurality of interconnects 122. In some implementations, the seed layer may be considered a part of the plurality of interconnects 142. The seed layer may include copper. The seed layer may include titanium.

[0041] Package 100 may include a front side and a back side. The back side of package 100 may include acoustic device 102. Acoustic device 102 includes a front side (e.g., a side including acoustic element 121) and a back side. The back side of package 100 may include a back side of substrate 120 (e.g., a surface of substrate 120 that does not include acoustic element 121, the back side of acoustic device 102). The front side of package 100 may include a side including polymer cover layer 104.

[0042] The package 100 is coupled to the board 106 through a plurality of solder interconnects 107. The package 100 is coupled to the board 106 so that the front side of the package 100 faces the board 106 and the back side of the package 100 faces away from the board 106. For example, the package 100 is coupled to the board 106 so that the polymer cover layer 104 faces the board 106, the front side of the acoustic device 102 faces the board 106, and the back side of the acoustic device 102 faces away from the board 106. The board 106 may include a printed circuit board (PCB). The board 106 may include at least one board dielectric layer 160 and a plurality of board interconnects 162. In some implementations, the plurality of solder interconnects 107 are coupled to the plurality of board interconnects 162 and interconnects from the plurality of interconnects 142. In some implementations, the plurality of solder interconnects 107 are coupled to the plurality of interconnects 144. The plurality of interconnects 144 may be located between the plurality of solder interconnects 107 and the plurality of interconnects 142. In some implementations, one or more electrical signals may travel through number of interconnects 144 , number of interconnects 142 , and / or number of interconnects 122 .

[0043] In some implementations, the polymer frame 105 can include a different material than the polymer layer 140. Thus, the polymer frame 105 and the polymer layer 140 can both be polymers, but have different properties.

[0044] Figure 2 A package 200 including additional metallizations and / or metallization layers is illustrated. The package 200 is similar to the package 100 and includes similar components configured in a manner similar to that described for the package 100. The package 200 includes the acoustic device 102, the polymer frame 105, the polymer cover layer 104, the cavity 103, the metallization 204, and the metallization 206. The polymer cover layer 104 is coupled to the acoustic device 102 through the polymer frame 105. The metallization 204 is coupled to a surface of the polymer cover layer 104. The metallization 204 may be a redistribution portion.

[0045] The metallization portion 204 includes an encapsulation layer 240 and a plurality of encapsulation interconnects 242. The encapsulation layer 240 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 240 may be a device for encapsulation. The encapsulation layer 240 may include several encapsulation layers. The encapsulation layer 240 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. A plurality of encapsulation interconnects 242 may be coupled to a plurality of interconnects 142. A plurality of encapsulation interconnects 242 may be coupled to an inductor of the polymer layer 140. For example, a plurality of encapsulation interconnects 242 may be coupled to a plurality of interconnects 142. A plurality of encapsulation interconnects 242 may include a plurality of metallization interconnects. A plurality of encapsulation interconnects 242 may include a plurality of redistribution interconnects. A plurality of encapsulation interconnects 242 are located in the encapsulation layer 240.

[0046] In some implementations, at least some of the encapsulated interconnects from the plurality of encapsulated interconnects 242 are configured to operate as inductors 210. Inductors 210 may include solenoid inductors. Inductors 210 may include and / or be defined according to a plurality of interconnects 142a, a plurality of encapsulated interconnects 242a, and a plurality of encapsulated interconnects 242b. Inductors 210 may be configured to be electrically coupled to acoustic devices 102. For example, inductors 210 may be configured to be electrically coupled to acoustic elements 121 through a plurality of interconnects 142 and a plurality of interconnects 122.

[0047] The inductor 210 is implemented such that the magnetic field generated by the inductor 210 points in a direction parallel to the first surface (e.g., the first planar surface) and / or the second surface (e.g., the first planar surface) of the polymer layer 140. This direction of the magnetic field results in less interference of the magnetic field with the operation and performance of the acoustic element 121. However, different implementations may configure the inductor 210 differently. The inductor 210 may be configured as a passive component (e.g., a matching element) in a filter topology together with the acoustic device 102 (e.g., a matching element for the acoustic element 121).

[0048] Metallization 206 is coupled to the surface of metallization 204. Metallization 206 may be a redistribution portion. Metallization 206 includes a dielectric layer 260 and a plurality of interconnects 262. The dielectric layer may include several dielectric layers. Dielectric layer 260 may include a polymer (e.g., epoxy, polyimide). The plurality of interconnects 262 are coupled to the plurality of encapsulation interconnects 242.

[0049] The package 200 is coupled to the board 106 via a plurality of interconnects 207. The plurality of interconnects 207 may be coupled to the plurality of board interconnects 162 and the plurality of interconnects 262 of the metallization 206. The plurality of interconnects 207 may include a land grid array (LGA). The plurality of interconnects 207 may include a metal layer. The metallization 206 is located between the metallization 204 and the board 106. In some implementations, the package 200 may be coupled to the board 106 via a plurality of solder interconnects (e.g., 107) located between the plurality of interconnects 207 and the plurality of board interconnects 162.

[0050] Package 200 may include a front side and a back side. The back side of package 200 may include acoustic device 102. Acoustic device 102 includes a front side (e.g., a side including acoustic element 121) and a back side. The back side of package 200 may include the back side of substrate 120 (e.g., a surface of substrate 120 that does not include acoustic element 121, the back side of acoustic device 102). The front side of package 200 may include a side including polymer cover layer 206.

[0051] The package 200 is coupled to the board 106 through the plurality of interconnects 207 and the plurality of solder interconnects 107. The package 200 is coupled to the board 106 such that the front side of the package 200 faces the board 106 and the back side of the package 200 faces away from the board 106. For example, the package 200 is coupled to the board 106 such that the metallization 206 faces the board 106, the front side of the acoustic device 102 faces the board 106, and the back side of the acoustic device 102 faces away from the board 106.

[0052] Figure 3 A package 300 including an acoustic device, an inductor, and a capacitor is illustrated. Package 300 is similar to package 200 and includes similar components configured in a manner similar to that described for package 200. Package 300 includes acoustic device 102, polymer frame 105, polymer cover layer 104, cavity 103, metallization 204, and metallization 206. Package 300 includes capacitor 310 located in metallization 206.

[0053] The metallization portion 206 includes a dielectric layer 360, a high-K dielectric layer 362, the dielectric layer 260, and the plurality of interconnects 262. The capacitor 310 may be defined by the encapsulation interconnect 242b from the plurality of encapsulation interconnects 242, the high-K dielectric layer 362, and the interconnect 262a from the plurality of interconnects 262. The dielectric layer 360 may be a similar dielectric or a different dielectric than the dielectric layer 260. The capacitor 310 is configured to be electrically coupled to the inductor 210 and the acoustic device 102.

[0054] The package 300 is coupled to the board 106 via the plurality of interconnects 207 and the plurality of solder interconnects 107. The package 300 is coupled to the board 106 such that the front side of the package 300 faces the board 106 and the back side of the package 300 faces away from the board 106. For example, the package 300 is coupled to the board 106 such that the metallization 206 faces the board 106, the front side of the acoustic device 102 faces the board 106, and the back side of the acoustic device 102 faces away from the board 106. In some implementations, the board 106 may be a printed circuit board. In some implementations, the board 106 may be a substrate (e.g., a package substrate).

[0055] The polymer frame 105, polymer layer 140, and encapsulation layer 240 may be selected based on several factors and / or considerations. For example, in some implementations, the polymer frame 105 may include a material having a high resolution for forming through-hole interconnects and capsules around the acoustic element. The polymer frame 105 may include a material that is strong enough to maintain its shape during the formation of the polymer layer 140.

[0056] In some implementations, polymer layer 140 may include a material with high resolution for forming through-hole interconnects. Polymer layer 140 may include a material that is strong enough to cover the cavity. Polymer layer 140 may include a material with a high modulus. In some implementations, polymer layer 140 may have a Young's modulus (E) of about 5 GPa or greater. Polymers with sufficient strength and / or a sufficiently high Young's modulus help ensure that polymer layer 140 does not collapse due to pressure from applying and / or forming encapsulation layer 240. This is important because during the process of forming encapsulation layer 240, the pressure of the weight of encapsulation layer 240 and the pressure from the process of applying encapsulation layer 240 may cause polymer layer 140 to collapse, which will cause cavity 103 to deform and / or not exist. Polymer layer 140 may include a material with good adhesion to polymer frame 105. In some implementations, polymer frame 105 and / or polymer layer 140 include materials other than glass, prepreg and / or polyimide. In some implementations, the polymer frame 105 and / or the polymer layer 140 are free of glass, prepreg, and / or polyimide.

[0057] In some implementations, the encapsulation layer 240 may include a dielectric having good resistivity and having high magnetic permeability. In some implementations, the encapsulation layer 240 may include ferrite ceramic as a filler.

[0058] In some implementations, the acoustic device and polymer cover layer can be implemented as part of a package that includes an encapsulation layer and a substrate. Figure 4-6 Various examples of packages having an encapsulation layer and a substrate are illustrated.

[0059] Figure 4 A package 400 is illustrated that includes a substrate 406, a package 200, and an encapsulation layer 408. The package 200 is similar to at least Figure 2 4. The package 200 described in . Package 200 is coupled to substrate 406 via a plurality of solder interconnects 407. Encapsulation layer 408 is coupled to substrate 406 and package 200. Encapsulation layer 408 encapsulates package 200. Encapsulation layer 408 may include a molding, a resin and / or an epoxy resin. Encapsulation layer 408 may be a device for encapsulation. Encapsulation layer 408 may include several encapsulation layers. Encapsulation layer 408 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Substrate 406 includes at least one dielectric layer 460 and a plurality of substrate interconnects 462. At least one dielectric layer 460 may include a core layer. Substrate 406 may be a package substrate. Note that instead of package 200, package 400 may include package 100 or package 300.

[0060] Figure 5 A package 500 is illustrated that includes a substrate 406, a package 502, and an encapsulation layer 408. The package 502 is similar to at least Figure 2 . Package 502 includes components arranged and / or configured in a similar manner to package 200. Package 502 includes acoustic device 102, polymer frame 105, polymer cover layer 104, and metallization portion 204. Package 502 is coupled to substrate 406 via multiple solder interconnects 507. Specifically, multiple encapsulation interconnects 242 of metallization portion 204 are coupled to substrate 406 via multiple solder interconnects 507. Encapsulation layer 408 is coupled to substrate 406 and package 502. Encapsulation layer 408 encapsulates package 502. Substrate 406 includes at least one dielectric layer 460 and multiple substrate interconnects 462. At least one dielectric layer 460 may include a core layer. Substrate 406 may be a package substrate. Package 500 includes an inductor 510. Inductor 510 may be defined based on interconnects from package 502 (e.g., interconnects from plurality of interconnects 142, encapsulation interconnects from plurality of encapsulation interconnects 242), solder interconnects from plurality of solder interconnects 507, and substrate interconnects from plurality of substrate interconnects 462. Inductor 510 may be configured as a solenoid inductor. Note that package 500 may include package 100, package 200, or package 300 instead of package 502.

[0061] Figure 6 A package 600 is illustrated that includes a substrate 406, a package 100, and an encapsulation layer 408. The package 100 is similar to at least Figure 1 . The package 100 described in . The package 100 is coupled to the substrate 406 via a plurality of solder interconnects 607. Specifically, the plurality of interconnects 142 of the polymer cap layer 104 are coupled to the substrate 406 via a plurality of solder interconnects 607. The encapsulation layer 408 is coupled to the substrate 406 and the package 100. The encapsulation layer 408 encapsulates the package 100. The substrate 406 includes at least one dielectric layer 460 and a plurality of substrate interconnects 462. The at least one dielectric layer 460 may include a core layer. The substrate 406 may be a package substrate. The package 600 includes an inductor 610. The inductor 610 may be defined according to an interconnect from the package 100 (e.g., an interconnect from the plurality of interconnects 142), a solder interconnect from the plurality of solder interconnects 607, and a substrate interconnect from the plurality of substrate interconnects 462. Note that instead of the package 100, the package 600 may include the package 200 or the package 300.

[0062] In some implementations, the inductance and / or quality factor of an inductor can be improved by providing and / or forming magnetic material within the windings of the inductor.

[0063] Figure 7 A package 700 is illustrated that includes magnetic material within windings of an inductor within the package. The package 700 is similar to Figure 3Package 700 includes components arranged and / or configured in a similar manner as package 300. Package 700 includes acoustic device 102, polymer frame 105, polymer cover layer 104, metallization portion 204 and metallization portion 206, and magnetic inlay 710. Magnetic inlay 710 includes magnetic material. Magnetic inlay 710 is located in metallization portion 204. Magnetic inlay 710 may be surrounded by interconnects from inductor 210. Note that magnetic inlay 710 can be implemented in a similar manner in any package described in the present disclosure. Magnetic inlay 710 may include a solid ferromagnetic inlay. However, other materials may be used for magnetic inlay 710.

[0064] The magnetic inlay 710 may include one or more magnetic layers and / or one or more magnetic materials. The magnetic inlay 710 includes an insulating layer, a dielectric layer, and / or a non-conductive material (e.g., a non-conductive material). The magnetic inlay 710 may be both a dielectric material and a magnetic material. Thus, at least one magnetic inlay 710 may have both dielectric properties and magnetic properties. The magnetic inlay 710 may include one or more materials. The magnetic inlay (e.g., a magnetic material) has a magnetic permeability value greater than 1 (e.g., about 10 or greater, ranging from 6-12). The magnetic inlay may have different magnetic permeability values ​​at different frequencies. As described in the present disclosure, the magnetic permeability value of the magnetic material and / or magnetic inlay is a relative magnetic permeability value, which is defined as the ratio of the magnetic permeability of the material to the magnetic permeability of free space. Thus, the magnetic permeability values ​​described for the magnetic material and / or magnetic inlay explained and / or described in the present disclosure may represent relative magnetic permeability values ​​relative to a defined magnetic permeability value (e.g., a reference magnetic permeability value) of free space. In some implementations, free space can be defined as having a defined permeability value μ0=4π×10 -7 H / (henry per meter). Materials with relative permeability values ​​greater than 1 are considered magnetic materials.

[0065] In some implementations, the acoustic device 102 may include several acoustic elements 121. To improve the performance of one or more acoustic elements 121, one or more acoustic elements may be partitioned into pods in their own space. For example, a polymer frame 105 may be used to form a pod that laterally surrounds one or more acoustic elements.

[0066] Figure 8 It is illustrated how the polymer frame 105 can be formed to provide a chamber that each laterally surrounds one or more acoustic elements 121 . Figure 8 Illustrated are compartments 803a, 803b, 803c, 803d, and 803e defined by polymer frame 105. Each specific compartment may define a specific cavity. Thus, Figure 8The cavity 103 shown in the figure may include several cavities, each located in a specific cabin. One or more acoustic elements 121 may be located in a specific cabin. Some cabins may include one acoustic element. Some cabins may include several acoustic elements.

[0067] Fig. 9 Another example of how the polymer frame 105 can be formed to provide a pod that each laterally surrounds one or more acoustic elements 121 is illustrated. Fig. 9 Illustrated are compartment 903a, compartment 903b, compartment 903c, compartment 903d, and compartment 903e defined by polymer frame 105. Fig. 9 The cabin shown in the figure is designed to be Figure 8 The chambers shown in more closely follow the contours of the acoustic element. Each specific chamber can define a specific cavity. Thus, Fig. 9 The cavity 103 shown in the figure may include multiple cavities, each located in a specific chamber. One or more acoustic elements 121 may be located in a specific chamber. Some chambers may include an acoustic element. The chamber may help isolate an acoustic element of an acoustic device from one or more acoustic elements. A polymer cover layer 104 may be present above each chamber.

[0068] The packages (e.g., 100, 200, 300, 400, 500, 600, 700) provide compact packages that can be configured as filters. These packages may be small enough to be implemented in very small devices while still providing effective and efficient signal filtering. This can be achieved by using a polymer cover implemented with an inductor. In addition, the polymer cover layer 104 and / or the metallization portion (e.g., 204, 206) can be configured to provide one or more electrical paths for the signal to travel between the acoustic device 102 and the plate 106. Thus, the polymer cover layer 104 and / or the metallization portion (e.g., 204, 206) provide multiple functionalities for the package (e.g., 100, 200, 300, 400, 500, 600, 700).

[0069] In some implementations, substrate 120 may include silicon (Si). Multiple interconnects 142, multiple encapsulation interconnects 242, multiple interconnects 262, and / or multiple interconnects 122 may include a seed layer. Polymer frame 105 may be configured to create a frame that laterally surrounds and / or defines cavity 103. Polymer frame 105 may be configured to create a frame that laterally surrounds acoustic element 121.

[0070] Fig.10 and 11 Cross-sectional cutaway views of several exemplary acoustic devices are illustrated. Each acoustic device may be configured as a filter (eg, a signal filter, a radio frequency (RF) filter).

[0071] Fig.10An acoustic device 1002 is illustrated that includes a substrate 1010, an acoustic element 1021, and a plurality of interconnects 1022. Acoustic device 1002 may represent acoustic device 102. Substrate 1010 may be a piezoelectric substrate. Substrate 1010 may include a piezoelectric material (eg, aluminum nitride (AlN), lithium niobate, lithium tantalate).

[0072] The acoustic element 1021 and the plurality of interconnects 1022 may be formed on and coupled to the substrate 1010. The acoustic element 1021 and the plurality of interconnects 1022 may be defined according to at least one metal layer (for example, a conductive material such as aluminum (Al), molybdenum (Mo) and / or copper (Cu)). The metal layer(s) may be patterned and / or configured as interconnects, electrodes and / or transducers for the acoustic device 1002. The acoustic element 1021 may include a first metal layer, and the plurality of interconnects 1022 may include a second metal layer. The first metal layer may be thinner than the second metal layer. The first metal layer may be configured to operate as at least one acoustic element 1021 (for example, a transducer), and the second metal layer may be configured to couple to the plurality of interconnects 1022 of the acoustic element (for example, a transducer). In another example, the piezoelectric substrate may include a substrate and a piezoelectric layer formed on and located on a surface of the substrate.

[0073] Fig.11 An acoustic device 1102 including a substrate 1110, an acoustic element 1021, and a plurality of interconnects 1022 is illustrated. Acoustic device 1102 may represent acoustic device 102. Substrate 1110 may be a piezoelectric substrate. Substrate 1110 may include substrate 1120 and a piezoelectric layer 1130 located on a surface of substrate 1120. Substrate 1120 may include silicon (Si). Substrate 1110 may include a piezoelectric material (e.g., lithium niobate, lithium tantalate). For example, piezoelectric layer 1130 may include aluminum nitride (AlN), lithium niobate, and / or lithium tantalate. Acoustic element 1021 is located on piezoelectric layer 1130. Similarly, a plurality of interconnects 1022 are located on piezoelectric layer 1130.

[0074] As used in the present disclosure, a piezoelectric substrate may refer to a substrate including a piezoelectric material (e.g., as shown in acoustic device 1002) and / or a substrate including a piezoelectric layer coupled to and located above a surface of the substrate (e.g., as shown in device 1102). Different implementations may use different materials for the piezoelectric material and / or the piezoelectric layer.

[0075] Any acoustic device (e.g., 102) described in the present disclosure may be implemented as an acoustic device 1002 and / or an acoustic device 1102. An acoustic device (e.g., 1002, 1102) may be implemented as a microelectromechanical system (MEMS) device. An acoustic device (e.g., 1002, 1102) may be implemented as a die (e.g., a bare die). An acoustic device 1002 and / or 1102 may be configured as a sound wave (SAW) filter. An acoustic device 1002 and / or 1102 may be configured as a bulk acoustic wave (BAW) filter. An acoustic device (e.g., 1002, 1102) may be a device for signal filtering and / or a device for signal extraction. Signal filtering may include signal extraction.

[0076] Having described various packages having acoustic devices and passive devices, a process for manufacturing the acoustic devices will now be described below.

[0077] Exemplary process for making an acoustic device

[0078] In some implementations, manufacturing an acoustic device includes several processes. Fig.12 Exemplary processes for providing or manufacturing an acoustic device are described. In some implementations, Fig.12 The process can be used to provide or manufacture Fig.10 The acoustic device 1002. However, Fig.12 The process may be used to manufacture any acoustic device described in this disclosure.

[0079] It should be noted that Fig.12 The processes of the present invention may combine one or more stages to simplify and / or clarify the processes for providing or manufacturing an acoustic device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of these processes may be replaced or substituted without departing from the spirit of the present disclosure.

[0080] like Fig.12 As shown in , stage 1 illustrates a state after providing a substrate 1010. The substrate 1010 can be a piezoelectric substrate. The substrate 1010 can include a piezoelectric material. In some implementations, the substrate 1010 includes silicon (Si). Different implementations can use different materials that can be used for piezoelectric materials (e.g., lithium niobate, lithium tantalate).

[0081] Stage 2 illustrates a state after the acoustic element 1021 is formed on the substrate 1010. The acoustic element 1021 may be defined by forming and patterning at least one metal layer on the substrate 1010. Patterning (masking) and evaporation (or plating) processes may be used to form at least one metal layer, which may define the acoustic element 1021. The acoustic element 1021 may include a transducer.

[0082] Stage 3 illustrates a state after forming a plurality of interconnects 1022 over the substrate 1010. The plurality of interconnects 1022 may be coupled to the acoustic element 1021. The plurality of interconnects 1022 may be defined by forming and patterning at least one metal layer over the substrate 1010. Patterning (masking) and evaporation (or plating) processes may be used to form at least one metal layer to form the plurality of interconnects 1022. Stage 3 may illustrate an acoustic device 1002 including the substrate 1010, the acoustic element 1021, and the plurality of interconnects 1022.

[0083] Exemplary process for making an acoustic device

[0084] In some implementations, manufacturing an acoustic device includes several processes. Fig.13 Exemplary processes for providing or manufacturing an acoustic device are described. In some implementations, Fig.13 The process can be used to provide or manufacture Fig.11 The acoustic device 1102. However, Fig.13 The process may be used to manufacture any acoustic device described in this disclosure.

[0085] It should be noted that Fig.13 The processes of the present invention may combine one or more stages to simplify and / or clarify the processes for providing or manufacturing an acoustic device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of these processes may be replaced or substituted without departing from the spirit of the present disclosure.

[0086] like Fig.13 As shown in , stage 1 illustrates a state after providing a substrate 1110. The substrate 1110 can be a piezoelectric substrate. The substrate 1110 can include a substrate 1120 and a piezoelectric layer 1130 coupled to and located on a surface of the substrate 1120. In some implementations, the substrate 1120 includes silicon (Si). Different implementations can use different materials that can be used for piezoelectric materials (e.g., lithium niobate, lithium tantalate).

[0087] Stage 2 illustrates a state after the acoustic element 1021 is formed on the substrate 1110. The acoustic element 1021 may be coupled to and located on the piezoelectric layer 1130. The acoustic element 1021 may be defined by forming and patterning at least one metal layer on the substrate 1110. Patterning and evaporation (or plating) processes may be used to form at least one metal layer, which may define the acoustic element 1021. The acoustic element 1021 may include a transducer.

[0088] Stage 3 illustrates a state after a plurality of interconnects 1022 are formed over the substrate 1110. The plurality of interconnects 1022 may be coupled to and located over the piezoelectric layer 1130. The plurality of interconnects 1022 may be coupled to the acoustic element 1021. The plurality of interconnects 1022 may be defined by forming and patterning at least one metal layer over the substrate 1110. Patterning and evaporation (or plating) processes may be used to form at least one metal layer to form the plurality of interconnects 1022. Stage 3 may illustrate an acoustic device 1102 including the substrate 1110, the acoustic element 1021, and the plurality of interconnects 1022.

[0089] Exemplary flow chart of a method for manufacturing an acoustic device

[0090] In some implementations, manufacturing an acoustic device includes several processes. Fig.14 An exemplary flow chart of a method 1400 for providing or manufacturing an acoustic device is illustrated. In some implementations, Fig.14 The method 1400 may be used to provide or manufacture Figure 10-11 Acoustic devices.

[0091] It should be noted that Fig.14 The method 1400 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an acoustic device and a metallization portion. In some implementations, the order of the processes may be changed or modified.

[0092] The method provides (at 1405) a piezoelectric substrate (e.g., 1010, 1110). The entire substrate may be made of a piezoelectric material, or only a portion of the substrate may include a piezoelectric material. For example, substrate 1110 may include substrate 1120 and a piezoelectric layer located on and coupled to substrate 1120. Different implementations may use different materials that may be used for the piezoelectric material and / or the piezoelectric layer (e.g., lithium niobate, lithium tantalate). Fig.12 Phase 1 and Fig.13 Stage 1 of the present invention illustrates and describes an example of providing a piezoelectric substrate.

[0093] The method forms (at 1410) at least one first metal layer on a substrate to form and define an acoustic element. The first metal layer may form an acoustic element 1021. Patterning (masking) and evaporation (or plating) processes may be used to form at least one metal layer, which may define the acoustic element 1021. The acoustic element 1021 may include a transducer. Fig.12 Phase 2 and Fig.13 Stage 2 of illustrates and describes an example of forming at least one first metal layer to form and define an acoustic element.

[0094] The method forms (at 1415) at least one second metal layer on the substrate to form and define a plurality of interconnects. The second metal layer may form a plurality of interconnects 1022. The plurality of interconnects 1022 may be coupled to the acoustic element 1021. Patterning (masking) and evaporation (or plating) processes may be used to form the at least one second metal layer to form the plurality of interconnects 1022. Fig.12 Phase 3 and Fig.13 Stage 3 of the present invention illustrates and describes an example of forming at least one second metal layer to form and define a plurality of interconnects.

[0095] Exemplary process for making a package including an acoustic device and a polymer cover layer

[0096] In some implementations, manufacturing the package includes several processes. Fig.15A -15J illustrates an exemplary process for providing or manufacturing a package. In some implementations, Figures 15A-15J The process can be used to provide or manufacture Figure 7 of package 700. However, Figures 15A-15J The process may be used to manufacture any package (eg, 100, 200, 300) described in the present disclosure.

[0097] It should be noted that Figures 15A-15J The process of the present invention may combine one or more stages to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of these processes may be replaced or substituted without departing from the spirit of the present disclosure.

[0098] like Fig.15A As shown in FIG. 1 , stage 1 illustrates a state after providing an acoustic device 102. The acoustic device 102 includes a substrate 120, an acoustic element 121, and interconnects 122. The acoustic element 121 may include several acoustic elements.

[0099] Stage 2 illustrates a state after providing a polymer frame 105 on the acoustic device 102. The polymer frame 105 may be formed using a deposition process and / or a lamination process.

[0100] Stage 3 illustrates a state after developing the polymer frame 105 (laser ablation is also possible) to form openings 1510 in the polymer frame 105 that expose the acoustic element 121 and the plurality of interconnects 122. The development of the polymer frame 105 may form one or more compartments (e.g., 803a, 903a) for the polymer frame 105. A photolithography process (e.g., an exposure and development process) may be used to form the shape, boundaries, and / or compartments of the polymer frame 105.

[0101] Stage 4 illustrates a state after providing a polymer layer 140 on the polymer frame 105. The polymer layer 140 may be formed using a deposition process and / or a lamination process. The polymer layer 140 may include a polymer material similar to or different from the polymer material of the polymer frame 105. Stage 4 also illustrates a cavity 103 formed between the polymer layer 140 and the acoustic device 102. The cavity 103 may include several cavities defined by the boundaries of the compartment of the polymer frame 105.

[0102] like Fig. 15B As shown in FIG. 5 , stage 5 illustrates a state after the polymer layer 140 is developed to form an opening 1520 in the polymer layer 140. The opening may be formed in the polymer layer 140 using a photolithography process (eg, an exposure and development process).

[0103] Stage 6 illustrates a state after a mask 1530 is formed on the polymer layer 140. The mask 1530 may include an opening exposing the polymer layer 140. Forming the mask may include spin coating, photolithography, and development.

[0104] In some implementations, before the mask is formed, a seed layer may be formed over the surfaces of the plurality of interconnects 122, the polymer frame 105, and the polymer layer 140. The seed layer may be formed using a sputtering or electroless plating process (eg, Ti / Cu sputtering or electroless plating).

[0105] Stage 7 illustrates a state after a plurality of interconnects 142 are formed through the openings of the mask 1530. A plating process may be used to form the plurality of interconnects 142. The plurality of interconnects 142 may be coupled to the plurality of interconnects 122.

[0106] like Fig. 15C As shown in FIG. 1 , stage 8 illustrates a state after removing the mask 1530. Removing the mask 1530 may include stripping the resist.

[0107] Stage 9 illustrates a state after a mask 1540 is formed on the polymer layer 140 and the plurality of interconnects 142. The mask 1540 may include openings 1550 that expose the plurality of interconnects 142. Forming the mask may include spin coating, photolithography, and development.

[0108] like Fig.15D As shown in FIG. 1 , stage 10 illustrates a state after forming a plurality of encapsulation interconnects 242 over the plurality of interconnects 142 and through the openings of mask 1540. A plating process may be used to form the plurality of encapsulation interconnects 242. The plurality of encapsulation interconnects 242 may be coupled to the plurality of interconnects 142.

[0109] Stage 11 illustrates a state after portions of mask 1540 and / or multiple encapsulation interconnects 242 are removed. For example, portions of mask 1540 and / or multiple encapsulation interconnects 242 may be ground and / or polished away. In some implementations, multiple encapsulation interconnects 242 may be encapsulation interconnects with a high aspect ratio, such as a 2:1 aspect ratio (e.g., height-to-width ratio). For example, the encapsulation interconnect may have a height of about 100 microns and a width of about 50 microns. Different implementations may have different heights, widths, and / or aspect ratios.

[0110] like Fig.15E As shown in FIG. 1 , stage 12 illustrates a state after removing mask 1540. Removing mask 1540 may include stripping the resist.

[0111] Stage 13 illustrates a state after optionally forming an encapsulation layer 1560. Encapsulation layer 1560 may be formed over and / or around polymer layer 140 and plurality of interconnects 142 and / or plurality of encapsulation interconnects 242. Encapsulation layer 1560 may include a molding, a resin, and / or an epoxy. Encapsulation layer 1560 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. In some implementations, the formation of encapsulation layer 1560 may be skipped.

[0112] like Fig.15F As shown in , stage 14 illustrates a state after a magnetic inlay 710 may be optionally provided on the polymer layer 140 and / or the encapsulation layer 1560. The magnetic inlay 710 may include a solid ferromagnetic inlay. The magnetic inlay 710 may be placed on the encapsulation layer 1560. In some implementations, the magnetic inlay 710 may be placed on the polymer layer 140.

[0113] Stage 15 illustrates a state after encapsulation layer 1570 is formed on encapsulation layer 1560, magnetic inlay 710, and multiple encapsulation interconnects 242. Encapsulation layer 1570 may include a molded part, a resin, and / or an epoxy resin. Encapsulation layer 1570 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. Encapsulation layer 1570 may be similar to encapsulation layer 1560. In some implementations, encapsulation layer 1560 and magnetic inlay 710 may be skipped. In such an example, encapsulation layer 1570 may be formed on polymer layer 140, multiple interconnects 142, and multiple encapsulation interconnects 242. In some implementations, encapsulation layer 1570 may include a material having magnetic properties. For example, encapsulation layer 1570 may include a ferrite ceramic as a filler. Encapsulation layer 1560 and / or encapsulation layer 1570 may be represented as encapsulation layer 240.

[0114] like Figure 15G, stage 16 illustrates a state after portions of the encapsulation layer 240 and / or the plurality of encapsulation interconnects 242 are removed. For example, portions of the encapsulation layer 240 and / or portions of the plurality of encapsulation interconnects 242 may be ground off and / or polished off. In some implementations, the plurality of encapsulation interconnects 242 may be encapsulation interconnects with a high aspect ratio, e.g., a 2:1 aspect ratio (e.g., height-to-width ratio). For example, the encapsulation interconnect may have a height of about 100 microns and a width of about 50 microns. Different implementations may have different heights, widths, and / or aspect ratios.

[0115] Stage 17 illustrates a state after forming a plurality of interconnects 1580 on polymer layer 140 and a plurality of encapsulation interconnects 242. A plating process may be used to form the plurality of interconnects 1580. In some implementations, the plurality of interconnects 1580 may be considered as part of the plurality of encapsulation interconnects 242. In some implementations, forming the plurality of interconnects 1580 may include forming a seed layer and forming a mask. A mask may be formed over the seed layer, and a plurality of interconnects 1580 may be formed over the seed layer through openings in the mask. Portions of the mask and the seed layer may be removed. Some of the encapsulation interconnects from the plurality of encapsulation interconnects 242 and some of the interconnects from the plurality of interconnects 142 may form an inductor 210.

[0116] like Fig.15H As shown in FIG. 1 , stage 18 illustrates a state after forming a high-K dielectric layer 362. The high-K dielectric layer 362 may be formed over the encapsulation interconnect 242b. The high-K dielectric layer 362 may be formed using a deposition process and / or a lamination process.

[0117] Stage 19 illustrates a state after a dielectric layer 360 is formed on the encapsulation layer 240. The dielectric layer 360 may be formed using a deposition process and / or a lamination process.

[0118] like Fig.15I As shown in FIG. 1 , stage 20 illustrates a state after forming a plurality of interconnects 262. The plurality of interconnects 262 may include an interconnect 262a coupled to and formed on a high-K dielectric layer 362. The interconnect 262a, the high-K dielectric layer 362, and the encapsulating interconnect 242b may form a capacitor 310, as shown in FIG. Figure 7 The plurality of interconnects 262 may be formed using a plating process.

[0119] Stage 21 illustrates a state after dielectric layer 260 is formed over polymer layer 140, dielectric layer 360, and plurality of interconnects 262. Dielectric layer 260 may be formed using a deposition process and / or a lamination process. Dielectric layer 260 may be similar or identical to dielectric layer 360. In some implementations, the formation of dielectric layer 260 may be skipped.

[0120] like Fig.15J, stage 22 illustrates a state after forming a plurality of interconnects 1590. The plurality of interconnects 1590 may be coupled to the plurality of interconnects 262. The plurality of interconnects 1590 may be considered a part of the plurality of interconnects 262. The plurality of interconnects 1590 may be formed using a plating process. In some implementations, the formation of the plurality of interconnects 1590 may be skipped.

[0121] Stage 23 illustrates a state after forming a plurality of interconnects 207 on the plurality of encapsulation interconnects 242. A plating process may be used to form the plurality of interconnects 207. The plurality of interconnects 207 may include a land grid array (LGA). The plurality of interconnects 207 may include one or more metal layers. The plurality of interconnects 207 may include an electroplating finish or an electroless plating finish. In some implementations, the formation of the plurality of interconnects 207 may be skipped. Stage 23 illustrates a package 700, which includes an acoustic device 102, a polymer frame 105, a polymer cover layer 104, a metallization portion 204, and a metallization portion 206.

[0122] Once the package (eg, 100, 200, 300, 700) is manufactured, the package may be coupled to the board 106 via the plurality of interconnects 207. For example, the package (eg, 100, 200, 300, 700) may be coupled to the plurality of board interconnects 162 via the plurality of interconnects 207.

[0123] Exemplary process for making a package including an acoustic device and a polymer cover layer

[0124] In some implementations, manufacturing the package includes several processes. Figures 16A-16B An exemplary process for providing or manufacturing a package including an acoustic device and a polymer cover layer is illustrated. In some implementations, Figures 16A-16B The process can be used to provide or manufacture Figure 4 of package 400. However, Figures 16A-16B The process may be used to manufacture any package described in this disclosure.

[0125] It should be noted that Figures 16A-16B The process of one or more stages can be combined to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure.

[0126] like Fig.16A, stage 1 illustrates a state after providing a substrate 406. The substrate 406 includes at least one dielectric layer 460 and a plurality of substrate interconnects 462. The at least one dielectric layer 460 may include a core layer. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a laminate substrate, a coreless substrate, a cored substrate, and / or an embedded trace substrate (ETS). The substrate 406 may be a package substrate.

[0127] Stage 2 illustrates a state after the package 200 is coupled to the first surface (eg, top surface) of the substrate 406 through the plurality of solder interconnects 407. The package 200 may be coupled to the substrate 406 using a solder reflow process.

[0128] Stage 3 illustrates a state after providing (e.g., forming) an encapsulation layer 408 on the substrate 406. The encapsulation layer 408 may encapsulate the package 200. The encapsulation layer 408 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 408 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 108 may be a means for encapsulation.

[0129] Exemplary flow chart of a method for manufacturing a package including an acoustic device and a polymer cover

[0130] In some implementations, manufacturing a package including an acoustic device and a polymer cover includes several processes. Fig.17 An exemplary flow chart of a method 1700 for providing or manufacturing a package is illustrated. In some implementations, Fig.17 The method 1700 may be used to provide or manufacture at least Figure 1-9 package.

[0131] It should be noted that Fig.17 The method 1700 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0132] The method provides (at 1705) an acoustic device (eg, 102) including a substrate and an acoustic element coupled to the substrate. Fig.15A Stage 1 of the invention illustrates an example of providing an acoustic device. Fig.12 and 13 Examples of how acoustic devices may be manufactured and provided are explained.

[0133] The method couples (at 1710) a polymer frame (e.g., 105) to the acoustic device, and couples (at 1710) a polymer cover layer to the acoustic device through the polymer frame. Coupling the polymer cover layer forms a cavity between the acoustic device and the polymer cover layer. The polymer cover layer is configured as a cover for the acoustic device. Figures 15A-15BStages 2-5 of illustrate an example of providing a polymer frame and a polymer cover layer.

[0134] The method forms (at 1715) a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device. Figures 15B-15C Stages 6-8 of illustrate an example of forming multiple interconnections in a polymer framework.

[0135] The method forms (at 1720) a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects. Figures 15B-15C Stages 6-8 of illustrative embodiments illustrate an example of forming a plurality of interconnects in a polymer cover layer. The plurality of cover interconnects may be formed during the same process as forming the plurality of frame interconnects.

[0136] The method forms (at 1725) an encapsulation layer (e.g., 240) coupled to the polymer cover layer, and forms (at 1725) a plurality of encapsulation interconnects (e.g., 242) at least in the encapsulation layer. The plurality of encapsulation interconnects are coupled to the plurality of cover interconnects. At least some of the plurality of encapsulation interconnects are configured to operate as inductors. In some implementations, magnetic material may be provided in the encapsulation layer. Figures 15B-15G Stages 9-17 of illustrative examples illustrate forming encapsulation layers and encapsulation interconnects.

[0137] The method forms (at 1730) at least one dielectric layer (e.g., 260) coupled to the encapsulation layer, and forms (at 1730) a plurality of interconnects (e.g., 262) at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects. Forming the dielectric layer and the plurality of interconnects may also include forming a capacitor including a high-K dielectric layer. Figures 15H-15J Stages 18-23 of illustrate an example of forming at least one dielectric layer and a plurality of interconnects.

[0138] Exemplary Electronic Devices

[0139] Fig.18 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 1802, a laptop computer device 1804, a fixed location terminal device 1806, a wearable device 1808, or a motor vehicle 1810 may include a device 1800 as described herein. The device 1800 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig.18The devices 1802, 1804, 1806, and 1808, and the vehicle 1810 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 1800, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0140] Figure 1-14 , 15A-15J, 16A-16B, and / or 17-18, one or more of the components, processes, features, and / or functions illustrated may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-14 , 15A-15J, 16A-16B, and / or 17-18 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figure 1-14 , 15A-15J, 16A–16B, and / or 17-18 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0141] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various parts, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0142] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the discussed features, advantages, or modes of operation. The term "coupling" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together so that current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulation" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. It is further noted that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A value of about X-XX may mean a value between X and XX (inclusive). The value(s) between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0143] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces, through holes, pads, solder posts, redistribution metal layers, and / or under bump metallization (UBM) layers. Interconnection may include one or more metal components (e.g., seed layer+metal layer). In some implementations, interconnection is a conductive material that can be configured to provide an electrical path for an electric current (e.g., data signal, grounding, or power). Interconnection can be part of a circuit. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Different implementations may use similar or different processes to form interconnection. In some implementations, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnection. For example, sputtering processes, spraying processes, and / or electroplating processes or chemical plating processes may be used to form (all) interconnections.

[0144] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0145] Further examples are described below to facilitate understanding of the present invention.

[0146] Aspect 1: A package includes: an acoustic device; a polymer frame coupled to the acoustic device; a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; a polymer cover layer coupled to the acoustic device through the polymer frame, wherein the polymer cover layer is configured as a cover for the acoustic device; a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects; and a cavity between the acoustic device and the polymer cover layer. The acoustic device includes a substrate and an acoustic element coupled to the substrate.

[0147] Aspect 2: The package of aspect 1, wherein the plurality of cover interconnects are coupled to the acoustic device through the plurality of frame interconnects.

[0148] Aspect 3: A package as in Aspects 1 to 2, further comprising: an encapsulation layer coupled to the polymer cover layer; and a plurality of encapsulation interconnects located at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects, and wherein at least some of the plurality of encapsulation interconnects are configured to operate as inductors.

[0149] Aspect 4: The package of aspect 3, wherein the encapsulation layer comprises a magnetic material having a magnetic permeability of 1 or greater.

[0150] Aspect 5: The package of aspect 4, wherein the magnetic material comprises ferrite ceramic as a filler for the encapsulation layer.

[0151] Aspect 6: The package of Aspect 3, further comprising: a magnetic inlay located in the encapsulation layer.

[0152] Aspect 7: The package of Aspect 6, wherein the magnetic inlay comprises a ferromagnetic inlay.

[0153] Aspect 8: The package of aspects 3 to 7, further comprising: at least one dielectric layer coupled to the encapsulation layer; and a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects.

[0154] Aspect 9: A package as in Aspects 3 to 7, further comprising: a high-K dielectric layer coupled to an encapsulation interconnect from the plurality of encapsulation interconnects; at least one dielectric layer coupled to the encapsulation layer; and a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects, wherein an interconnect from the plurality of interconnects is coupled to the high-K dielectric layer, and wherein the encapsulation interconnect, the high-K dielectric layer, and the interconnect are configured to operate as a capacitor.

[0155] Aspect 10: The package of aspects 3 to 9, wherein the plurality of encapsulated interconnects includes at least one encapsulated interconnect, the at least one encapsulated interconnect including an aspect ratio of about 2:1 or greater.

[0156] Aspect 11: The package of Aspects 1 to 10, further comprising: a packaging substrate coupled to the multiple cover interconnects via multiple solder interconnects so that the back side of the acoustic device faces away from the packaging substrate; and an encapsulation layer coupled to the packaging substrate, the polymer cover layer, the polymer frame and the acoustic device.

[0157] Aspect 12: The package of aspect 11, wherein the substrate comprises a plurality of interconnects, and wherein at least some interconnects from the plurality of interconnects, at least some solder interconnects from the plurality of solder interconnects, and at least some lid interconnects from the plurality of lid interconnects are configured to operate as inductors.

[0158] Aspect 13: The package of Aspects 1 to 2, further comprising: an encapsulation layer coupled to the polymer cover layer; a plurality of encapsulation interconnects at least located in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects; a packaging substrate coupled to the plurality of encapsulation interconnects via a plurality of solder interconnects so that the back side of the acoustic device faces away from the packaging substrate; and a second encapsulation layer coupled to the packaging substrate, the encapsulation layer, the polymer cover layer, the polymer frame and the acoustic device.

[0159] Aspect 14: The package of Aspects 1 to 2, further comprising: an encapsulation layer coupled to the polymer cover layer; a plurality of encapsulation interconnects at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects; at least one dielectric layer coupled to the encapsulation layer; a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects; a packaging substrate coupled to the plurality of interconnects via a plurality of solder interconnects so that the back side of the acoustic device faces away from the packaging substrate; and a second encapsulation layer coupled to the packaging substrate, the at least one dielectric layer, the encapsulation layer, the polymer cover layer, the polymer frame, and the acoustic device.

[0160] Aspect 15: The package of aspects 1 to 14, wherein the polymer frame comprises a different material than the polymer cap layer.

[0161] Aspect 16: The package of aspects 1 to 15, wherein the minimum height of the cavity is about 4 microns.

[0162] Aspect 17: The package of aspects 1 to 16, wherein the acoustic device is configured to operate as a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter.

[0163] Aspect 18: An apparatus comprising an acoustic device; a polymer frame coupled to the acoustic device; a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; a polymer cover layer coupled to the acoustic device through the polymer frame, wherein the polymer cover layer is configured as a cover for the acoustic device; a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects; and a cavity between the acoustic device and the polymer cover layer. The acoustic device comprises a substrate and an acoustic element coupled to the substrate.

[0164] Aspect 19: The device of Aspect 18 further comprises: an encapsulation layer coupled to the polymer cover layer; and a plurality of encapsulation interconnects located at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects, and wherein at least some of the plurality of encapsulation interconnects are configured to operate as inductors.

[0165] Aspect 20: The apparatus of Aspect 19, wherein the encapsulation layer comprises a magnetic material having a magnetic permeability of 1 or greater.

[0166] Aspect 21: The device of aspects 19 to 20, further comprising: a magnetic inlay located in the encapsulation layer.

[0167] Aspect 22: The apparatus of aspects 19 to 21, further comprising: at least one dielectric layer coupled to the encapsulation layer; and a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects.

[0168] Aspect 23: The device of Aspects 19 to 21 further comprises: a high-K dielectric layer coupled to an encapsulation interconnect from the plurality of encapsulation interconnects; at least one dielectric layer coupled to the encapsulation layer; and a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects, wherein an interconnect from the plurality of interconnects is coupled to the high-K dielectric layer, and wherein the encapsulation interconnect, the high-K dielectric layer, and the interconnect are configured to operate as a capacitor.

[0169] Aspect 24: The apparatus of aspects 18 to 23, wherein the acoustic device, the polymer frame, and the polymer cover are part of a package.

[0170] Aspect 25: A device as in Aspects 18 to 24, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0171] Aspect 26: A method for manufacturing a package. The method provides an acoustic device including a substrate and an acoustic element coupled to the substrate. The method couples a polymer frame to the acoustic device. The method couples a polymer cover layer to the acoustic device through the polymer frame. Wherein coupling the polymer cover layer forms a cavity between the acoustic device and the polymer cover layer, and wherein the polymer cover layer is configured as a cover for the acoustic device. The method forms a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device. The method forms a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects.

[0172] Aspect 27: The method of Aspect 26 further includes: forming an encapsulation layer coupled to the polymer cover layer; and forming a plurality of encapsulation interconnects at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects, and wherein at least some of the plurality of encapsulation interconnects are configured to operate as inductors.

[0173] Aspect 28: The method of aspect 27, further comprising: providing a magnetic inlay located in the encapsulation layer.

[0174] Aspect 29: The method of aspects 27 to 28, further comprising: forming at least one dielectric layer coupled to the encapsulation layer; and forming a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects.

[0175] Aspect 30: The method of Aspects 27 to 28, further comprising: forming a high-K dielectric layer coupled to an encapsulation interconnect from the plurality of encapsulation interconnects; forming at least one dielectric layer coupled to the encapsulation layer; and forming a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects, wherein the interconnects from the plurality of interconnects are coupled to the high-K dielectric layer, and wherein the encapsulation interconnect, the high-K dielectric layer, and the interconnect are configured to operate as a capacitor.

[0176] The various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the various aspects. Thus, the teachings of the present disclosure can be readily applied to other types of devices, and many replacements, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: An acoustic device, comprising: substrate; and an acoustic element coupled to the substrate; a polymer frame coupled to the acoustic device; a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; a polymer cover layer coupled to the acoustic device through the polymer frame, wherein the polymer cover layer is configured as a cover for the acoustic device; a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects; and A cavity is located between the acoustic device and the polymer cover layer. 2 . The package of claim 1 , wherein the plurality of cover interconnects are coupled to the acoustic device through the plurality of frame interconnects.

3. The package of claim 1, further comprising: an encapsulation layer coupled to the polymer cap layer; as well as a plurality of encapsulation interconnections at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects, and Wherein at least some of the plurality of encapsulated interconnects are configured to operate as inductors. The package of claim 3 , wherein the encapsulation layer comprises a magnetic material having a magnetic permeability of 1 or more.

5. The package of claim 4, wherein the magnetic material comprises ferrite ceramic as a filler for the encapsulation layer.

6. The package of claim 3, further comprising: A magnetic inlay is located in the encapsulating layer.

7. The package of claim 6, wherein the magnetic inlay comprises a ferromagnetic inlay.

8. The package of claim 3, further comprising: at least one dielectric layer coupled to the encapsulation layer; as well as A plurality of interconnects are located at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulating interconnects.

9. The package of claim 3, further comprising: a high-K dielectric layer coupled to an encapsulation interconnect from the plurality of encapsulation interconnects; at least one dielectric layer coupled to the encapsulation layer; as well as a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulating interconnects, wherein an interconnect from the plurality of interconnects is coupled to the high-K dielectric layer, and Wherein the encapsulating interconnect, the high-K dielectric layer, and the interconnect are configured to operate as a capacitor.

10. The package of claim 3, wherein the plurality of encapsulated interconnects comprises at least one encapsulated interconnect comprising an aspect ratio of approximately 2:1 or greater.

11. The package of claim 1, further comprising: a package substrate coupled to the plurality of cover interconnects by a plurality of solder interconnects such that a back side of the acoustic device faces away from the package substrate; as well as An encapsulation layer is coupled to the packaging substrate, the polymer cover layer, the polymer frame, and the acoustic device.

12. The package according to claim 11, wherein the package substrate comprises a plurality of interconnects, and Wherein at least some interconnects from the plurality of interconnects, at least some solder interconnects from the plurality of solder interconnects, and at least some cover interconnects from the plurality of cover interconnects are configured to operate as inductors.

13. The package of claim 1, further comprising: an encapsulation layer coupled to the polymer cap layer; a plurality of encapsulation interconnects at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of lid interconnects; a packaging substrate coupled to the plurality of encapsulation interconnects via a plurality of solder interconnects such that a back side of the acoustic device faces away from the packaging substrate; as well as A second encapsulation layer is coupled to the packaging substrate, the encapsulation layer, the polymer cover layer, the polymer frame, and the acoustic device.

14. The package of claim 1, further comprising: an encapsulation layer coupled to the polymer cap layer; a plurality of encapsulation interconnects at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of lid interconnects; at least one dielectric layer coupled to the encapsulation layer; a plurality of interconnects disposed at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects; a package substrate coupled to the plurality of interconnects via a plurality of solder interconnects such that a back side of the acoustic device faces away from the package substrate; as well as A second encapsulation layer is coupled to the packaging substrate, the at least one dielectric layer, the encapsulation layer, the polymer cover layer, the polymer frame, and the acoustic device.

15. The package of claim 1 wherein the polymer frame comprises a different material than the polymer cap layer.

16. The package of claim 1 wherein the minimum height of the cavity is approximately 4 microns.

17. The package of claim 1, wherein the acoustic device is configured to operate as a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter.

18. A device comprising: An acoustic device, comprising: substrate; and an acoustic element coupled to the substrate; a polymer frame coupled to the acoustic device; a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; a polymer cover layer coupled to the acoustic device through the polymer frame, wherein the polymer cover layer is configured as a cover for the acoustic device; a plurality of cover interconnects in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects; and A cavity is located between the acoustic device and the polymer cover layer.

19. The apparatus of claim 18, further comprising: an encapsulation layer coupled to the polymer cap layer; as well as a plurality of encapsulation interconnections at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects, and Wherein at least some of the plurality of encapsulated interconnects are configured to operate as inductors.

20. The apparatus of claim 19, wherein the encapsulation layer comprises a magnetic material having a magnetic permeability of 1 or greater.

21. The device of claim 19, further comprising a magnetic inlay located in the encapsulation layer.

22. The apparatus of claim 19, further comprising: at least one dielectric layer coupled to the encapsulation layer; as well as A plurality of interconnects are located at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulating interconnects.

23. The apparatus of claim 19, further comprising: a high-K dielectric layer coupled to an encapsulation interconnect from the plurality of encapsulation interconnects; at least one dielectric layer coupled to the encapsulation layer; as well as a plurality of interconnects at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulating interconnects, wherein an interconnect from the plurality of interconnects is coupled to the high-K dielectric layer, and Wherein the encapsulating interconnect, the high-K dielectric layer, and the interconnect are configured to operate as a capacitor.

24. The apparatus of claim 18, wherein the acoustic device, the polymer frame, and the polymer cover are part of a package.

25. The device of claim 18, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

26. A method for manufacturing a package, comprising: An acoustic device is provided, the acoustic device comprising: substrate; and an acoustic element coupled to the substrate; coupling a polymer frame to the acoustic device; coupling a polymer cover layer to the acoustic device via the polymer frame, wherein coupling the polymer cover layer forms a cavity between the acoustic device and the polymer cover layer, and wherein the polymer cover layer is configured as a cover for the acoustic device; forming a plurality of frame interconnects in the polymer frame, wherein the plurality of frame interconnects are coupled to the acoustic device; A plurality of cover interconnects are formed in the polymer cover layer, wherein the plurality of cover interconnects are coupled to the plurality of frame interconnects.

27. The method of claim 26, further comprising: forming an encapsulation layer coupled to the polymer cap layer; as well as forming a plurality of encapsulation interconnects at least in the encapsulation layer, wherein the plurality of encapsulation interconnects are coupled to the plurality of cover interconnects, and Wherein at least some of the plurality of encapsulated interconnects are configured to operate as inductors.

28. The method of claim 27, further comprising: A magnetic inlay is provided in the encapsulating layer.

29. The method of claim 27, further comprising: forming at least one dielectric layer coupled to the encapsulation layer; as well as A plurality of interconnects are formed at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulation interconnects.

30. The method of claim 27, further comprising: forming a high-K dielectric layer coupled to an encapsulation interconnect from the plurality of encapsulation interconnects; forming at least one dielectric layer coupled to the encapsulation layer; as well as forming a plurality of interconnections at least in the at least one dielectric layer, wherein the plurality of interconnects are coupled to the plurality of encapsulating interconnects, wherein an interconnect from the plurality of interconnects is coupled to the high-K dielectric layer, and Wherein the encapsulating interconnect, the high-K dielectric layer, and the interconnect are configured to operate as a capacitor.

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