BCC low coding rate design for next generation WLAN

Abstract

Techniques for binary convolutional code (BCC) low coding rate design related to a next generation wireless local area network (WLAN) are described. A processor of a device (e.g., a station (STA)) receives and encodes a string of input bits. When encoding the input bits, the processor encodes the input bits by a BCC encoder of the processor using a basic encoding rate. The processor also repeats the output of the BCC encoder by a repetition circuit of the processor to obtain an effective coding rate of the input bits lower than the base coding rate.

Description

[0001] Cross-references

[0002] The present disclosure is part of a non-provisional patent application claiming priority to U.S. Provisional Patent Application No. 63 / 353,084 filed on June 17, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to wireless communications, and more particularly to a low coding rate binary convolutional code (BCC) design for next generation wireless local area network (WLAN). Background Art

[0004] Unless otherwise indicated, the approaches described in this section are not prior art to the claims listed below and are not admitted to be prior art by inclusion in this section.

[0005] Regarding wireless communications, for example, according to the Institute of Electrical and Electronics Engineer (IEEE) 802.11 standard, enhanced long range (ELR) Wi-Fi (or WiFi) is one of the main goals of the next generation of Wi-Fi. However, the design of how to utilize the BCC low coding rate in the next generation WLAN has yet to be defined or specified. Therefore, it is necessary to solve the BCC low coding rate design problem for the next generation WLAN. Summary of the invention

[0006] The following summary is for illustration only and is not limiting in any way. This summary is intended to introduce the concepts, highlights, benefits, and advantages of the novel and non-obvious technologies described herein. Selected implementations are further described in the detailed description below. Therefore, this summary is not intended to identify essential features of the claimed subject matter, nor is it used to determine the scope of the claimed subject matter.

[0007] The purpose of the present disclosure is to provide schemes, concepts, designs, techniques, methods and devices for BCC low coding rate design for next generation WLAN. In addition, under various schemes, a new robust modulation and coding scheme (MCS) design with BCC low coding rate is also proposed.

[0008] In one aspect, a method may involve receiving a sequence of input bits. The method may also involve encoding the sequence of input bits by: (i) a BCC encoder of a processor encoding the input bits using a base coding rate; and (ii) a repetition circuit of the processor repeating an output of the BCC encoder such that an effective coding rate of the input bits is less than the base coding rate.

[0009] In another aspect, an apparatus may include a transceiver configured for wireless communication and a processor coupled to the transceiver. The processor may receive a sequence of input bits. The processor may also encode the sequence of input bits by: (i) a BCC encoder of the processor encodes the input bits using a base coding rate; and (ii) a repetition circuit of the processor repeats an output of the BCC encoder so that an effective coding rate of the input bits is lower than the base coding rate.

[0010] It is worth noting that although the description provided herein may be in the context of a specific radio access technology, network, and network topology such as Wi-Fi, the proposed concepts, solutions, and any variations / derivatives thereof may be implemented in, for, and by other types of radio access technologies, networks, and network topologies, such as, but not limited to, Bluetooth, ZigBee, Fifth Generation (5G) / New Radio (NR), Long-Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, Internet-of-Things (IoT), Industrial IoT (IIoT), and narrowband IoT (NB-IoT). Therefore, the scope of the present disclosure is not limited to the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to further understand this article and are incorporated as part of this article and constitute this article. The accompanying drawings, together with the description of this article, illustrate embodiments of the present disclosure and are used to explain the concepts of the present disclosure. It is worth noting that since some components may be shown as being out of proportion to the size in actual implementation, the drawings are not necessarily drawn to scale to clearly illustrate the concepts of the present disclosure.

[0012] Figure 1 is a schematic diagram of an example network environment in which various solutions and schemes according to the present disclosure may be implemented.

[0013] Figure 2 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0014] Figure 3is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0015] Figure 4 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0016] Figure 5 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0017] Figure 6 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0018] Figure 7 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0019] Figure 8 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0020] Fig. 9 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0021] Fig.10 is a schematic diagram of an example design according to a proposed scheme of the present disclosure.

[0022] Fig.11 is a block diagram of an example communication system according to an embodiment of the present disclosure.

[0023] Fig.12 is an example flow chart according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Detailed embodiments and implementations of the claimed subject matter are disclosed herein. However, it should be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matter, which may be embodied in various forms. However, the present disclosure may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments and implementations set forth herein. On the contrary, these exemplary embodiments and implementations are provided to make the description of the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. In the following description, details of well-known features and technologies may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

[0025] Overview

[0026] Embodiments according to the present disclosure relate to various technologies, methods, schemes or solutions related to BCC low coding rate design for next generation WLAN. According to the present disclosure, multiple possible solutions can be implemented individually or in combination. That is, although these possible solutions may be described separately below, two or more of the possible solutions can be implemented in one combination or another combination.

[0027] Figure 1 An example network environment 100 is shown in which various solutions and schemes based on the present disclosure may be implemented. Figures 2 to 12 An example implementation of various proposed solutions in a network environment 100 based on the present disclosure is shown. Figures 1 to 12 , descriptions of various schemes are provided below.

[0028] refer to Figure 1 , the network environment 100 may involve at least a station (STA) 110 and a STA 120 for wireless communication. Any of the STA 110 and the STA 120 may be an access point (AP) STA, or any of the STA 110 and the STA 120 may act as a non-AP STA. In some cases, the STA 110 and the STA 120 may be associated with a basic service set (BSS) according to one or more IEEE 802.11 standards (e.g., IEEE 802.11be and future standards). Each of the STAs 110 and 120 may be configured to communicate with each other by using a BCC low coding rate design for a next generation WLAN based on various proposed schemes. That is, any one or both of the STA 110 and the STA 120 may act as a "user" in the proposed schemes and examples described below. It is worth noting that although the various proposed schemes may be described separately or separately below, in actual implementation, some or all of the proposed schemes may be utilized or otherwise implemented in combination. Of course, each of the proposed solutions may be utilized or otherwise implemented individually or separately.

[0029] Figure 2 An example design 200 according to the proposed scheme of the present disclosure is shown. Design 200 involves BCC low coding rate and repetition. Figure 2The various functions and / or operations involved in encoding a sequence of data and / or information bits to achieve a BCC low coding rate for next generation WLAN may involve a BCC encoding operation (e.g., by a BCC encoder 210), a repetition operation (e.g., by a repetition circuit 220), an interleaving function (e.g., by an interleaver 230), and a quadrature amplitude modulation (QAM) mapping function (e.g., by a QAM mapper 240). Under the proposed scheme, the basic coding rate (R) used in the design 200 may be 1 / 2, 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, or 1 / 8. In addition, under the proposed scheme, the repetition of the codeword or output data utilized in the design 200 may be 1x (repeated once), 2x (repeated twice), 3x (repeated three times), 4x (repeated four times), 6x (repeated six times), or 8x (repeated eight times) to achieve a low effective coding rate lower than the basic coding rate. Under the proposed scheme, there may be different options (option-1, option-2 and option-3) regarding the repetition pattern. For example, with R=1 / 2 as the basic coding rate, in the case of x2 repetition, in option-1, the repetition pattern may be x1,x2,x3,…,xn,x1,x2,x3,…,xn. In option-2, the repetition pattern may be x1,x1,x2,x2,…,xn,xn. In option-3, the repetition pattern may be x1,x2,x1,x2,x3,x4,x3,x4,…x(n-1),xn.

[0030] Figure 3 An example design 300 according to the proposed scheme of the present disclosure is shown. In the design 300, the basic coding rate R=1 / 2, and the number of bits (k) input to the encoder (e.g., BCC encoder 210) at one time=7. In addition, in the design 300, the polynomial may include g0=133 o , g1=171 o , g0 = [1011011] b , g1 = [1111001] b Under option-1, after encoding, the BCC codeword may be repeated Nx times to obtain the codeword repetition pattern [A, B, ...][A, B, ...], ..., [A, B, ...]. Under option-2, the output of each branch may be repeated Nx times to obtain the repetition pattern [A, A, ..., A, B, B, ..., B, ...]. Under option-3, the outputs from both branches may be repeated Nx times to obtain the repetition pattern {A, B, A, B, ..., A, B, ...].

[0031] Figure 4An example design 400 according to the proposed scheme of the present disclosure is shown. In the design 400, the basic coding rate R=1 / 3, and k=7. In addition, in the design 400, the polynomial may include g0=133 o , g1=171 o , g2=165 o , g0 = [1011011] b , g1 = [1111001] b , g2 = [1110101] b Under option-1, after encoding, the BCC codeword may be repeated Nx times to obtain the codeword repetition pattern [A, B, C, ...][A, B, C, ...], ..., [A, B, C, ...]. Under option-2, the output of each branch may be repeated Nx times to obtain the repetition pattern [A, A, ..., A, B, B, ..., B, C, C, ..., C, ...]. Under option-3, the outputs from the three branches may be repeated Nx times to obtain the repetition pattern {A, B, C, A, B, C, ..., A, B, C, ...].

[0032] Figure 5 An example design 500 according to the proposed scheme of the present disclosure is shown. In the design 500, the basic coding rate R=1 / 4, and k=7. In addition, in the design 500, the polynomial may include g0=133 o , g1=171 o , g2=165 o , g3=117 o , g0 = [1011011] b , g1 = [1111001] b , g2 = [1110101] b , g3 = [1001111] b . It is worth noting that alternative values ​​of g3 may include [113, 123, 127, 135, 137, 145, 153, 155, 157, 173, 175]. Under option-1, after encoding, the BCC codeword may be repeated Nx times to obtain the codeword repetition pattern [A, B, C, D, ...][A, B, C, D, ...], ..., [A, B, C, D, ...]. Under option-2, the output of each branch may be repeated Nx times to obtain the repetition pattern [A, A, ..., A, B, B, ..., B, C, C, ..., C, D, D, ..., D, ...]. Under option-3, the outputs from the four branches may be repeated Nx times to obtain the repetition pattern {A, B, C, D, A, B, C, D, ..., A, B, C, D, ...].

[0033] Figure 6An example design 600 according to the proposed scheme of the present disclosure is shown. In the design 600, the basic coding rate R=1 / 5, and k=7. In addition, in the design 600, the polynomial may include g0=133 o , g1=171 o , g2=165 o , g3=117 o , g4=135 o , g0 = [1011011] b , g1 = [1111001] b , g2 = [1110101] b , g3 = [1001111] b , g4 = [1011101] b .

[0034] Figure 7 An example design 700 according to the proposed scheme of the present disclosure is shown. In the design 700, the basic coding rate R=1 / 8, and k=7. In addition, in the design 700, the polynomial may include g0=133 o , g1=171 o , g2=165 o , g3=117 o , g4=135 o , g5=157 o , g6=123 o , g7=145 o , g0 = [1011011] b , g1 = [1111001] b , g2 = [1110101] b , g3 = [1001111] b , g4 = [1011101] b , g5 = [1101111] b , g6 = [1010011] b , g7 = [1100101] bUnder option-1, after encoding, the BCC codeword may be repeated Nx times to obtain the codeword repetition pattern [A, B, C, D, E, F, G, H, …][A, B, C, D, E, F, G, H, …], …, [A, B, C, D, E, F, G, H, …]. Under option-2, the output of each branch may be repeated Nx times to obtain the repetition pattern [A, A, …, A, B, B, …, B, C, C, …, C, D, D, …, D, E, E, …, E, F, F, .., F, G, G, …, G, H, H, …H, …]. Under option-3, the outputs from the eight branches may be repeated Nx times to obtain the repeating pattern {A, B, C, D, E, F, G, H, A, B, C, D, E, F, G, H, …, A, B, C, D, E, F, G, H, …].

[0035] Under various proposed schemes according to the present disclosure, when k=7 and R=1 / 6, the polynomial may include g0=133 o , g1=171 o , g2=165 o , g3=117 o , g4=135 o , g5=157 o , g0 = [1011011] b , g1 = [1111001] b , g2 = [1110101] b , g3 = [1001111] b , g4 = [1011101] b , g5 = [1101111] b In addition, when k = 7 and R = 1 / 7, the polynomial can include g0 = 133 o , g1=171 o , g2=165 o , g3=117 o , g4=135 o , g5=157 o , g6=123 o , g0 = [1011011] b , g1 = [1111001] b , g2 = [1110101] b , g3 = [1001111] b , g4 = [1011101] b , g5 = [1101111] b , g6 = [1010011] b In addition, when k=7 and R=1 / 8, the polynomial may include g0=133 o, g1=171 o , g2=165 o , g3=117 o , g4=135 o , g5=157 o , g6=123 o , g7=145 o , g0 = [1011011] b , g1 = [1111001] b , g2 = [1110101] b , g3 = [1001111] b , g4 = [1011101] b , g5 = [1101111] b , g6 = [1010011] b , g7 = [1100101] b .

[0038] Figure 8 An example design 800 according to the proposed scheme of the present disclosure is shown. In the proposed scheme, the basic coding rate can be 1 / 2 or other rates, such as any existing coding rate in IEEE 802.11ax / be, R=1 / 2, 2 / 3, 3 / 4, 5 / 6, etc. The number of repetitions (Nx) can be any integer, such as Nx=2, 3, 4, etc. See Figure 8 The table in design 800 shows the effective coding rate (eR) according to different basic coding rates (e.g., 1 / 2, 2 / 3, 3 / 4, 5 / 6) and different repetition numbers (Nx). Low coding rate (LCR) can be applied to any modulation scheme, such as binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), 16 quadrature amplitude modulation (16QAM), etc.

[0039] Fig. 9 An example design 900 according to the proposed scheme of the present disclosure is shown. In the proposed scheme, in addition to performing repetition, different low coding rates R=1 / 2, 1 / 3, 1 / 4, 1 / 6, 1 / 8 can also be used to achieve a lower effective coding rate (eR), such as eR=1 / 4, 1 / 6, 1 / 8, 1 / 12, 1 / 16, 1 / 24, 1 / 32 or Fig. 9 Any other coding rate listed in the table in design 900 shown.

[0040] Fig.10 An example design 1000 according to the proposed scheme of the present disclosure is shown. From various low coding rate simulations under the proposed scheme, it can be found that to achieve the same throughput or data rate, QPSK (having a relatively higher modulation rate than BPSK) combined with a low coding rate can often achieve better performance than BPSK (having a relatively lower modulation rate than QPSK) combined with R=1 / 2 or BPSK / R=1 / 2+dual carrier modulation (DCM). The simulation parameters include: 20MHz bandwidth, 242-tone resource unit (RU), one spatial stream (ss), single transmission and single reception (1T1R), estimated channel state, BCC coding and no beamforming. Reference Fig.10 , the table in design 1000 summarizes some performance comparison results of the following comparisons: (1) IEEE 802.11be MCS0 (BPSK+R=1 / 2) with QPSK+R=1 / 4; (2) IEEE 802.11be MCS15 (BPSK / R=1 / 2+DCM) with QPSK+R=1 / 8. Therefore, under the proposed scheme, the following MCS options for low coding rates are utilized to achieve robustness and reliable communication: (a) the first new MCS (MCS-x) includes QPSK+R=1 / 4; and (b) the second new MCS (MCS-y) includes QPSK+R=1 / 8.

[0041] Illustrative Embodiments

[0042] Fig.11 An example system 1100 having at least an example device 1110 and an example device 1120 according to an embodiment of the present invention is shown. Each of the devices 1110 and 1120 can perform various functions to implement the schemes, techniques, processes and methods described herein for BCC low coding rate design for next generation WLAN, including the various proposed designs, concepts, schemes, systems and methods described above and the processes described below. For example, the device 1110 can be implemented in the STA 110, the device 1120 can be implemented in the STA 120, or vice versa.

[0043] Each of the devices 1110 and 1120 may be part of an electronic device, which may be a non-AP STA or an AP STA, such as a portable or mobile device, a wearable device, a wireless communication device, or a computing device. When implemented in a STA, each of the devices 1110 and 1120 may be implemented in a smart phone, a smart watch, a personal digital assistant, a digital camera, or a computing device (such as a tablet, a laptop, or a notebook computer). Each of the devices 1110 and 1120 may also be part of a machine-type device, which may be an Internet of Things (IoT) device, such as a non-mobile or fixed device, a home device, a wired communication device, or a computing device. For example, each of the devices 1110 and 1120 may be implemented in a smart thermostat, a smart refrigerator, a smart door lock, a wireless speaker, or a home control center. When implemented in a network device or as a network device, the device 1110 and / or the device 1120 may be implemented in a network node, such as an AP in a WLAN.

[0044] In some embodiments, each of the devices 1110 and 1120 may be implemented in the form of one or more integrated-circuit (IC) chips, such as but not limited to one or more single-core processors, one or more multi-core processors, one or more reduced instruction set computers, or a plurality of integrated circuits.

[0045] (reduced-instruction set computing, RISC) processor or one or more complex instruction set computing (complex-instruction-set-computing, CISC) processors. In the above various schemes, the device 1110 and the device 1120 can be implemented in a STA or an AP or implemented as a STA or an AP. For example, each of the devices 1110 and 1120 includes at least Fig.11 110 and 1120. Each of the devices 1110 and 1120 may also include one or more other components (such as an internal power supply, a display device, and / or a user interface device) that are not related to the proposed solution of the present disclosure, so for the sake of simplicity and brevity, Fig.11 These components of device 1110 and device 1120 are not shown in the figure and are not described in the following content.

[0046] In one aspect, processor 1112 and processor 1122 may be implemented in the form of one or more single-core processors, one or more multi-core processors, one or more RISC processors, or one or more CISC processors. That is, although a singular word "processor" is used herein to refer to processor 1112 and processor 1122, according to the present disclosure, in some embodiments, each of processor 1112 and processor 1122 may include multiple processors, while in other embodiments, they may include a single processor. In another aspect, each of processor 1112 and processor 1122 may be implemented in the form of hardware (and optionally, firmware) having electronic components, wherein the electronic components include, but are not limited to, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors, and / or one or more varactors, which are configured and arranged to achieve specific purposes according to the present disclosure. In other words, in at least some embodiments, each of processors 1112 and processor 1122 is a special-purpose machine specifically designed, arranged, and configured to perform specific tasks, including tasks related to BCC low coding rate design for next generation WLANs based on various embodiments of the present disclosure.

[0047] In some embodiments, the device 1110 may also include a transceiver 1116 coupled to the processor 1112. The transceiver 1116 may include a transmitter capable of wirelessly transmitting data and a receiver capable of wirelessly receiving data. In some embodiments, the device 1120 may also include a transceiver 1126 coupled to the processor 1122. The transceiver 1126 may include a transmitter capable of wirelessly transmitting data and a receiver capable of wirelessly receiving data. It is worth noting that although the transceiver 1116 and the transceiver 1126 are shown to be external to the processor 1112 and the processor 1122 and separate from the processor 1112 and the processor 1122, respectively, in some embodiments, the transceiver 1116 may be an integrated part of the processor 1112 as a system on chip (SoC), and the transceiver 1126 may be an integrated part of the processor 1122 as a SoC.

[0048] In some embodiments, the device 1110 may further include a memory 1114 coupled to the processor 1112 and accessible to the processor 1112 and storing data therein. In some embodiments, the device 1120 may further include a memory 1124 coupled to the processor 1122 and accessible to the processor 1122 and storing data therein. Each of the memory 1114 and the memory 1124 may include a random-access memory (RAM), such as a dynamic RAM (DRAM), a static RAM (SRAM), a thyristor RAM (T-RAM) and / or a zero-capacitor RAM (Z-RAM). Alternatively, each of the memory 1114 and the memory 1124 may also include a read-only memory (ROM), such as a mask ROM, a programmable ROM (PROM), an erasable programmable ROM (EPROM) and / or an electrically erasable programmable ROM (EEPROM). Alternatively, each of the memory 1114 and the memory 1124 may also include a non-volatile random-access memory (NVRAM), such as a flash memory, a solid-state memory, a ferroelectric RAM (FeRAM), a magnetoresistive RAM (MRAM) and / or a phase-change memory.

[0049] Each of the devices 1110 and 1120 may be a communication entity capable of communicating with each other using various proposed schemes based on the present disclosure. For illustrative purposes and not limitation, the capabilities of the device 1110 as STA 110 and the device 1120 as STA 120 are described below. It is worth noting that although a detailed description of the capabilities, functions and / or technical features of the device 1120 is provided below, the same description may be applied to the device 1110, although for the sake of brevity, a detailed description of the device 1110 is not provided separately. It is also worth noting that although the example embodiments described below are provided in the context of a WLAN, the same embodiments may also be implemented in other types of networks.

[0050] In various proposed schemes related to the BCC low coding rate design for the next generation WLAN according to the present disclosure, in the network environment 100, the device 1110 is implemented in or as the STA 110, the device 1120 is implemented in or as the STA 120, and the processor 1112 of the device 1110 can receive a string of input bits. In addition, the processor 1112 can encode the string of input bits. For example, the processor 1112 can encode the input bits using a basic coding rate through the BCC encoder 210 of the processor 1112. In addition, the processor 1112 can repeat the output of the BCC encoder through the repetition circuit 220 of the processor 1112, thereby causing the effective coding rate of the input bits to be lower than the basic coding rate.

[0051] In some embodiments, the basic coding rate can be 1 / 2, 1 / 3, 1 / 4, 1 / 6, 1 / 8, 2 / 3, 3 / 4 or 5 / 6.

[0052] In some embodiments, when repeating the output of the BCC encoder, the processor 1112 may repeat a codeword generated by the BCC encoder multiple times, where the codeword includes a combination of output data from multiple output branches of the BCC encoder (eg, Option-1 as described above).

[0053] Alternatively, when repeating the output of the BCC encoder, the processor 1112 may repeat the respective output data of each output branch of the BCC encoder multiple times, thereby generating multiple repetitions of the first output data of the first output branch of the BCC encoder, and subsequently multiple repetitions of the second output data of the second output branch of the BCC encoder (e.g., as described in Option-2 above).

[0054] Alternatively, when repeating the output of the BCC encoder, the processor 1112 may repeat the combination of output data of multiple output branches of the BCC encoder multiple times, so that in each repetition, the combination of output data includes the first output data of the first output branch of the BCC encoder, and the second output data of the second output branch of the following BCC encoder (for example, as described in Option-3).

[0055] In some embodiments, the basic coding rate may be 1 / 2, 2 / 3, 3 / 4, or 5 / 6. In this case, in the repetition, the processor 1112 may repeat 1 time, 2 times, 3 times, 4 times, 6 times, 8 times, 12 times, or 16 times. Alternatively, the basic coding rate may be 1 / 2, 1 / 3, 1 / 4, 1 / 6, or 1 / 8. In this case, in the repetition, the processor 1112 may repeat 1 time, 2 times, 3 times, 4 times, 6 times, or 8 times.

[0056] In some embodiments, when encoding the string of input bits, the processor 1112 may encode the string of input bits using QPSK and an MCS of a basic coding rate of 1 / 4. Alternatively, when encoding the string of input bits, the processor 1112 may encode the string of input bits using QPSK and an MCS of a basic coding rate of 1 / 8.

[0057] In some embodiments, the processor 1112 may perform additional operations when encoding the string of input bits. For example, the processor 1112 may interleave the output of the repetition circuit through the interleaver 230 of the processor 1112. In addition, the processor 1112 may map the output of the interleaver through the QAM mapper 240 of the processor 1112.

[0058] Illustrative Process

[0059] Fig.12 An example process 1200 according to an embodiment of the present disclosure is shown. Process 1200 may represent aspects of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 1200 may represent aspects of proposed concepts and schemes related to BCC low coding rate designs for next generation WLANs based on the present disclosure. Process 1200 may include one or more operations, actions, or functions as shown in one or more of blocks 1210 and 1220 and sub-blocks 1222 and 1224. Although shown as discrete blocks, the various blocks of process 1200 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. In addition, the blocks / sub-blocks of process 1200 may be arranged in blocks 1210 and 1220. Fig.12110 and 1120, or, in a different order. In addition, one or more blocks / subblocks of process 1200 may be repeatedly or iteratively performed. Process 1200 may be implemented by or in device 1110 and device 1120 and any variants thereof. For illustrative purposes only and without limiting the scope, process 1200 is described below in the context of device 1110 implemented in STA 110 (acting as a non-AP STA of a wireless network (e.g., a WLAN based on one or more standards of the IEEE 802.11 standard in the network environment 120) or as STA 110 (acting as a non-AP STA), and device 1120 implemented in STA 120 (acting as an AP STA of a wireless network (a WLAN based on one or more standards of the IEEE 802.11 standard in the network environment 120) or as STA 120. Process 1200 may start at block 1210.

[0060] At 1210, process 1200 may involve processor 1112 of device 1110 receiving a sequence of input bits. Process 1200 executes from 1210 to 1220.

[0061] At 1220, process 1200 may involve processor 1112 of device 1110 encoding the series of input bits. In encoding the input bits, process 1200 may involve processor 1112 performing certain operations represented by 1222 and 1224.

[0062] At 1222, process 1200 may involve processor 1112 of device 1110 encoding the input bits using the base coding rate via BCC encoder 210 of processor 1112. Process 1200 may be performed from 1222 to 1224.

[0063] At 1224, process 1200 may involve processor 1112 of device 1110 repeating, via repetition circuit 220 of processor 1112, the output of the BCC encoder to obtain an effective coding rate of the input bits that is lower than the base coding rate.

[0064] In some embodiments, the basic coding rate can be 1 / 2, 1 / 3, 1 / 4, 1 / 6, 1 / 8, 2 / 3, 3 / 4 or 5 / 6.

[0065] In some embodiments, when repeating the output of the BCC encoder, process 1200 may involve processor 1112 repeating a codeword generated by the BCC encoder multiple times, and the codeword includes a combination of output data of multiple output branches of the BCC encoder (e.g., option-1 as described above).

[0066] Alternatively, when repeating the output of the BCC encoder, the process 1200 may involve the processor 1112 generating multiple repetitions of first output data of a first output branch of the BCC encoder by repeating the corresponding output data of each output branch of the BCC encoder multiple times, and then multiple repetitions of second output data of a second output branch of the BCC encoder (e.g., as described in Option-2 above).

[0067] Alternatively, when repeating the output of the BCC encoder, the process 1200 may involve the processor 1112 repeating a combination of output data of multiple output branches of the BCC encoder multiple times so that in each repetition, the combination of output data includes first output data of a first output branch of the BCC encoder and second output data of a subsequent second output branch of the BCC encoder (e.g., as described in Option-3 above).

[0068] In some embodiments, the basic coding rate may be 1 / 2, 2 / 3, 3 / 4, or 5 / 6. In this case, in the repetition, the process 1200 may involve the processor 1112 repeating 1 time, 2 times, 3 times, 4 times, 6 times, 8 times, 12 times, or 16 times. Alternatively, the basic coding rate may be 1 / 2, 1 / 3, 1 / 4, 1 / 6, or 1 / 8. In this case, in the repetition, the process 1200 may involve the processor 1112 repeating 1 time, 2 times, 3 times, 4 times, 6 times, or 8 times.

[0069] In some embodiments, when encoding the string of input bits, the process 1200 may involve the processor 1112 encoding the string of input bits using QPSK and an MCS of 1 / 4 of the basic coding rate. Alternatively, when encoding the string of input bits, the process 1200 may involve the processor 1112 encoding the string of input bits using QPSK and an MCS of 1 / 8 of the basic coding rate.

[0070] In some embodiments, when encoding the string of input bits, the process 1200 may involve the processor 1112 performing additional operations. For example, the process 1200 may involve the processor 1112 interleaving the output of the repetition circuit through the interleaver 230 of the processor 1112. In addition, the process 1200 may involve the processor 1112 mapping the output of the interleaver through the QAM mapper 240 of the processor 1112.

[0071] Additional Notes

[0072] The subject matter described herein sometimes illustrates different components contained in or connected to different other components.It is to be understood that these depicted architectures are only examples, and many other architectures that realize the same function can actually be implemented.In a conceptual sense, any arrangement of components that realize the same function is effectively "associated" so that the desired function is realized.Therefore, regardless of the architecture or intermediate components, any two components that are combined to realize a specific function herein can be regarded as "associated" to each other so that the desired function is realized.Similarly, any two components so associated can also be regarded as "operationally connected" or "operationally coupled" to each other to realize the desired function, and any two components that can be so associated can also be regarded as "operationally couplable" to each other to realize the desired function.Specific examples of operation that can be coupled include but are not limited to physically matching and / or physically interacting components and / or wirelessly interacting and / or wirelessly interacting components and / or logically interacting and / or logically interactive components.

[0073] In addition, with respect to the extensive use of any plural and / or singular terms herein, those of ordinary skill in the art may convert from the plural to the singular and / or from the singular to the plural as needed for context and / or application. For the sake of clarity, various singular / plural reciprocities may be explicitly set forth herein.

[0074] In addition, one of ordinary skill in the art will understand that, in general, the terms used herein and especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be "open" terms, e.g., the term "comprising" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least", the term "including" should be interpreted as "including but not limited to", etc. One of ordinary skill in the art will also understand that if a specific number of an introduced claim recitation is intended, such intent will be explicitly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be interpreted as implying that a claim recitation, through the introduction of the indefinite article "a" or "an", will limit any particular claim that includes such introduced claim recitation to implementations that include only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a and / or an" should be interpreted as meaning "at least one" or "one or more"). In addition, even if a specific number of introduced claim recitations is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., an uncensored recitation of "two recitations" means at least two recitations or two or more recitations in the absence of other modifiers). Furthermore, in those cases where a convention similar to “at least one of A, B, and C, etc.” is used, such an interpretation is generally intended in the sense that one skilled in the art will understand this convention (e.g., “a system having at least one of A, B, and C” would include but is not limited to systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In those cases where a convention similar to “at least one of A, B, or C, etc.” is used, such an interpretation is generally intended in the sense that one skilled in the art will understand this convention (e.g., “a system having at least one of A, B, or C” would include but is not limited to systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). One skilled in the art will also understand that any transitional words and / or phrases that actually present two or more alternatives, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one, either, or both of these items. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0075] From the above, it will be appreciated that various implementations of the present disclosure have been described herein for illustrative purposes, and various modifications may be made without departing from the scope and spirit of the present disclosure. Therefore, the various implementations disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

Claims

1. A method comprising: The device's processor receives a stream of input bits; as well as The processor encodes the string of input bits by performing a plurality of operations, the plurality of operations comprising: A binary convolutional code (BCC) encoder of the processor encodes the input bits using a base code rate; The repetition circuit of the processor repeats the output of the BCC encoder to obtain an effective coding rate of the input bits that is lower than the basic coding rate.

2. The method according to claim 1, wherein the basic coding rate comprises 1 / 2, 1 / 3, 1 / 4, 1 / 6 or 1 / 8.

3. The method of claim 2, wherein repeating the output of the BCC encoder comprises: The codeword generated by the BCC encoder is repeated a plurality of times, and wherein the codeword comprises: a combination of output data from a plurality of output branches of the BCC encoder.

4. The method of claim 2, wherein repeating the output of the BCC encoder comprises: The corresponding output data of each output branch of the BCC encoder is repeated multiple times to generate multiple repetitions of first output data of a first output branch of the BCC encoder and subsequently multiple repetitions of second output data of a second output branch of the BCC encoder.

5. The method of claim 2, wherein repeating the output of the BCC encoder comprises: Combining output data of a plurality of output branches of the BCC encoder is repeated a plurality of times, such that in each repetition, the combination of output data comprises first output data of a first output branch of the BCC encoder followed by second output data of a second output branch of the BCC encoder.

6. The method of claim 1, wherein the basic coding rate comprises 1 / 2, 2 / 3, 3 / 4 or 5 / 6, and wherein the repetition comprises repetition 1 time, 2 times, 3 times, 4 times, 6 times, 8 times, 12 times or 16 times.

7. The method of claim 1, wherein the basic coding rate comprises 1 / 2, 1 / 3, 1 / 4, 1 / 6 or 1 / 8, and wherein the repetition comprises repetition 1 time, 2 times, 3 times, 4 times, 6 times or 8 times.

8. The method of claim 1, wherein encoding the sequence of input bits comprises: The string of input bits is encoded using Quadrature Phase Shift Keying (QPSK) and a Modulation and Coding Scheme (MCS) of 1 / 4 the basic coding rate.

9. The method of claim 1 , wherein encoding the sequence of input bits comprises: The string of input bits is encoded using Quadrature Phase Shift Keying (QPSK) and a Modulation and Coding Scheme (MCS) of 1 / 8 of the basic coding rate.

10. The method of claim 1, wherein the encoding of the sequence of input bits further comprises: An interleaver of the processor interleaves the output of the repetitive circuit; as well as A quadrature amplitude modulation (QAM) mapper of the processor maps the output of the interleaver.

11. A device comprising: a transceiver configured for wireless communication; as well as A processor coupled to the transceiver and configured to perform operations including: receiving a sequence of input bits; and This string of input bits is encoded by performing the following operations: A binary convolutional code (BCC) encoder of the processor encodes the input bits using a base code rate; as well as The repetition circuit of the processor repeats the output of the BCC encoder to obtain an effective coding rate of the input bits that is lower than the basic coding rate.

12. The apparatus according to claim 11, wherein the basic coding rate comprises 1 / 2, 1 / 3, 1 / 4, 1 / 6 or 1 / 8.

13. The apparatus of claim 12, wherein repeating the output of the BCC encoder comprises: The codeword generated by the BCC encoder is repeated a plurality of times, and wherein the codeword comprises: a combination of output data from a plurality of output branches of the BCC encoder.

14. The apparatus of claim 12, wherein repeating the output of the BCC encoder comprises: The corresponding output data of each output branch of the BCC encoder is repeated multiple times to generate multiple repetitions of first output data of a first output branch of the BCC encoder and subsequently multiple repetitions of second output data of a second output branch of the BCC encoder.

15. The apparatus of claim 12, wherein repeating the output of the BCC encoder comprises: Combining output data of a plurality of output branches of the BCC encoder is repeated a plurality of times, such that in each repetition, the combination of output data comprises first output data of a first output branch of the BCC encoder followed by second output data of a second output branch of the BCC encoder.

16. The apparatus of claim 11, wherein the basic coding rate comprises 1 / 2, 2 / 3, 3 / 4, or 5 / 6, and wherein the repetition comprises repetition 1 time, 2 times, 3 times, 4 times, 6 times, 8 times, 12 times, or 16 times.

17. The apparatus of claim 11, wherein the basic coding rate comprises 1 / 2, 1 / 3, 1 / 4, 1 / 6, or 1 / 8, and wherein the repetition comprises repetition 1 time, 2 times, 3 times, 4 times, 6 times, or 8 times.

18. The apparatus of claim 11, wherein the encoding of the sequence of input bits comprises: The string of input bits is encoded using Quadrature Phase Shift Keying (QPSK) and a Modulation and Coding Scheme (MCS) of 1 / 4 the basic coding rate.

19. The apparatus of claim 11, wherein the encoding of the sequence of input bits comprises: The string of input bits is encoded using Quadrature Phase Shift Keying (QPSK) and a Modulation and Coding Scheme (MCS) of 1 / 8 of the basic coding rate.

20. The apparatus of claim 11, wherein: In encoding the string of input bits, the processor is further configured to perform operations including: An interleaver of the processor interleaves the output of the repetition circuit; and A quadrature amplitude modulation (QAM) mapper of the processor maps the output of the interleaver.

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