Buried metal signal rail for memory array

Abstract

An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail disposed in a buried layer between the memory cell array and the plurality of shunt transistors, the buried layer being embedded in the substrate underneath the transistors. The device also includes a single-layer via in the same layer as the transistor and electrically connecting the memory cell transistor to the shunt transistor through a buried metal signal rail.

Description

Technical Field

[0001] The present invention relates to the electrical, electronic and computer fields and, more particularly, to the fabrication of integrated circuit memory devices. Background Art

[0002] As is well known, integrated circuit memory devices incorporate an array of memory cells addressed by word lines and bit lines (metal traces and vias) through which voltage / current can be applied to write and read individual cells. Typically, the bit lines connect from the memory cell transistors (in the front-end process layers) up to the back-end process layers through multiple levels of metal vias, and then back down through more levels of via connections to sense amplifiers also formed in the front-end process layers. In the operation of conventional IC memory devices, due in part to the layout of the bit lines, significant I 2 R loss and waiting time. Summary of the invention

[0003] The principles of the present invention provide techniques for buried metal signal track(s) for a memory array.

[0004] In one aspect, an example integrated circuit memory device includes a substrate and an array of memory cells disposed on the substrate. Each memory cell includes at least one memory cell transistor disposed in a first layer of the device adjacent to a top side of the substrate. The device also includes a plurality of shunt transistors, each shunt transistor disposed in the first layer. The device also includes a buried metal signal rail disposed in a buried layer of the device between the memory cell array and the plurality of shunt transistors, the buried layer being embedded in the substrate below the first layer. The device also includes a first single layer of vias disposed in the first layer and electrically connecting one of the memory cell transistors to the buried metal signal rail; and a second single layer of vias disposed in the first layer and electrically connecting the buried metal signal rail to one of the plurality of shunt transistors.

[0005] According to another aspect, an exemplary method for manufacturing an integrated circuit memory device is provided. The method includes: forming a memory cell transistor and a shunt transistor in a first layer of the device, wherein the first layer is adjacent to the substrate on a top side of the substrate. The method also includes forming a buried metal signal rail in a buried layer of the device embedded in the substrate between the memory cell transistor and the shunt transistor; and the method also includes forming a bit line that connects the memory cell transistor to the shunt transistor via the buried metal signal rail, such that the bit line is completely contained within the first layer and the buried layer.

[0006] According to another aspect, in an integrated circuit memory device, a method includes transmitting a signal from a memory cell transistor disposed in a first layer to a buried metal signal rail disposed in a buried layer embedded in a substrate of the device through a first single layer via disposed in a first layer of the device, wherein the first layer is adjacent to a top side of the substrate of the device.

[0007] In view of the above, the technology of the present invention can provide substantially beneficial technical effects. For example, one or more embodiments provide one or more of the following:

[0008] Significant resistance reduction (-50-60%) of both via / metal stack and lines results in improvements in READ and WRITE operations, which enables larger memory book sizes.

[0009] Eliminating two of the four vias in the memory unit cell saves ~0.56μm 2 The unit cell footprint of 100nm is 100nm, which enables significant shrinkage of the cell.

[0010] This enables the upper metal stack line layers to be used for purposes other than memory access.

[0011] Heterogeneous Integration of Backside Power Networks. The backside power network does not necessarily require heterogeneous integration, although it is expected that backside power will provide very attractive benefits for heterogeneously integrated systems.

[0012] Some embodiments may not have these potential advantages, and these potential advantages are not required for all embodiments.These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 schematically depicts an integrated circuit memory device according to the prior art.

[0014] FIG. 2 schematically shows a memory cell and a shunt transistor according to the prior art, which are connected by a bit line including multi-layer vias.

[0015] Figure 3 An integrated circuit memory device incorporating buried metal wiring according to an example embodiment is depicted in schematic form.

[0016] Figure 4 A memory cell and a shunt transistor connected by a buried metal signal rail are schematically shown according to an exemplary embodiment.

[0017] Figure 5A and Figure 5B A schematic diagram of a method for manufacturing a Figure 3and Figure 4 The steps of the method of the integrated circuit memory device shown in FIG.

[0018] Figure 6 Advantages of the exemplary embodiments compared to the prior art are shown in table form. DETAILED DESCRIPTION

[0019] FIG. 1 depicts in schematic form an integrated circuit memory device 100 according to the prior art. The device 100 includes memory arrays 102, 104 and a sense amplifier array 106. Each of the memory arrays 102, 104 includes a plurality of memory cells 108, and the sense amplifier array 106 includes a plurality of sense amplifiers 110. The columns of the memory arrays 102, 104 are electrically connected to the sense amplifier array 106 through bit lines 112. The word lines 114 are electrically connected to the rows of the memory arrays 102, 104. As will be understood by a person of ordinary skill, each memory cell 108 can be addressed by a combination of its word line and bit line. The column driver provides a source voltage VSS or a drain voltage VDD to the memory cell. The signal FEED_BLH is provided to the bit line 112 through the sense amplifier array 106, and the bit line 112 provides the signal to a sub-portion or segment of the entire array 102, 104.

[0020] FIG. 2 schematically illustrates a portion of a memory cell 108 and a sense amplifier 110 according to the prior art, which are connected by a bit line 112 including multi-layer vias 202, 204. Those skilled in the art will be familiar with the specific metal layers that make up the multi-layer vias, such as M1, M2, M3, M4, M5, M6, M7, M8, which will not be described in detail. In one or more embodiments, the memory cell 108 and the portion of the sense amplifier 110 each include a FinFET (Fin Field Effect Transistor) 206, and the bit line 112 connects these transistors. In one or more embodiments, the memory cell 108 includes a memory module 208, such as a phase change memory, a magnetoresistive random access memory, or a resistive random access memory.

[0021] In one or more embodiments, memory 208 is a phase change memory module including a bottom electrode 220 , a heater element 222 , an optional metal level 224 , and a phase change material 226 (eg, a chalcogenide material), with a top electrode indicated as M4 .

[0022] The choice of memory module is not limited to resistive memory; embodiments of the present invention, particularly structures for communicating between memory cells 108 and sense amplifiers 110 of sense amplifiers, are equally applicable to static random access memory (SRAM) or dynamic random access memory (DRAM). In one or more embodiments, memory cells 108 (similar to multi-layer vias 202, 204) include multiple layers of intermediate metal 210.

[0023] Figure 3 An integrated circuit memory device 300 incorporating buried metal wiring 304 is schematically depicted according to an example embodiment. The device 300 includes memory arrays 102, 104 and sense amplifier arrays 106. Each of the memory arrays 102, 104 includes a plurality of memory cells 108, and the sense amplifier array 106 includes a plurality of sense amplifiers 110. The columns of the memory arrays 102, 104 are electrically connected to the sense amplifier arrays 106 through bit lines 302, which are implemented in the buried metal signal rails 304. The word lines 114 are electrically connected to the rows of the memory arrays 102, 104. As will be appreciated by one of ordinary skill, each memory cell 108 can be addressed by a combination of its word line and bit line.

[0024] The difference between a signal rail and a power rail is that a signal rail is connected to a signal source that provides a time-varying signal, whereas a power rail is connected to a power supply or ground. A signal path connects the source of one device to the gate of another device, whereas a power rail is connected to a global power distribution network (or "grid"), which in turn connects to many devices. Note that a power rail can carry DC and can also have time-dependent currents; for example, if a portion of a logic block is "power-gated," in which case power is temporarily stopped from that section of the chip. Therefore, a power rail can often carry both DC and time-dependent currents.

[0025] Figure 4Schematically illustrated are portions of a memory cell 108 and a sense amplifier 110 according to an exemplary embodiment, which are connected by a bit line 302 including a buried metal signal rail 304 and a single layer of vias 402, 404. In one or more embodiments, the vias 402 and 404 are formed from the top side of the chip and typically have dimensions in the range of, for example, 5 nm-25 nm. They can be formed of metals such as Co, Ru, W, Mo, or any other metal that can withstand the high thermal budget (~1000K) of device processing. The height of these vias can be in the range of, for example, 20 nm-100 nm. In one or more embodiments, the memory cell 108 and a portion of the sense amplifier 110 each include a FinFET (fin field effect transistor) 206. In one or more embodiments, the memory cell 108 includes a memory module 208, such as a phase change memory, a magnetoresistive random access memory, or a resistive random access memory. The choice of memory module is not limited to resistive memory. Embodiments of the present invention, particularly relating to a structure for communication between the memory cell 108 and the sense amplifier 110, are also applicable to other types of memory cells, such as static random access memory (SRAM) or dynamic random access memory (DRAM). Figure 4 The illustrated structure also includes a buried metal power rail 410 that is electrically connected to one of the transistors 206 in the sense amplifier 110. In one or more embodiments, the buried metal power rail 410 is adjacent to the buried metal signal rail 304.

[0026] Figure 5A and Figure 5B Schematic diagram for manufacturing Figure 3 and Figure 4 . At 502, a starting substrate, such as silicon, is obtained. At 504, the fins 206 are patterned and an interlayer dielectric (e.g., an oxide such as SiO2, not separately numbered) is deposited around them in a manner known to those of ordinary skill. At 506, buried metal signal rails 304 and buried metal power rails 410 are formed. Each buried rail has a liner and also has a conductive filler (not separately numbered), which is familiar to those of ordinary skill in the art.

[0027] Semiconductor device manufacturing includes various steps of the device patterning process. For example, the manufacture of semiconductor chips may start with device patterns generated by, for example, multiple CAD (computer-aided design) processes, and then work to replicate these device patterns in a substrate. The replication process may include the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing processes.

[0028] As an exemplary subtractive process, in a photolithography process, a layer of photoresist material may first be applied on top of a substrate and then selectively exposed according to a predetermined device pattern or patterns. Portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photoresist may then be developed in a developer solution to remove un-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer to produce a photoresist pattern or photomask. Subsequently, the photoresist pattern or photomask may be copied or transferred to a substrate below the photoresist pattern.

[0029] Various structures described herein, such as source / drain structures, can be grown epitaxially. As used herein, "epitaxial" or "epitaxial growth" refers to a process of forming a single crystal or large-grained polycrystalline material layer on an existing material with similar crystalline properties. One feature of epitaxy is that the process causes the crystal structure of an existing substrate or seed layer (including any defects therein) to be replicated in the epitaxially grown material. Epitaxial growth may include heteroepitaxial (i.e., growing a material having a composition different from that of its underlying layer) or homoepitaxial (i.e., growing a material comprising the same composition as that of its underlying layer). Heteroepitaxial growth introduces strain in the epitaxially grown material because its crystal structure may be deformed to match the crystal structure of the underlying layer. In certain applications, such strain may be desirable. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, the epitaxial semiconductor material may have the same crystalline properties as the deposition surface on which it may be formed. For example, epitaxial semiconductor material deposited on a {100} crystal surface may adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process may selectively form on semiconductor surfaces and may not deposit material on dielectric surfaces (eg, silicon dioxide or silicon nitride surfaces).

[0030] Many different precursors can be used for epitaxial deposition of in-situ doped semiconductor materials. In some embodiments, the gas source for depositing the epitaxially formed in-situ doped semiconductor material can include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane, and combinations thereof. In other examples, when the in-situ doped semiconductor material contains germanium, the germanium gas source can be selected from germanium, digermane, halogenated germanes, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Examples of other epitaxial growth processes that can be used for growing semiconductor layers described herein include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE).

[0031] "In situ" refers to the introduction of dopants that determine the conductivity type of the doped layer during a process step (e.g., epitaxial deposition) that forms the doped layer. The terms "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the grown semiconductor material (crystalline blanket) has substantially the same crystalline properties as the semiconductor material (seed material) of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move back and forth on the surface so that the deposited atoms orient themselves to the crystalline arrangement of the atoms of the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed.

[0032] At 508, the front-end and middle-end processes are completed. The front-end process forms transistors, diodes, or other active elements, while the middle-end process forms conductive traces and vias that interconnect the active elements. The elements added in step 508 include transistor devices (including source, drain, channel, gate, etc.) and "middle-end" electrical connections between transistors and interconnects in the BEOL. These connections include gate connections and source / drain connections. These electrical connections can be embedded in oxide materials (such as SiO2, etc.) and can include a dielectric capping layer (such as SiN) on top of them. At 510, the front-side process of the back-end process layer (BEOL) is completed. Step 510 includes forming all BEOL metal layers. To form a single metal layer, a low-k dielectric is deposited and then etched to form openings. These openings are filled with metal (such as Cu) and then chemically mechanically polished (CMP) to remove excess metal. Then, all parts are covered with dielectric capping materials (such as SiN). This process is repeated for each metal layer subsequently formed on top of the previous metal layer. The chip may have, for example, any one of 10-20 total metal levels, with the size increasing from the bottom to the top metal level. At 512, the front side of the wafer is coated in preparation for backside processing. In one or more embodiments, the wafer may be coated with a thick oxide or nitride based material to protect the front side of the wafer during subsequent processing. At 514, the wafer is flipped.

[0033] At 516, the wafer is thinned. Those skilled in the art employ various techniques to remove material at various stages in the formation of semiconductor structures. As used herein, these processes are generally referred to as "etching." For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, which are all known techniques for removing selective materials when forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. Those skilled in the art readily understand the techniques and applications of etching, and therefore, a more detailed description of these processes is not provided herein.

[0034] Another mode of material removal is chemical mechanical planarization (CMP), which may be used to thin the wafer in step 516 in one or more embodiments.

[0035] At 518, nano-through silicon vias (TSVs) 519 are formed to the buried metal power rails 410. An etch and fill process (e.g., "Bosch etch") may be used to create the openings, which are then filled with metal (e.g., copper) to form the nano-TSVs. At 520, a backside metal process is completed that connects the buried metal power rails 410 with the backside power rails 521. For example, step 520 may be performed in the same manner as step 510, except now on the backside of the wafer instead of the front side. Several layers of interconnect wiring may be formed using the same steps as described above (dielectric deposition, etching, metal fill, CMP, dielectric cap).

[0036] The steps shown in FIG. 5 are not necessarily the only steps of method 500 , which may include additional details and intermediate steps that will be understood by one of ordinary skill in the art in light of this disclosure.

[0037] Figure 6 The advantages of the exemplary embodiments compared to the prior art are shown in table form. It is noteworthy that selected embodiments of the structure of the present invention reduce the bit line resistance by 53%-62% compared to the prior art. These percentages of improvement may not be present in all embodiments.

[0038] In view of the discussion thus far, it will be appreciated that, in general, an exemplary integrated circuit memory device includes a substrate ( Figure 4 ” in “Si”); an array of memory cells (e.g., 108) disposed on a substrate, wherein each memory cell includes at least one memory cell transistor 206 disposed in a first layer of the device adjacent to the top side of the substrate. The first layer is typically formed by a front end of line (FEOL) process, e.g., Figure 5A Step 504 and step 508. The device also includes a plurality of shunt transistors (e.g., 110), each of which is disposed in the first layer. The device also includes a buried metal signal rail 304, which is disposed in a buried layer of the device between the memory cell array and the plurality of shunt transistors, the buried layer being embedded in the substrate below the first layer. The device also includes a first single-layer via 402, which is disposed in the first layer and electrically connects one of the memory cell transistors to the buried metal signal rail; and a second single-layer via 404, which is disposed in the first layer and electrically connects the buried metal signal rail to one of the plurality of shunt transistors.

[0039] In one or more embodiments, at least one of the memory cells comprises a resistive memory element disposed in a second layer of the device, the second layer being adjacent to a top side of the first layer, i.e., the top side of the first layer opposite to the substrate. In one or more embodiments, the second layer may be formed as part of a middle of line (MOL) process, i.e., Figure 5A Step 508.

[0040] In one or more embodiments, at least one memory cell transistor is a fin field effect transistor (FinFET). In one or more embodiments, at least one shunt transistor is a fin field effect transistor (FinFET).

[0041] In one or more embodiments, the apparatus further includes a second memory cell array (e.g., Figure 3 102 and 104 and a second buried metal signal track (e.g., Figure 3 ), and a plurality of shunt transistors, a buried metal signal rail, and a second buried metal signal rail form a bit line bus interconnecting the memory cell array with a second memory cell array.

[0042] In one or more embodiments, the apparatus further includes a buried metal power rail 410 adjacent to the buried metal signal rail in the buried layer and adjacent to one of the plurality of shunt transistors in the first layer.

[0043] In one or more embodiments, the device further includes a backside via 521 electrically connected to the buried metal power rail and extending from the buried layer to a bottom side of the substrate, wherein the bottom side of the substrate is opposite to the first layer.

[0044] According to another aspect, an exemplary method 500 for manufacturing an integrated circuit memory device is provided. The method includes: forming a memory cell transistor and a shunt transistor in a first layer of the device, wherein the first layer is adjacent to the substrate on a top side of the substrate, at 504 and 508. The method also includes, at 506, forming a buried metal signal track in a buried layer of the device embedded in the substrate between the memory cell transistor and the shunt transistor; and the method also includes, at 508, forming a bit line connecting the memory cell transistor to the shunt transistor via the buried metal signal track, such that the bit line is completely contained within the first layer and the buried layer.

[0045] In one or more embodiments, forming the bit line includes forming a first single layer of vias electrically connecting the memory cell transistor to the buried metal signal rail; and forming a second single layer of vias from the buried metal signal rail to the shunt transistor.

[0046] Some embodiments of the method further include, at 506 , forming a buried metal power rail adjacent to the buried metal signal rail and adjacent to the shunt transistor.

[0047] One or more embodiments further include, at 518 , forming a backside via electrically connected to the buried metal power rail.

[0048] In one or more embodiments, forming at least one of the memory cell transistors includes forming a FinFET. In one or more embodiments, forming at least one shunt transistor includes forming a FinFET.

[0049] According to another aspect, in an integrated circuit memory device, a method includes transmitting a signal from a buried metal signal rail disposed in a buried layer embedded in a substrate to a memory cell transistor disposed in the first layer through a first single-layer via disposed in a first layer of the device, wherein the first layer is adjacent to a top side of the substrate of the device. In one or more embodiments, the method further includes transmitting the signal from the buried metal signal rail to a shunt transistor of a sense amplifier through a second single-layer via, wherein the shunt transistor is also disposed in the first layer.

[0050] Although the entire manufacturing method and the structure formed thereby are novel, certain individual processing steps required to implement the method can utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. These techniques and tools are already familiar to those of ordinary skill in the relevant art given the teachings herein. In addition, one or more processing steps and tools for manufacturing semiconductor devices are also described in many readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Basic Principles, Practice and Modeling 1st Edition, Prentice Hall, 2001 and P. H. Holloway et al., Compound Semiconductor Handbook: Growth, Processing, Programming and Devices, Cambridge University Press, 2008, both of which are incorporated herein by reference. It is emphasized that although some individual processing steps are set forth herein, these steps are merely illustrative, and those skilled in the art may be familiar with several equally suitable alternatives that will be applicable.

[0051] It should be understood that the various layers and / or regions shown in the drawings may not be drawn to scale. In addition, for ease of explanation, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This does not mean that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0052] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An integrated circuit memory device, comprising: substrate; an array of memory cells disposed on the substrate, wherein each memory cell comprises at least one memory cell transistor disposed in a first layer of the device adjacent to a top side of the substrate; a plurality of shunt transistors, each shunt transistor being disposed in the first layer; a buried metal signal rail disposed in a buried layer of the device between the memory cell array and the plurality of shunt transistors, the buried layer being embedded in the substrate below the first layer; a first single layer via disposed in the first layer and electrically connecting one of the memory cell transistors to a buried metal signal rail; as well as A second single layer via is disposed in the first layer and electrically connects the buried metal signal rail to one of the plurality of shunt transistors.

2. The device of claim 1, wherein at least one of the memory cells comprises a resistive memory element disposed in a second layer of the device adjacent to a top side of the first layer, wherein the top side of the first layer is opposite the substrate. 3 . The device of claim 1 , wherein at least one of the memory cell transistors is a fin field effect transistor (FinFET). 4 . The apparatus of claim 1 , wherein at least one of the shunt transistors is a fin field effect transistor (FinFET).

5. The apparatus of claim 1 further comprising a second memory cell array and a second buried metal signal rail, wherein the plurality of shunt transistors, the buried metal signal rail, and the second buried metal signal rail comprise a bit line bus interconnecting the memory cell array with the second memory cell array. 6 . The apparatus of claim 1 , further comprising a buried metal power rail adjacent to the buried metal signal rail in the buried layer and adjacent to a shunt transistor of the plurality of shunt transistors in the first layer.

7. The apparatus of claim 6, further comprising a backside via electrically connected to the buried metal power rail and extending from the buried layer to a bottom side of the substrate, wherein the bottom side of the substrate is opposite the first layer.

8. A method for manufacturing an integrated circuit memory device, the method comprising: forming a memory cell transistor and a shunt transistor in a first layer of the device, wherein the first layer is adjacent to the substrate on a top side of the substrate; forming a buried metal signal rail in a buried layer of the device, the buried metal signal rail being embedded in the substrate between the memory cell transistor and the shunt transistor; as well as A bit line is formed that connects the memory cell transistor to the shunt transistor via the buried metal signal rail, wherein the bit line is completely contained within the first layer and the buried layer.

9. The method of claim 8, wherein forming the bit line comprises: forming a first single layer via electrically connecting the memory cell transistor to the buried metal signal rail; as well as A second single layer via is formed from the buried metal signal rail to the shunt transistor.

10. The method according to claim 8, further comprising: A buried metal power rail is formed adjacent to the buried metal signal rail and adjacent to the shunt transistor.

11. The method according to claim 10, further comprising: Backside vias are formed that are electrically connected to the buried metal power rail.

12. The method of claim 8, wherein forming at least one of the memory cell transistors comprises forming a FinFET.

13. The method of claim 8, wherein forming at least one of the shunt transistors comprises forming a FinFET.

14. A method comprising, in an integrated circuit memory device: A signal is transmitted from a memory cell transistor disposed in a first layer of the device to a buried metal signal rail through a first single layer via disposed in the first layer, wherein the first layer is adjacent to a top side of a substrate of the device, and the buried metal signal rail is disposed in a buried layer embedded in the substrate of the device.

15. The method according to claim 14, further comprising: The signal is transmitted from the buried metal signal rail to a shunt transistor of a sense amplifier through a second single-layer via, wherein the shunt transistor is also disposed in the first layer.

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