Reading circuit, reading method and infrared detector

Abstract

The invention provides a readout circuit, a readout method and an infrared detector, and relates to the technical field of infrared imaging, the readout circuit reduces noise by additionally arranging reference pixel blocks and changing the number of the reference pixel blocks, and reduces the influence of cross grains on an image. The reading circuit comprises a plurality of detection pixel blocks and at least one reference pixel block which are arranged in an array; the detection pixel block comprises a plurality of detection pixels arranged in an array; the number of the reference pixel blocks is smaller than the line number of the plurality of detection pixel blocks; one reference pixel block is correspondingly connected with at least one row of detection pixel blocks; the reference pixel block comprises a plurality of reference pixels arranged in an array; the reference pixel block is used for connecting the multiple rows of detection pixel blocks in sequence; the detection pixel block is used for outputting a detection signal under the condition that the detection pixel block is connected with the reference pixel block.

Description

Technical Field

[0001] The present application relates to the field of infrared imaging technology, and in particular to a readout circuit, a readout method, and an infrared detector. Background Art

[0002] At present, infrared imaging technology has important applications in many fields. As the core of infrared imaging technology, the infrared focal plane array includes two parts: infrared detection and readout circuit. Among them, the microbolometer focal plane array (Focal Plane Array, FPA) has high sensitivity and is the most widely used infrared focal plane array. It detects the size of the infrared radiation signal by measuring the change of its resistance value.

[0003] In the prior art, the readout circuit does not have a suitable bias circuit, so the Joule heat effect generated by the microbolometer focal plane array cannot be offset, and the asymmetric power supply noise and circuit noise will also have a great impact on the performance. Summary of the invention

[0004] The invention provides a readout circuit, a readout method and an infrared detector. The readout circuit reduces noise and reduces the influence of horizontal stripes on an image by changing the number and arrangement of reference pixel blocks.

[0005] In a first aspect, the present application provides a readout circuit. The readout circuit comprises: a plurality of detection pixel blocks arranged in an array and at least one reference pixel block; the detection pixel block comprises a plurality of detection pixels arranged in an array; the number of the reference pixel blocks is less than the number of rows of the plurality of detection pixel blocks; one reference pixel block is correspondingly connected to at least one row of the detection pixel blocks; the reference pixel block comprises a plurality of reference pixels arranged in an array; the reference pixel block is used to sequentially connect to a plurality of rows of the detection pixel blocks; the detection pixel block is used to output a detection signal when connected to the reference pixel block.

[0006] Based on the above scheme, the embodiment of the present application provides a readout circuit, which reduces noise by adding reference pixel blocks and changing the number. When a row of detection pixel blocks is working, a reference pixel block is connected so that the output current does not change, and the current is transmitted to a signal processing subcircuit, and a signal processing subcircuit converts the current into a voltage output; after the row of detection pixel blocks completes the work, it is disconnected from the reference pixel block, and then when another row of detection pixel blocks starts working, a reference pixel block is connected so that the output current does not change, and the current is transmitted to another signal processing subcircuit, and another signal processing subcircuit converts the current into a voltage output; then at least one reference pixel block is connected to a row of detection pixel blocks to work until all detection pixel blocks have completed their work and stop. In this way, noise can be reduced and better matching can be achieved by only using at least one reference pixel block, thereby reducing the impact of horizontal stripes on the image.

[0007] In some embodiments, the readout circuit further includes: a first control subcircuit connected to the at least one reference pixel block; the first control subcircuit is used to turn on the at least one reference pixel block.

[0008] In some embodiments, the first control subcircuit includes: a plurality of first switches; one of the first switches is correspondingly connected to one of the reference pixels.

[0009] In some embodiments, the readout circuit also includes: a second control subcircuit connected to the multiple detection pixel blocks; the second control subcircuit is used to make at least one row of the detection pixel blocks turned on at the same time when one of the reference pixel blocks is turned on, and when at least one row of the detection pixel blocks is turned on, make each detection pixel block in the at least one row of detection pixel blocks turned on at the same time and output a detection signal.

[0010] In some embodiments, the second control subcircuit includes: a plurality of second switches; and one second switch is correspondingly connected to one detection pixel.

[0011] In some embodiments, the detection pixel includes: a first resistor; the reference pixel includes: a second resistor; and the resistance values ​​of the first resistor and the second resistor decrease as the temperature increases.

[0012] In some embodiments, the readout circuit also includes: a bridge unit; the first end of the bridge unit is electrically connected to the power supply end, the second end of the bridge unit is electrically connected to the power supply end, the third end of the bridge unit is electrically connected to the first end of the reference pixel block, and the fourth end of the bridge unit is electrically connected to the first end of the detection pixel block.

[0013] In some embodiments, the multiple detection pixel blocks are arranged into i rows of detection pixel blocks; the at least one reference pixel block includes: a reference pixel block; the reference pixel block includes m×n reference pixels, the detection pixel block includes m×n detection pixels, each reference pixel in the reference pixel block corresponds to each detection pixel in the detection pixel block one by one; the reference pixel block is correspondingly connected to the i rows of detection pixel blocks; each reference pixel in the reference pixel block is turned on in turn, and when the reference pixel is turned on, the corresponding detection pixels of each detection pixel block in the i rows of detection pixel blocks are turned on at the same time.

[0014] In some embodiments, the multiple detection pixel blocks are arranged into i rows of detection pixel blocks; the at least one reference pixel block includes: h reference pixel blocks; the 2≤h≤i-1; the reference pixel block includes m×n reference pixels, the detection pixel block includes m×n detection pixels, and each reference pixel in the reference pixel block corresponds to each detection pixel in the detection pixel block one by one; one of the reference pixel blocks is correspondingly connected to the k rows of detection pixel blocks; 1≤k<i-1; each reference pixel in one of the reference pixel blocks is turned on in turn, and when the reference pixel is turned on, the corresponding detection pixels of each detection pixel block in the k rows of detection pixel blocks are turned on at the same time.

[0015] In some embodiments, the multiple detection pixel blocks are arranged into i rows of detection pixel blocks; the at least one reference pixel block includes: i reference pixel blocks; the reference pixel block includes m×n reference pixels, the detection pixel block includes m×n detection pixels, each reference pixel in the reference pixel block corresponds to each detection pixel in the detection pixel block one by one; the i reference pixel blocks are correspondingly connected to the i rows of detection pixel blocks; each reference pixel in one of the reference pixel blocks is turned on in turn, and when the reference pixel is turned on, the corresponding detection pixels of each detection pixel block in the row of detection pixel blocks are turned on at the same time.

[0016] In some embodiments, the readout circuit also includes: a bridge unit; when the readout circuit also includes a first control subcircuit; the first end of the bridge unit is electrically connected to the power supply end, the second end of the bridge unit is electrically connected to the power supply end, the third end of the bridge unit is electrically connected to one end of the first control subcircuit, the other end of the first control subcircuit is electrically connected to the first end of the reference pixel block, the fourth end of the bridge unit is electrically connected to one end of the second control subcircuit, and the other end of the second control subcircuit is electrically connected to the first end of the detection pixel block.

[0017] In some embodiments, the bridge unit includes: a first sub-unit and multiple second sub-units, and the multiple second sub-units are connected in parallel; the first end of the first sub-unit is electrically connected to the first end of the bridge unit, and the second end of the first sub-unit is electrically connected to the third end of the bridge unit; the first end of the second sub-unit is electrically connected to the second end of the bridge unit, and the second end of the first sub-unit is electrically connected to the fourth end of the bridge unit; the third end of the second sub-unit is electrically connected to the third end of the first sub-unit; the fourth end of the second sub-unit is electrically connected to the fourth end of the first sub-unit; wherein, the second sub-unit corresponds to a row of detection pixel blocks.

[0018] In some embodiments, the first subunit includes: a third resistor, a first transistor, and a second transistor; the first end of the third resistor is electrically connected to the first end of the first subunit, and the second end of the third resistor is electrically connected to the first end of the first transistor; the control end of the first transistor is electrically connected to the third end of the first subunit, and the second end of the first transistor is electrically connected to the first end of the second transistor; the control end of the second transistor is electrically connected to the fourth end of the first subunit, the control end of the second transistor is also electrically connected to the first end of the second transistor, and the second end of the second transistor is electrically connected to the second end of the first subunit.

[0019] In some embodiments, the second subunit includes: a fourth resistor, a third transistor and a fourth transistor; the first end of the fourth resistor is electrically connected to the first end of the second subunit, and the second end of the fourth resistor is electrically connected to the first end of the third transistor; the control end of the third transistor is electrically connected to the third end of the second subunit, and the second end of the third transistor is electrically connected to the first end of the fourth transistor; the control end of the fourth transistor is electrically connected to the fourth end of the second subunit, and the second end of the fourth transistor is electrically connected to the second end of the second subunit.

[0020] In some embodiments, the readout circuit further includes: a plurality of signal processing sub-circuits; one of the signal processing sub-circuits is correspondingly connected to one of the detection pixel blocks; and an input end of the signal processing sub-circuit is electrically connected to an output end of the bridge unit.

[0021] When one of the reference pixel blocks is connected to one of the detection pixel blocks, one of the signal processing sub-circuits is configured to integrate one of the detection pixel blocks, and after one of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from the one of the detection pixel blocks; when one of the reference pixel blocks is connected to another of the detection pixel blocks, another of the signal processing sub-circuits is configured to integrate another of the detection pixel blocks, and after the other of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from the other of the detection pixel blocks.

[0022] In a second aspect, the present application provides a readout method of a readout circuit, which is applied to the above-mentioned readout circuit.

[0023] The reference pixel block is sequentially connected to a plurality of rows of the detection pixel blocks; and the detection pixel block outputs a detection signal when connected to the reference pixel block.

[0024] The beneficial effects that can be achieved by a readout method provided in some embodiments of the present application are the same as the beneficial effects that can be achieved by a readout circuit provided by the above technical solution, and will not be repeated here.

[0025] In some embodiments, when the readout circuit further includes: a first control subcircuit and a second control subcircuit; the first control subcircuit turns on the at least one reference pixel block; when the second control subcircuit turns on a plurality of rows of detection pixel blocks in sequence when one of the reference pixel blocks is turned on, and when each row of detection pixel blocks is turned on, each detection pixel block in the row of detection pixel blocks is turned on at the same time, and the row of detection pixel blocks outputs a detection signal.

[0026] In some embodiments, when the first control subcircuit includes a plurality of first switches and the second control subcircuit includes a plurality of second switches; the first switches turn on the plurality of reference pixels;

[0027] When one of the reference pixels is turned on, the second switch sequentially turns on one detection pixel of each detection pixel block in a column of detection pixel blocks, so that multiple detection pixels of each detection pixel block in the column of detection pixel blocks output detection signals.

[0028] In some embodiments, when the readout circuit further includes a plurality of signal processing sub-circuits; when one of the reference pixel blocks is connected to one of the detection pixel blocks, one of the signal processing sub-circuits integrates one of the detection pixel blocks, and after one of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from one of the detection pixel blocks; when one of the reference pixel blocks is connected to another of the detection pixel blocks, another of the signal processing sub-circuits integrates another of the detection pixel blocks, and after another of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from another of the detection pixel blocks.

[0029] In a third aspect, the present application provides an infrared detector, comprising: the above-mentioned readout circuit.

[0030] The beneficial effects that can be achieved by an infrared detector provided by some embodiments of the present application are the same as the beneficial effects that can be achieved by a readout circuit provided by the above technical solution, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the embodiments of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0032] Figure 1 is a schematic diagram of an existing readout circuit;

[0033] Figure 2 A schematic diagram of a readout circuit provided for some embodiments of the present disclosure;

[0034] Figure 3 A schematic diagram of another readout circuit provided for some embodiments of the present disclosure;

[0035] Figure 4 A schematic diagram of another readout circuit provided for some embodiments of the present disclosure;

[0036] Figure 5 A schematic diagram of another readout circuit provided for some embodiments of the present disclosure;

[0037] Figure 6 A schematic diagram of another readout circuit provided for some embodiments of the present disclosure;

[0038] Figure 7 A circuit diagram of a readout circuit provided for some embodiments of the present disclosure;

[0039] Figure 8 A switching timing diagram of a readout circuit provided for some embodiments of the present disclosure;

[0040] Fig. 9 A schematic diagram of an infrared detector provided for some embodiments of the present disclosure.

[0041] Reference numerals

[0042] 1. Detection pixel block; 2. Reference pixel block; 11. First control subcircuit; 12. Second control subcircuit; 20. Bridge unit; 21. First subunit; 22. Second subunit; 3. Signal processing subcircuit; 100. Readout circuit; Pt, detection pixel; Pc, reference pixel; Srs, first switch; Srsm, second switch; Rs, first resistor; Rsm, second resistor; Rdm, third resistor; Rd, fourth resistor; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0045] At present, infrared imaging technology has important applications in many fields. As the core of infrared imaging technology, the infrared focal plane array includes two parts: infrared detection and readout circuit. Among them, the microbolometer focal plane array (Focal Plane Array, FPA) has high sensitivity and is the most widely used infrared focal plane array. It detects the size of the infrared radiation signal by measuring the change of its resistance value.

[0046] Among them, microbolometers generally use cantilever beam microbridge structures made by micromachining technology. A layer of thermosensitive material with a high temperature coefficient of resistance (TCR) is deposited on the bridge deck, and the bridge deck is supported by two bridge legs with good mechanical properties and plated with conductive materials. The contact points between the bridge legs and the substrate are bridge piers, which are electrically connected to the silicon readout integrated circuit (ROIC) under the microbolometer. Through the bridge legs and bridge piers, the thermosensitive material is connected to the electrical channel of the readout circuit, forming a pixel unit that is sensitive to temperature and connected to the readout circuit.

[0047] In the prior art, the readout circuit does not have a suitable bias circuit, so the Joule heat effect generated by the microbolometer focal plane array cannot be offset, and the asymmetric power supply noise and circuit noise will also have a great impact on the performance.

[0048] For example, refer to Figure 1 , Figure 1 The detection pixel blocks include multiple detection pixel blocks, which are arranged in an array, with a total of i rows and j columns; each detection pixel block includes: m rows and n columns of detection pixels.

[0049] Based on this, some embodiments of the present application provide a readout circuit. Figure 2 As shown, the present application provides a readout circuit 100. The readout circuit 100 comprises: a plurality of detection pixel blocks 1 and at least one reference pixel block 2 arranged in an array.

[0050] The detection pixel block 1 includes a plurality of detection pixels Pt arranged in an array; the number of reference pixel blocks 2 is less than or equal to the number of rows of the plurality of detection pixel blocks 1; one reference pixel block 2 is correspondingly connected to at least one row of detection pixel blocks 1; the reference pixel block 2 includes a plurality of reference pixels Pc arranged in an array.

[0051] The reference pixel block 2 is used to sequentially connect to a plurality of rows of the detection pixel blocks 1 ; the detection pixel block 1 is used to output a detection signal when connected to the reference pixel block 2 .

[0052] in, Figure 2 The m and n in refers to that the multiple reference pixels Pc included in the reference pixel block 2 are arranged in m rows and n columns; similarly, the multiple detection pixels Pt included in the detection pixel block 1 are arranged in m rows and n columns. i and j refer to that the multiple detection pixel block 1 is arranged in i rows and j columns.

[0053] In some embodiments, Figure 2As shown, when the number of reference pixel blocks 2 is one, the reference pixel block 2 is connected to the first row of detection pixel blocks 1, and the first row of detection pixel blocks 1 outputs a detection signal when connected to the reference pixel block 2; then the reference pixel block 2 is connected to the second row of detection pixel blocks 1, until the i-th row of detection pixel blocks 1 is completely connected.

[0054] In some embodiments, the detection signal is a current signal.

[0055] When the reference pixel block 2 is not connected to the corresponding detection pixel block 1 and the readout circuit 100 is working, the internal temperature will gradually increase, that is, when the current passes through the detection pixel block 1, heat will be generated, which will affect the resistance value of the detection pixel block 1, and finally affect the size of the output current, which will be different from the current obtained by detection, thereby generating noise.

[0056] After the reference pixel block 2 is connected to a column of detection pixel blocks 1, the characteristics of the reference pixel block 2 and the detection pixel block 1 are consistent, so the noise generated can be offset and the influence of horizontal stripes on the image can be reduced. In other words, when the detection pixel block 1 is working, the reference pixel block 2 is connected to offset the noise and then output the current.

[0057] At the same time, in the present application, by using the reference pixel block 2 to replace the reference pixel Pc, and using the detection pixel block 1 to replace the detection pixel Pt, when processing and analyzing the image, the reference pixel block can be used to process and conduct multiple detection pixels in parallel, thereby improving the processing efficiency. And when a single reference pixel block 2 is used, a bias can be provided for all detection pixel blocks 1 at the same time, which can extend the integration time and improve the performance compared to the traditional structure of using only a single pixel.

[0058] In the present application, a reference pixel block 2 that senses Joule heat is added, thereby providing a suitable bias and eliminating the influence of Joule heat on the detection pixel block 1.

[0059] Based on the above scheme, the embodiment of the present application provides a readout circuit 100, which reduces noise by adding reference pixel blocks 2 and changing the number. When a row of detection pixel blocks 1 is working, a reference pixel block 2 is connected so that the output current does not change; after the detection pixel blocks 1 in this row have completed their work, they are disconnected from the reference pixel blocks 2, and then when another row of detection pixel blocks 1 starts working, a reference pixel block 2 is connected so that the output current does not change; then at least one reference pixel block 2 is connected to a row of detection pixel blocks 1 to work, and the process stops after all detection pixel blocks 1 have completed their work. In this way, noise can be reduced and better matching can be achieved by only using at least one reference pixel block 2, thereby reducing the impact of horizontal stripes on the image.

[0060] like Figure 3 to Figure 7As shown, in some embodiments, the detection pixel Pt includes: a first resistor Rs; the reference pixel Pc includes: a second resistor Rsm.

[0061] The resistance values ​​of the first resistor Rs and the second resistor Rsm decrease as the temperature increases.

[0062] like Figure 3 and Figure 7 As shown, the readout circuit 100 further includes: a first control subcircuit 11 .

[0063] The first control subcircuit 11 is connected to at least one reference pixel block 2 ; the first control subcircuit 11 is used to turn on at least one reference pixel block 2 .

[0064] In some embodiments, the first control subcircuit 11 includes: a plurality of first switches Srsm; a first switch Srsm is correspondingly connected to a second resistor Rsm, when the first switch Srsm is turned on, the reference pixel Pc is turned on; when the first switch Srsm is turned off, the reference pixel Pc is turned off.

[0065] like Figure 3 and Figure 7 As shown, the readout circuit 100 further includes: a second control subcircuit 12 .

[0066] The second control subcircuit 12 is connected to multiple detection pixel blocks 1; the second control subcircuit 12 is used to make multiple rows of detection pixel blocks 1 turn on in sequence when a reference pixel block 2 is turned on, and when each row of detection pixel blocks 1 is turned on, make each detection pixel block 1 in the row of detection pixel blocks 1 turn on at the same time and output detection signals.

[0067] In some embodiments, the second control subcircuit 12 includes: a plurality of second switches Srs; a second switch Srs is correspondingly connected to a first resistor Rs, when the second switch Srs is turned on, the detection pixel Pt is turned on; when the second switch Srs is turned off, the detection pixel Pt is turned off.

[0068] For example, refer to Figure 3 When the number of reference pixel blocks 2 is one, the first control subcircuit 11 is used to turn on the reference pixel block 2; when the first control subcircuit 11 controls the reference pixel block 2 to be turned on, the second control subcircuit 12 simultaneously turns on multiple detection pixel blocks 1 in the first row of detection pixel blocks 1; then the second control subcircuit 12 controls the first row of detection pixel blocks 1 to be turned off, and the second control subcircuit 12 then simultaneously turns on multiple detection pixel blocks 1 in the second row of detection pixel blocks 1; until multiple detection pixel blocks 1 in the i-th row of detection pixel blocks 1 are turned on at the same time; finally, the detection signal is output.

[0069] In some embodiments, reference Figure 4, at least one reference pixel block 2 includes two reference pixel blocks 2.

[0070] The first control subcircuit 11 is used to turn on the reference pixel block 2. When the first control subcircuit 11 controls the first reference pixel block 2 to turn on, the second control subcircuit 12 simultaneously turns on each detection pixel block 1 in the first row of detection pixel blocks 1, so that each detection pixel block 1 in the first row of detection pixel blocks 1 outputs a detection signal. Then, when the first control subcircuit 11 controls the first reference pixel block 2 to turn off and controls the second reference pixel block 2 to turn on, the second control subcircuit 12 then simultaneously turns on each detection pixel block 1 in the second row of detection pixel blocks 1.

[0071] Then the first control subcircuit 11 controls the second reference pixel block 2 to be turned off, and when the first reference pixel block 2 is turned on, the second control subcircuit 12 turns on all the detection pixel blocks 1 in the third row of detection pixel blocks 1 at the same time. This process is repeated until multiple detection pixel blocks 1 in the i-th row of detection pixel blocks 1 are turned on at the same time, and finally the detection signal is output.

[0072] In some embodiments, reference Figure 5 , at least one reference pixel block 2 includes i reference pixel blocks 2. Where i is the number of rows of detection pixel blocks. That is, one reference pixel block 2 corresponds to a connected row of detection pixel blocks 1.

[0073] The first control subcircuit 11 is used to turn on the reference pixel block 2. When the first control subcircuit 11 controls the first reference pixel block 2 to be turned on, the second control subcircuit 12 simultaneously turns on multiple detection pixel blocks 1 in the first row of detection pixel blocks 1, so that the multiple detection pixel blocks 1 in the first row of detection pixel blocks 1 output detection signals. Then, when the first control subcircuit 11 controls the first reference pixel block 2 to be turned off and controls the second reference pixel block 2 to be turned on, the second control subcircuit 12 then simultaneously turns on multiple detection pixel blocks 1 in the second row of detection pixel blocks 1.

[0074] Then the first control subcircuit 11 controls the second reference pixel block 2 to be turned off, and when the third reference pixel block 2 is turned on, the second control subcircuit 12 simultaneously turns on multiple detection pixel blocks 1 in the third row of detection pixel blocks 1. This process is repeated until the first control subcircuit 11 controls the i-th reference pixel block 2 to be turned on, and the second control subcircuit 12 simultaneously turns on multiple detection pixel blocks 1 in the i-th row of detection pixel blocks 1; finally, the detection signal is output.

[0075] The fewer the number of reference pixel blocks 2, the higher the matching degree, the easier it is to offset the noise, and at the same time, the area of ​​the readout circuit 100 occupied is smaller, which can reduce the overall cost.

[0076] In some embodiments, when the number of reference pixel blocks 2 is small, the size of the reference pixel blocks 2 may be increased, thereby reducing 1 / f noise.

[0077] 1 / f noise, also known as flicker noise or pink noise, is a type of noise that is common in electronic devices and circuits. Its characteristic is that the power spectrum density of the noise is inversely proportional to the frequency, that is, as the frequency decreases, the intensity of the noise increases. This noise is particularly significant at low frequencies and may have a certain impact on the performance of electronic equipment.

[0078] Methods to reduce 1 / f noise include selecting appropriate electronic components, optimizing circuit design, and applying noise suppression techniques. For example, using high-quality electronic components can reduce the impact of internal defects and impurities on noise; optimizing circuit design can reduce the impact of noise sources.

[0079] In the present application, the possibility of internal defects of electronic devices is reduced by reducing the number of reference pixel blocks 2 and increasing the size of reference pixel blocks 2, thereby reducing 1 / f noise.

[0080] It should be noted that both resistors Rsmx and Rsx will change resistance under the influence of Joule heat. The higher the temperature, the lower the resistance value. In the traditional readout circuit, only resistor Rsx can be affected by Joule heat, which will make the readout circuit asymmetric, and the influence of power supply noise and circuit noise will be greatly increased. Therefore, the resistor Rsmx is replaced with a resistor of the same type as the resistor Rsx, so that it can be affected by Joule heat, so that the readout circuit can become symmetrical, offsetting the influence of power supply noise and circuit noise.

[0081] In some embodiments, Figure 2 and Figure 3 As shown, a plurality of detection pixel blocks 1 are arranged into i rows of detection pixel blocks 1; and at least one reference pixel block 2 includes: a reference pixel block 2.

[0082] The reference pixel block 2 includes m×n reference pixels, and the detection pixel block 1 includes m×n detection pixels. Each reference pixel in the reference pixel block 2 corresponds to each detection pixel in the detection pixel block 1 one by one; the reference pixel block 2 is connected correspondingly to the i-row detection pixel block 1; each reference pixel in the reference pixel block 2 is turned on in turn, and when the reference pixel is turned on, the corresponding detection pixels of each detection pixel block 1 in the i-row detection pixel block 1 are turned on at the same time.

[0083] Reference Figure 2 and Figure 3It can be seen that when there is only one reference pixel block 2, when the first reference pixel in a reference pixel block 2 is turned on, the first detection pixel in each detection pixel block 1 is also turned on correspondingly, thereby outputting a detection signal.

[0084] In some embodiments, Figure 3 As shown, a plurality of detection pixel blocks 1 are arranged into i rows of detection pixel blocks 1; at least one reference pixel block 2 includes: h reference pixel blocks 2; 2≤h≤i-1.

[0085] The reference pixel block 2 includes m×n reference pixels, the detection pixel block 1 includes m×n detection pixels, each reference pixel in the reference pixel block 2 corresponds to each detection pixel in the detection pixel block 1 one by one; one reference pixel block 2 is connected to k rows of detection pixel blocks 1; 1≤k<i-1.

[0086] Each reference pixel in a reference pixel block 2 is turned on in sequence. When the reference pixel is turned on, the corresponding detection pixels in each detection pixel block 1 in the k-row detection pixel block 1 are turned on at the same time.

[0087] Reference Figure 4 It can be seen that, for example, when h=2, i=20, 1≤k<19; there are two reference pixel blocks 2 and twenty detection pixel blocks 1. When the first reference pixel of the first reference pixel block 2 is turned on, the first detection pixel of the k-row detection pixel block 1 is also turned on, thereby outputting a detection signal. When the first reference pixel of the second reference pixel is turned on, the first detection pixel of the k-row detection pixel block 1 is also turned on, thereby outputting a detection signal; it can be seen that k=10, that is, one reference pixel block 2 corresponds to 10 detection pixel blocks 1.

[0088] In some embodiments, the first reference pixel block 2 may correspond to 8 rows of detection pixel blocks 1, and the second reference pixel block 2 may correspond to 12 rows of detection pixel blocks 1. As long as all detection pixel blocks 1 are turned on, no specific allocation is required.

[0089] In some embodiments, Figure 5 As shown, a plurality of detection pixel blocks 1 are arranged into i rows of detection pixel blocks 1 ; and at least one reference pixel block 2 includes: i reference pixel blocks 2 .

[0090] The reference pixel block 2 includes m×n reference pixels, and the detection pixel block 1 includes m×n detection pixels. Each reference pixel in the reference pixel block 2 corresponds to each detection pixel in the detection pixel block 1 one by one; i reference pixel blocks 2 are connected correspondingly to i rows of detection pixel blocks 1; each reference pixel in a reference pixel block 2 is turned on in turn, and when the reference pixel is turned on, the corresponding detection pixels of each detection pixel block 1 in a row of detection pixel blocks 1 are turned on at the same time.

[0091] Reference Figure 4 It can be seen that, for example, when i=20, there are a total of twenty reference pixel blocks 2 and twenty rows of detection pixel blocks 1. When the first reference pixel of the first reference pixel block 2 is turned on, the first detection pixel of each detection pixel block 1 of the first row of detection pixel blocks 1 is also turned on accordingly, thereby outputting a detection signal. When the first reference pixel of the second reference pixel is turned on, the first detection pixel of each detection pixel block 1 of the second row of detection pixel blocks 1 is also turned on accordingly, thereby outputting a detection signal; and so on, until all twenty rows of detection pixel blocks 1 are turned on.

[0092] like Figure 6 and Figure 7 As shown, in some embodiments, the number of reference pixels Pc in the reference pixel block 2 is the same as the number of detection pixels Pt in the detection pixel block 1. Figure 6 The reference pixel block 2 and the detection pixel block 1 are both 2*2 arrays.

[0093] The four reference pixels Pc are turned on in sequence through the first switch Srsm. When the first switch Srsm controls the first reference pixel Pc to be turned on, the second switch Srs controls the first detection pixel Pt of each detection pixel block of the first row detection pixel block 1 to be turned on; that is, Rsm <1> With Rs11 <1> , Rs12 <1> ……Rs1n <1> A total of n detection pixels Pt are turned on at the same time and then output detection signals.

[0094] Next, when the first switch Srsm controls the second reference pixel Pc to be turned on, the second switch Srs controls the second detection pixel Pt of each detection pixel block of the first row detection pixel block 1 to be turned on; that is, Rsm <2> With Rs11 <2> , Rs12 <2> ……Rs1n <2> A total of n detection pixels Pt are turned on at the same time and then output detection signals.

[0095] When the first switch Srsm controls the third reference pixel Pc to be turned on, the second switch Srs controls the third detection pixel Pt of each detection pixel block of the first row detection pixel block 1 to be turned on; that is, Rsm <3> With Rs11 <3> , Rs12 <3> ……Rs1n <3> A total of n detection pixels Pt are turned on at the same time and then output detection signals.

[0096] When the first switch Srsm controls the fourth reference pixel Pc to be turned on, the second switch Srs controls the fourth detection pixel Pt of each detection pixel block of the first row detection pixel block 1 to be turned on; that is, Rsm <4> With Rs11 <4> , Rs12 <4> ……Rs1n <4> A total of n detection pixels Pt are turned on at the same time and then output detection signals.

[0097] According to the above control method, the second switch then sequentially connects the detection pixel blocks of other rows until the mth row.

[0098] in, Figure 6 This is only an embodiment of a 2*2 array, and other cases will not be described in detail.

[0099] like Figure 7 As shown, in some embodiments, the readout circuit 100 further includes: a bridge unit 20 .

[0100] The first end of the bridge unit 20 is electrically connected to the power supply terminal VSK, the second end of the bridge unit 20 is electrically connected to the power supply terminal VSK, the third end of the bridge unit 20 is electrically connected to one end of the first control subcircuit 11, the other end of the first control subcircuit 11 is electrically connected to the first end of the reference pixel block 2, the fourth end of the bridge unit 20 is electrically connected to one end of the second control subcircuit 12, and the other end of the second control subcircuit 12 is electrically connected to the first end of the detection pixel block 1.

[0101] That is to say, the first control subcircuit 11 also controls the conduction or disconnection between the bridge unit 20 and the reference pixel block 2 ; the second control subcircuit 12 also controls the conduction or disconnection between the bridge unit 20 and the detection pixel block 1 .

[0102] Among them, it should be noted that Figure 6 This corresponds to a schematic diagram of a 2×2 array of detection pixels in a reference pixel block. Figure 7 The corresponding one is a readout circuit diagram in which the number of detection pixels in the reference pixel block is N.

[0103] like Figure 7 As shown, the bridge unit 20 includes: a first subunit 21 and a plurality of second subunits 22, and the plurality of second subunits 22 are connected in parallel.

[0104] The first end of the first subunit 21 is electrically connected to the first end of the bridge unit 20 , and the second end of the first subunit 21 is electrically connected to the third end of the bridge unit 20 .

[0105] The first end of the second subunit 22 is electrically connected to the second end of the bridge unit 20, the second end of the first subunit 21 is electrically connected to the fourth end of the bridge unit 20; the third end of the second subunit 22 is electrically connected to the third end of the first subunit 21; the fourth end of the second subunit 22 is electrically connected to the fourth end of the first subunit 21.

[0106] The second subunit 22 is connected to a row of detection pixel blocks 1 .

[0107] The first subunit 21 includes: a third resistor Rdm, a first transistor M1 and a second transistor M2.

[0108] A first end of the third resistor Rdm is electrically connected to a first end of the first subunit 21 , and a second end of the third resistor Rdm is electrically connected to a first end of the first transistor M1 .

[0109] The control terminal of the first transistor M1 is electrically connected to the third terminal of the first subunit 21 , and the second terminal of the first transistor M1 is electrically connected to the first terminal of the second transistor M2 .

[0110] The control end of the second transistor M2 is electrically connected to the fourth end of the first subunit 21 , the control end of the second transistor M2 is also electrically connected to the first end of the second transistor M2 , and the second end of the second transistor M2 is electrically connected to the second end of the first subunit 21 .

[0111] The first subunit 21 includes: a fourth resistor Rd, a third transistor M3 and a fourth transistor M4.

[0112] A first end of the fourth resistor Rd is electrically connected to a first end of the second subunit 22 , and a second end of the fourth resistor Rd is electrically connected to a first end of the third transistor M3 .

[0113] The control end of the third transistor M3 is electrically connected to the third end of the second subunit 22 , and the second end of the third transistor M3 is electrically connected to the first end of the fourth transistor M4 .

[0114] The control terminal of the fourth transistor M4 is electrically connected to the fourth terminal of the second sub-unit 22 , and the second terminal of the fourth transistor M4 is electrically connected to the second terminal of the second sub-unit 22 .

[0115] It should be noted that the detection signal refers to the current output by the fourth transistor M4. The purpose of this application is to keep the current output by the first transistor M1 unchanged, so the reference pixel block 2 is introduced to offset the detection pixel block. When the detection pixel block is working, the resistance will decrease due to the influence of Joule heat, and the current flowing through the detection pixel block will increase, that is, the current output by the first transistor M1 will increase. In order to ensure that the current of the first transistor M1 remains unchanged, the bias voltage Vfid needs to be reduced synchronously; in order to reduce the bias voltage Vfid synchronously, the current output by the fourth transistor M4 needs to remain unchanged when the resistance of the reference pixel block 2 is reduced. Therefore, by turning on the reference pixel block 2, the bias voltage Vfid can be reduced, so that the current of the first transistor M1 remains unchanged.

[0116] Among them, refer to Figure 6 and Figure 7 In the case where both the reference pixel block 2 and the detection pixel block 1 are 2*2 arrays, the bias voltage Vfid is reduced through four reference pixels, that is, four second resistors Rsm, so that the current of the first transistor M1 remains unchanged, thereby eliminating the influence of Joule heat on the output dynamic range.

[0117] Reference Figure 7 and Figure 8 , in the first second switch Srsm <1> When turned on, the first switch Srs corresponding to each column of detection pixel block 1 <1> The corresponding conduction makes the first row detection pixel block 1 connected to the first reference pixel block 2, and the second switch Srsm <2> When turned on, the second first switch Srs corresponding to each column of detection pixel block 1 <2> Correspondingly, the second row detection pixel block 1 is connected to the first reference pixel block 2, and the first second switch Srsm <1> When it is turned on again, the third first switch Srs corresponding to each column of detection pixel block 1 <3> Correspondingly, the third row of detection pixel block 1 is connected to the first reference pixel block 2, and so on, until all detection pixel blocks 1 complete the work.

[0118] It should be noted that Figure 8 is a timing diagram of the first switch and the second switch.

[0119] like Figure 7 As shown, the readout circuit further includes: a plurality of signal processing sub-circuits 3.

[0120] An input terminal of the signal processing subcircuit 3 is electrically connected to an output terminal of the bridge unit 20 .

[0121] In the case of only one reference pixel block 2, when one reference pixel block 2 is connected to one detection pixel block 1, the signal processing subcircuit 3 is configured to integrate one detection pixel block 1, and after one detection pixel block 1 is integrated, one reference pixel block 2 is disconnected from one detection pixel block. When one reference pixel block 2 is connected to another detection pixel block 1, the signal processing subcircuit 3 is configured to integrate another detection pixel block 1, and after another detection pixel block 1 is integrated, one reference pixel block 2 is disconnected from another detection pixel block 1.

[0122] When there are multiple reference pixel blocks, you can refer to Figure 3 to Figure 6 The description will not be elaborated here.

[0123] Based on the above scheme, the embodiment of the present application provides a readout circuit, and the readout circuit 100 works through at least one reference pixel block 2 to offset the noise generated by the detection pixel block 1. When a row of detection pixel blocks 1 is working, a reference pixel block 2 is connected so that the output current does not change, and the current is transmitted to a signal processing subcircuit 3, and a signal processing subcircuit 3 converts the current into a voltage output; after the row of detection pixel blocks 1 completes the work, it is disconnected from the reference pixel block 2, and then when another row of detection pixel blocks 1 starts working, a reference pixel block 2 is connected so that the output current does not change, and the current is transmitted to another signal processing subcircuit 3, and another signal processing subcircuit 3 converts the current into a voltage output; then at least one reference pixel block 2 is connected to a row of detection pixel blocks 1 to work until all detection pixel blocks 1 have completed the work and stop. In this way, noise can be reduced and better matching can be achieved by only using at least one reference pixel block 2, thereby reducing the influence of horizontal stripes on the image.

[0124] The present application also provides a readout method of a readout circuit, the specific process is as follows:

[0125] S1. The reference pixel block 2 is connected to multiple rows of detection pixel blocks 1 in sequence.

[0126] S2. When the detection pixel block 1 is connected with the reference pixel block 2, it outputs a detection signal.

[0127] For example, when a row of detection pixel blocks 1 is working, a reference pixel block 2 is connected so that the output current does not change; after the row of detection pixel blocks 1 completes its work, it is disconnected from the reference pixel block 2, and then when another row of detection pixel blocks 1 starts working, a reference pixel block 2 is connected so that the output current does not change; then at least one reference pixel block 2 is connected to a row of detection pixel blocks 1 to work, and the process stops after all detection pixel blocks 1 complete their work. In this way, noise can be reduced and better matching can be achieved by only using at least one reference pixel block 2, thereby reducing the impact of horizontal stripes on the image.

[0128] The number of reference pixel blocks 2 is greater than or equal to 1 and less than or equal to the number of rows of detection pixel block 1. The detection signal is the output current.

[0129] When the readout circuit 100 further includes: a first control subcircuit 11 and a second control subcircuit 12:

[0130] S11 . The first control subcircuit 11 turns on at least one reference pixel block 2 .

[0131] For example, when the number of reference pixel blocks 2 is one, the first control subcircuit 11 is used to turn on the reference pixel block 2; when the first control subcircuit 11 controls the reference pixel block 2 to be turned on, multiple detection pixel blocks 1 in the first row of detection pixel blocks 1 are turned on with the reference pixel block 2; then the first row of detection pixel blocks 1 are controlled to be disconnected, and then multiple detection pixel blocks 1 in the second row of detection pixel blocks 1 are turned on with the reference pixel block 2; until multiple detection pixel blocks 1 in the i-th row of detection pixel blocks 1 are turned on at the same time; finally, a detection signal is output.

[0132] Here, i refers to the row number of the detection pixel block 1.

[0133] S21, when a reference pixel block 2 is turned on, the second control subcircuit 12 turns on multiple rows of detection pixel blocks 1 in sequence, and when each row of detection pixel blocks 1 is turned on, each detection pixel block 1 in a row of detection pixel blocks 1 is turned on at the same time, and a row of detection pixel blocks 1 outputs a detection signal.

[0134] For example, when the number of reference pixel blocks 2 is one, the first control subcircuit 11 is used to turn on the reference pixel block 2; when the first control subcircuit 11 controls the reference pixel block 2 to be turned on, the second control subcircuit 12 simultaneously turns on multiple detection pixel blocks 1 in the first row of detection pixel blocks 1; then the second control subcircuit 12 controls the first row of detection pixel blocks 1 to be turned off, and the second control subcircuit 12 then simultaneously turns on multiple detection pixel blocks 1 in the second row of detection pixel blocks 1; until multiple detection pixel blocks 1 in the i-th row of detection pixel blocks 1 are turned on at the same time; and finally, the detection signal is output.

[0135] Here, i refers to the row number of the detection pixel block 1.

[0136] In the case where the first control subcircuit 11 includes a plurality of first switches Srsm and the second control subcircuit 12 includes a plurality of second switches Srs:

[0137] S111. The first switch Srsm turns on a plurality of reference pixels.

[0138] For example, when the number of reference pixel blocks 2 is one, the first switch Srsm is used to turn on multiple reference pixels in the reference pixel block 2, and turn them on in sequence; when the first switch Srsm controls the first reference pixel in the reference pixel block 2 to turn on, the second control subcircuit 12 simultaneously turns on the first detection pixel of the multiple detection pixel blocks 1 in the first row of detection pixel blocks 1; then when the first switch Srsm controls the second reference pixel in the reference pixel block 2 to turn on, the second control subcircuit 12 simultaneously turns on the second detection pixel of the multiple detection pixel blocks 1 in the first row of detection pixel blocks 1; until all the detection pixel blocks 1 in the detection pixel block 1 are turned on at the same time; and finally, the detection signal is output.

[0139] S211. When a reference pixel is turned on, the second switch Srs sequentially turns on a detection pixel in each detection pixel block 1 in a column of detection pixel blocks 1, so that multiple detection pixels in each detection pixel block 1 in a column of detection pixel blocks 1 output detection signals.

[0140] For example, when the number of reference pixel blocks 2 is one, the first switch Srsm is used to turn on multiple reference pixels in the reference pixel block 2, and turn them on in sequence; when the first switch Srsm controls the first reference pixel in the reference pixel block 2 to be turned on, the second switch Srs simultaneously turns on the first detection pixel of the multiple detection pixel blocks 1 in the first row of detection pixel blocks 1; then when the first switch Srsm controls the second reference pixel in the reference pixel block 2 to be turned on, the second switch Srs simultaneously turns on the second detection pixel of the multiple detection pixel blocks 1 in the first row of detection pixel blocks 1; until all the detection pixel blocks 1 in the detection pixel block 1 are turned on at the same time; and finally, the detection signal is output.

[0141] In the case where the readout circuit 100 further includes a plurality of signal processing sub-circuits 3:

[0142] S101. When a reference pixel block 2 is connected to a detection pixel block 1, a signal processing subcircuit 3 integrates a detection pixel block 1. After a detection pixel block 1 is integrated, a reference pixel block 2 is disconnected from a detection pixel block 1.

[0143] S102, when a reference pixel block 2 is connected to another detection pixel block 1, a signal processing subcircuit 3 integrates the other detection pixel block 1, and after the other detection pixel block 1 is integrated, a reference pixel block 2 is disconnected from the other detection pixel block 1.

[0144] For example, when a row of detection pixel blocks 1 is working, a reference pixel block 2 is connected so that the output current does not change, and the current is transmitted to a signal processing subcircuit 3, and the signal processing subcircuit 3 converts the current into a voltage output; after the row of detection pixel blocks 1 completes the work, it is disconnected from the reference pixel block 2, and then when another row of detection pixel blocks 1 starts working, a reference pixel block 2 is connected so that the output current does not change, and the current is transmitted to another signal processing subcircuit 3, and the other signal processing subcircuit 3 converts the current into a voltage output; then at least one reference pixel block 2 is connected to a row of detection pixel blocks 1 to work, and the process stops after all detection pixel blocks 1 complete the work. In this way, noise can be reduced and better matching can be achieved by only using at least one reference pixel block 2, thereby reducing the influence of horizontal stripes on the image.

[0145] Among them, one detection pixel block 1 is correspondingly connected to one signal processing sub-circuit 3.

[0146] like Fig. 9 As shown, some embodiments of the present application further provide an infrared detector, and the infrared detector 200 includes: a readout circuit 100 .

[0147] Based on the above scheme, when the readout circuit in the infrared detector in the present application includes at least one reference pixel block, it is beneficial to reduce 1 / f noise and reduce the influence of horizontal stripes on the image; when the number of reference pixel blocks is expanded, the influence of non-ideal factors such as gradient differences caused by layout and routing parasitics can be reduced. And because there is no large area consumption of reference pixel blocks, the reference pixel blocks can be made to have the same number of rows as the detection pixel blocks, which is beneficial to reduce 1 / f noise and thermal noise.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A readout circuit, characterized in that: include: A plurality of detection pixel blocks arranged in an array, wherein the detection pixel block comprises a plurality of detection pixels arranged in an array; at least one reference pixel block, the number of the reference pixel blocks being less than or equal to the number of rows of the plurality of detection pixel blocks; One of the reference pixel blocks is correspondingly connected to at least one row of the detection pixel blocks; the reference pixel block includes a plurality of reference pixels arranged in an array; The reference pixel block is used to sequentially connect with each of the detection pixel blocks in at least one row of the detection pixel blocks; The detection pixel block is used to output a detection signal when connected with the reference pixel block.

2. The readout circuit according to claim 1, characterized in that: The readout circuit further includes: a first control subcircuit connected to the at least one reference pixel block; The first control subcircuit is used to turn on the at least one reference pixel block.

3. The readout circuit according to claim 2, characterized in that: The first control subcircuit includes: a plurality of first switches; One of the first switches is connected to one of the reference pixels accordingly.

4. The readout circuit according to claim 1 or 2, characterized in that: The readout circuit further includes: a second control subcircuit connected to the plurality of detection pixel blocks; The second control subcircuit is used to enable at least one row of the detection pixel blocks to be turned on simultaneously when one of the reference pixel blocks is turned on, and to enable each detection pixel block in at least one row of the detection pixel blocks to be turned on simultaneously and output a detection signal when at least one row of the detection pixel blocks is turned on.

5. The readout circuit according to claim 4, characterized in that: The second control subcircuit includes: a plurality of second switches; One of the second switches is connected to one of the detection pixels accordingly.

6. The readout circuit according to claim 1, characterized in that: The detection pixel comprises: a first resistor; the reference pixel comprises: a second resistor; The resistance values ​​of the first resistor and the second resistor decrease as the temperature increases.

7. The readout circuit according to claim 1, characterized in that: The plurality of detection pixel blocks are arranged into i rows of detection pixel blocks; The at least one reference pixel block comprises: a reference pixel block; The reference pixel block includes m×n reference pixels, the detection pixel block includes m×n detection pixels, and each reference pixel in the reference pixel block corresponds to each detection pixel in the detection pixel block one by one; The reference pixel block is correspondingly connected to the i-row detection pixel block; Each reference pixel in the reference pixel block is turned on in sequence. When the reference pixel is turned on, the corresponding detection pixel in each detection pixel block in the i-row detection pixel block is turned on at the same time.

8. The readout circuit according to claim 1, characterized in that: The plurality of detection pixel blocks are arranged into i rows of detection pixel blocks; The at least one reference pixel block includes: h reference pixel blocks; 2≤h≤i-1; The reference pixel block includes m×n reference pixels, the detection pixel block includes m×n detection pixels, and each reference pixel in the reference pixel block corresponds to each detection pixel in the detection pixel block one by one; One of the reference pixel blocks is connected to k rows of detection pixel blocks in correspondence; 1≤k<i-1; The reference pixels in one of the reference pixel blocks are turned on in sequence. When the reference pixels are turned on, the corresponding detection pixels in each detection pixel block in the k-row detection pixel block are turned on at the same time.

9. The readout circuit according to claim 1, characterized in that: The plurality of detection pixel blocks are arranged into i rows of detection pixel blocks; The at least one reference pixel block comprises: i reference pixel blocks; The reference pixel block includes m×n reference pixels, the detection pixel block includes m×n detection pixels, and each reference pixel in the reference pixel block corresponds to each detection pixel in the detection pixel block one by one; The i reference pixel blocks are correspondingly connected to the i rows of detection pixel blocks; The reference pixels in one of the reference pixel blocks are turned on in sequence. When the reference pixels are turned on, the corresponding detection pixels in each detection pixel block in a row of the detection pixel blocks are turned on at the same time.

10. The readout circuit according to claim 4, characterized in that: The readout circuit further comprises: a bridge unit; in the case where the readout circuit further comprises a first control subcircuit; The first end of the bridge unit is electrically connected to the power supply end, the second end of the bridge unit is electrically connected to the power supply end, the third end of the bridge unit is electrically connected to one end of the first control subcircuit, the other end of the first control subcircuit is electrically connected to the first end of the reference pixel block, the fourth end of the bridge unit is electrically connected to one end of the second control subcircuit, and the other end of the second control subcircuit is electrically connected to the first end of the detection pixel block.

11. The readout circuit according to claim 10, characterized in that: The bridge unit comprises: a first subunit and a plurality of second subunits, wherein the plurality of second subunits are connected in parallel; The first end of the first subunit is electrically connected to the first end of the bridge unit, and the second end of the first subunit is electrically connected to the third end of the bridge unit; The first end of the second subunit is electrically connected to the second end of the bridge unit, the second end of the first subunit is electrically connected to the fourth end of the bridge unit; the third end of the second subunit is electrically connected to the third end of the first subunit; the fourth end of the second subunit is electrically connected to the fourth end of the first subunit; The second subunit is connected to a row of detection pixel blocks.

12. The readout circuit according to claim 10, characterized in that: The readout circuit further includes: a plurality of signal processing subcircuits; one of the signal processing subcircuits is correspondingly connected to one of the detection pixel blocks; The input end of the signal processing subcircuit is electrically connected to the output end of the bridge unit; When one of the reference pixel blocks is connected to one of the detection pixel blocks, one of the signal processing subcircuits is configured to integrate one of the detection pixel blocks, and after one of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from one of the detection pixel blocks; One of the reference pixel blocks is connected to another of the detection pixel blocks, and another of the signal processing subcircuits is configured to integrate another of the detection pixel blocks. After the other of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from another of the detection pixel blocks.

13. A readout method of a readout circuit, characterized in that: Applicable to a readout circuit as claimed in any one of claims 1 to 12; The reference pixel block is sequentially connected to a plurality of rows of detection pixel blocks; The detection pixel block outputs a detection signal when connected with the reference pixel block.

14. The reading method according to claim 13, characterized in that: In the case where the readout circuit further comprises: a first control subcircuit and a second control subcircuit; The first control subcircuit turns on the at least one reference pixel block; When one of the reference pixel blocks is turned on, the second control subcircuit turns on multiple rows of detection pixel blocks in sequence, and when each row of detection pixel blocks is turned on, each detection pixel block in the row is turned on at the same time, and the row of detection pixel blocks outputs a detection signal.

15. The reading method according to claim 14, characterized in that: In the case where the first control subcircuit includes a plurality of first switches and the second control subcircuit includes a plurality of second switches; The first switch turns on the plurality of reference pixels; When one of the reference pixels is turned on, the second switch sequentially turns on one detection pixel of each detection pixel block in a column of detection pixel blocks, so that multiple detection pixels of each detection pixel block in the column of detection pixel blocks output detection signals.

16. The reading method according to any one of claims 13 to 15, characterized in that: In the case where the readout circuit further comprises a plurality of signal processing sub-circuits; When one of the reference pixel blocks is connected to one of the detection pixel blocks, one of the signal processing subcircuits integrates one of the detection pixel blocks, and after one of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from one of the detection pixel blocks; When one of the reference pixel blocks is connected to another of the detection pixel blocks, another of the signal processing subcircuits integrates the other of the detection pixel blocks. After the other of the detection pixel blocks is integrated, one of the reference pixel blocks is disconnected from the other of the detection pixel blocks.

17. An infrared detector, characterized in that: include: The readout circuit according to any one of claims 1 to 12.

Images