Method, device and equipment for inhibiting SBFET threshold voltage drift

Abstract

The invention discloses a method, a device and equipment for inhibiting threshold voltage drift of an SBFET, relates to the technical field of semiconductors, and aims to solve the problem of threshold voltage drift during transfer characteristic test of the SBFET in the prior art. The method comprises the following steps: acquiring actual measurement data of SBFET gate voltage and drain current transfer characteristics, and acquiring simulation test data of an SBFET interface trap and an oxide layer trap; the simulation test data comprises simulation test data of grid voltage and drain current transfer characteristics; based on the simulation test data and the actual measurement data, determining a target trap influencing SBFET threshold voltage drift; further determining a target charging voltage and a target charging duration of the target trap; and finally, based on the target charging voltage and the target charging duration, charging the target trap so as to suppress the drift of the threshold voltage when the SBFET is subjected to the transfer characteristic test. On the basis, effective suppression of threshold voltage drift during repeated transfer characteristic testing of the SBFET is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of Schottky barrier diodes, and in particular to a method, a device and equipment for suppressing SBFET threshold voltage drift. Background Art

[0002] When repeatedly testing the transfer characteristic curve of the SBFET (Schottky barrier field effect transistor) structure, a unidirectional drift of the threshold voltage occurred. This threshold voltage drift phenomenon is a huge interference to the threshold voltage drift after irradiation. If this interference cannot be resolved before the irradiation experiment, it will have a huge impact on the total dose effect research of the SBFET device.

[0003] Therefore, there is an urgent need for a technical solution that can suppress the threshold voltage drift of the SBFET to solve the problem of threshold voltage drift when performing transfer characteristic testing on the Schottky barrier field effect transistor in the prior art. Summary of the invention

[0004] The purpose of the present invention is to provide a method, device and equipment for suppressing SBFET threshold voltage drift. By comparing the simulation test data of Schottky barrier field effect transistor interface traps and oxide layer traps with the measured data, the target traps that affect the SBFET threshold voltage drift are determined; the target traps are further charged to suppress the threshold voltage drift of the SBFET when the transfer characteristics test is performed, thereby solving the problem of threshold voltage drift when the transfer characteristics test of the SBFET is performed in the prior art.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a method for suppressing SBFET threshold voltage drift, which may include:

[0007] Obtain measured data of SBFET gate voltage and drain current transfer characteristics;

[0008] Acquire simulation test data of SBFET interface traps and oxide layer traps; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics;

[0009] Based on the simulation test data and the measured data, determining a target trap that affects a threshold voltage drift of a SBFET;

[0010] Determining a target charging voltage and a target charging duration of the target trap;

[0011] Based on the target charging voltage and the target charging time, the target trap is charged to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics.

[0012] Preferably, the step of obtaining the simulation test data of the SBFET interface traps and the oxide layer traps may include:

[0013] Setting uniformly distributed oxide layer traps in the oxide layer of the SBFET within the entire bandgap, performing a gate voltage and drain current transfer characteristic simulation test on the SBFET, and obtaining simulation test data of the oxide layer traps;

[0014] Uniformly distributed interface traps are set in the entire forbidden band range at the interface between the oxide layer and the semiconductor of the SBFET, and the gate voltage and drain current transfer characteristics of the SBFET are simulated and tested to obtain simulation test data of the interface traps.

[0015] Preferably, the step of setting uniformly distributed oxide layer traps in the oxide layer of the SBFET within the entire bandgap range, performing a gate voltage and drain current transfer characteristic simulation test on the SBFET, and obtaining simulation test data of the oxide layer traps may include:

[0016] Setting uniformly distributed oxide layer traps in the oxide layers of the plurality of SBFETs in the entire bandgap range to obtain a plurality of first SBFET test samples; the oxide layer traps of the plurality of first SBFET test samples have different charge densities;

[0017] A gate voltage and drain current transfer characteristic simulation test is performed on a plurality of the first SBFET test samples to obtain simulation test data of the oxide layer trap.

[0018] Preferably, the step of setting uniformly distributed interface traps in the entire bandgap range at the interface between the oxide layer and the semiconductor of the SBFET, performing a gate voltage and drain current transfer characteristic simulation test on the SBFET, and obtaining simulation test data of the interface traps may include:

[0019] Setting uniformly distributed interface traps in the entire bandgap range at the interface between the oxide layer and the semiconductor of the plurality of SBFETs to obtain a plurality of second SBFET test samples; the interface traps of the plurality of second SBFET test samples have different charge densities;

[0020] Performing gate voltage and drain current transfer characteristic simulation tests on a plurality of the second SBFET test samples to obtain simulation test data of donor interface traps and simulation test data of acceptor interface traps;

[0021] The simulation test data of the donor interface trap and the simulation test data of the acceptor interface trap are used as the simulation test data of the interface trap.

[0022] Preferably, determining the target trap that affects the SBFET threshold voltage drift based on the simulation test data and the measured data may include:

[0023] Comparing the simulation test data of the oxide layer trap with the measured data to obtain a first comparison result;

[0024] Comparing the simulated test data of the interface trap with the measured data to obtain a second comparison result;

[0025] Based on the first comparison result and the second comparison result, a target trap that affects the threshold voltage drift of the SBFET is obtained; the target trap is a slow interface trap among interface traps.

[0026] Preferably, determining the target charging voltage and target charging duration of the target trap may include:

[0027] Provide multiple SBFET charging test samples;

[0028] Determining a target charging voltage acting on the source and gate electrodes of the plurality of SBFETs based on the withstand voltage capabilities of the plurality of SBFET charging test samples;

[0029] Based on the target charging voltage and according to different charging durations, pre-charging the plurality of SBFET charging test samples respectively;

[0030] Repeatedly testing the gate voltage and drain current transfer characteristics of the plurality of SBFET charging test samples after pre-charging to obtain a plurality of target measured data;

[0031] Based on the multiple target measured data, multiple target charging test samples are obtained; the multiple target charging test samples are samples whose threshold voltage does not drift;

[0032] The charging time durations corresponding to the target charging test samples are sorted, and the shortest charging time duration is used as the target charging time duration of the SBFET target trap.

[0033] Preferably, the pre-charging of the plurality of SBFET charging test samples respectively according to different charging durations based on the target charging voltage may include:

[0034] Connecting the source and drain of the plurality of SBFET charging test samples to a voltage of -10V and the gate to a voltage of 0V;

[0035] According to different charging durations, the plurality of SBFET charging test samples are pre-charged respectively.

[0036] Preferably, charging the SBFET target well based on the target charging duration may then include:

[0037] According to a plurality of target cumulative radiation dose nodes, performing a radiation effect test on the charged SBFET to obtain radiation test data;

[0038] Based on the radiation test data, the drift amounts of the threshold voltage and the flat-band voltage of the charged SBFET are verified.

[0039] In a second aspect, the present invention provides a device for suppressing SBFET threshold voltage drift, which may include:

[0040] A first acquisition module, the first acquisition module is used to obtain measured data of SBFET gate voltage and drain current transfer characteristics;

[0041] A second acquisition module, the second acquisition module is used to acquire simulation test data of SBFET interface traps and oxide layer traps; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics;

[0042] A first determination module, the first determination module is used to determine a target trap that affects the SBFET threshold voltage drift based on the simulation test data and the measured data;

[0043] A second determination module, the second determination module is used to determine a target charging voltage and a target charging time of the SBFET target trap;

[0044] A charging module is used to charge the SBFET target trap based on the target charging voltage and the target charging time to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics.

[0045] In a third aspect, the present invention provides a device for suppressing SBFET threshold voltage drift, which may include a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the method for suppressing SBFET threshold voltage drift described in the first aspect is implemented when the processor executes the computer program.

[0046] Compared with the prior art, the present invention provides a method for suppressing SBFET threshold voltage drift, by obtaining measured data of SBFET gate voltage and drain current transfer characteristics, and obtaining simulation test data of SBFET interface traps and oxide layer traps; wherein the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics; based on the simulation test data and the measured data, determining the target trap that affects the SBFET threshold voltage drift; determining the target charging voltage and target charging time of the target trap; charging the target trap according to the target charging voltage and target charging time to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics; based on this, under the bias condition of charging the target trap, the energy band at the interface between silicon and the oxide layer is bent downward, and the charge of the target trap is increased, thereby achieving effective suppression of the threshold voltage drift when the SBFET is repeatedly tested for transfer characteristics; testing and verification show that the threshold voltage drift of the SBFET after charging is effectively suppressed when the transfer characteristics test is repeatedly performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0048] Figure 1a A top view of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0049] Figure 1b is a cross-sectional view of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0050] Figure 2a A schematic diagram of transfer characteristic drift caused by repeated transfer characteristic tests of SBFET in the prior art;

[0051] Figure 2b A schematic diagram of a change curve of a positive gate voltage current turn-on voltage drift and a negative gate voltage current turn-on voltage drift of an SBFET in the prior art;

[0052] Figure 3 A schematic diagram of the main process of a method for suppressing SBFET threshold voltage drift provided by the present invention;

[0053] Figure 4 A schematic diagram of a transfer characteristic curve simulation result of setting uniformly distributed oxide layer traps in the oxide layer of the SBFET within the entire forbidden band in the method for suppressing the threshold voltage drift of the SBFET provided by the present invention;

[0054] Figure 5A schematic diagram of the simulation results of the transfer characteristic curve of setting uniformly distributed interface traps in the entire forbidden band range at the interface between the oxide layer and the semiconductor of the SBFET in the method for suppressing the threshold voltage drift of the SBFET provided by the present invention;

[0055] Figure 6 A schematic diagram of simulation results of gradual accumulation of acceptor trap charges during a forward gate voltage scanning process in the method for suppressing SBFET threshold voltage drift provided by the present invention;

[0056] Figure 7 A schematic diagram of simulation results of gradual accumulation of donor trap charge during a negative gate voltage scanning process in the method for suppressing SBFET threshold voltage drift provided by the present invention;

[0057] Figure 8 A schematic diagram of the simulation results of the energy band ranges of the donor interface trap and the acceptor interface trap in the method for suppressing the SBFET threshold voltage drift provided by the present invention;

[0058] Fig. 9 A schematic diagram of simulation results of transfer characteristic curves corresponding to acceptor interface traps uniformly distributed at the center points of the forbidden bands at the same energy level range width and different energy level range widths in the method for suppressing SBFET threshold voltage drift provided by the present invention;

[0059] Fig.10 A schematic diagram of the threshold voltage drift results after repeated transfer characteristic tests are performed on samples with different charging time lengths in the method for suppressing SBFET threshold voltage drift provided by the present invention;

[0060] Fig.11 A schematic diagram of the irradiation test results of the method for suppressing SBFET threshold voltage drift provided by the present invention;

[0061] Fig.12 Schematic diagram of the irradiation experimental results of the SBFET in the SB-TG state without slow interface state charging before irradiation;

[0062] Fig.13 A schematic diagram of the structure of a device for suppressing SBFET threshold voltage drift provided by the present invention;

[0063] Fig.14 A schematic diagram of the structure of a device for suppressing SBFET threshold voltage drift provided by the present invention.

[0064] Reference numerals: 1 - source, 2 - drain, 3 - silicon island, 4 - substrate, 5 - oxide layer, 6 - gate. DETAILED DESCRIPTION

[0065] In order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their order of precedence. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit them to be different.

[0066] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0067] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the previous time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0068] First, some English abbreviations involved in the present invention are explained as follows:

[0069]

[0070] In the prior art, it is often believed that a Schottky junction is formed when metal and semiconductor come into contact. Figure 1a to Figure 1b , Figure 1a A top view of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0071] Figure 1b is a cross-sectional view of a Schottky barrier field effect transistor (SBFET) in the prior art; wherein, Figure 1b The graph shown is Figure 1a Cross-sectional view at the dotted line. Figure 1a to Figure 1bIn order to use the TCAD simulation model to simulate the Schottky barrier field effect transistor, the internal structure of the Schottky barrier field effect transistor can be obtained, and then the simulation test can be performed, which is helpful to improve the design optimization of the Schottky barrier field effect transistor. Figure 1a The black dotted area on the white background on the left is the drain 2, the black dotted area on the white background on the right is the source 1, and the black square area in the middle is the silicon island 3; Figure 1b The black stripe region at the bottom is the gate 6 , the upper surface of the gate 6 is deposited with the substrate 4 , and the upper surface of the substrate 4 is deposited with the oxide layer 5 .

[0072] In the actual test process, the SBFET structure is repeatedly tested for transfer characteristics, and the following results can be obtained: Figure 2a to Figure 2b See the test results shown. Figure 2a to Figure 2b , Figure 2a A schematic diagram of transfer characteristic drift caused by repeated transfer characteristic tests of SBFET in the prior art; Figure 2b Schematic diagram of the change curve of the positive gate voltage current turn-on voltage drift and the negative gate voltage current turn-on voltage drift of the SBFET in the prior art. Figure 2a In the figure, the negative gate voltage transfer characteristic curve in illustration (1) has no regular drift, and the right half transfer characteristic curve in illustration (2) has regular positive drift. Figure 2a The content shown in the figure shows that SBFET has good current regulation capability at both positive and negative gate voltages. The threshold voltage and flat band voltage of SBFET are extracted by the Y-function method. Repeated testing will result in the current turn-on threshold voltage (V th ) drifts forward regularly, and the drift reaches saturation at about 0.3V. However, the left current turn-on voltage, i.e., the flat band voltage (V fb ) There is no regular unidirectional drift.

[0073] By sorting out the test results of multiple groups of SBFET devices, similar problems are found, such as Figure 2b Therefore, we believe that repeated testing of SBFET will only result in the current turn-on voltage (threshold voltage V th ) drift, and cannot cause the current turn-on voltage (flat band voltage V fb ) of the unidirectional drift.

[0074] In view of this, the present invention provides a method, device and apparatus for suppressing SBFET threshold voltage drift, so as to solve the problem of threshold voltage drift when performing transfer characteristic test on SBFET in the prior art.

[0075] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:

[0076] In a first aspect, the present invention provides a method for suppressing SBFET threshold voltage drift; see Figure 3 , Figure 3 A schematic diagram of the main process of a method for suppressing SBFET threshold voltage drift provided by the present invention; the execution subject is a server or terminal device equipped with the technical solution disclosed in the embodiment of the present invention, such as a service platform or a handheld device, etc.

[0077] exist Figure 3 The methods may include:

[0078] Step 310: Obtain measured data of the SBFET gate voltage and drain current transfer characteristics.

[0079] Step 320: Acquire simulation test data of SBFET interface traps and oxide layer traps; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics.

[0080] Step 330: Determine a target trap that affects the SBFET threshold voltage drift based on the simulation test data and the measured data.

[0081] In step 310 to step 330, firstly, the measured data of the gate voltage and drain current transfer characteristics of the SBFET in the actual test process are obtained; further, simulation test data consistent with the size of the measured sample is obtained, and the simulation test data respectively includes the simulation test data of the interface trap and the oxide layer trap; the simulation test data and the measured data are compared and analyzed to determine the target trap of the SBFET threshold voltage drift; the target trap is determined by analysis to be a slow interface trap in the interface trap. It can be understood that the measured data and simulation test data obtained in step 310 and step 320 are respectively the measured data obtained after actual testing of multiple SBFET test pieces with the same size parameters, and the simulation test data obtained after simulation testing of multiple SBFET simulation test pieces with the same size parameters as in the actual measurement process.

[0082] Step 340: Determine a target charging voltage and a target charging duration of the target trap.

[0083] Step 350: Based on the target charging voltage and the target charging time, the target trap is charged to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics.

[0084] In step 340 to step 350, first, it is necessary to determine the bias voltage for charging the target trap. The conventional charging method is to connect the source (Source) and drain (Drain) electrodes to a voltage of -10V and the gate to a voltage of 0V. Under this bias condition, the energy band at the interface between silicon and the oxide layer bends downward, which will increase the charge of the interface donor trap, that is, charging the acceptor interface trap; it is further necessary to determine the target charging time to determine how long it takes to suppress the drift of the threshold voltage under the action of the target charging voltage, and obtain the target charging time after verification; finally, based on the target charging voltage and the target charging time, the target trap is charged, and after the charging is completed, the SBFET will not experience threshold voltage drift during repeated tests of the gate voltage and drain current transfer characteristics.

[0085] Based on this, the present invention provides a method for suppressing SBFET threshold voltage drift, by obtaining measured data of SBFET gate voltage and drain current transfer characteristics, and simulation test data of SBFET interface traps and oxide layer traps; based on the simulation test data and the measured data, the target trap that affects the SBFET threshold voltage drift is determined; the target charging voltage and target charging time of the target trap are further determined; finally, based on the target charging voltage and the target charging time, the target trap is charged to suppress the drift of the threshold voltage when the SBFET is subjected to a transfer characteristic test; based on this, the threshold voltage drift is effectively suppressed when the SBFET is repeatedly subjected to a transfer characteristic test, the problem of threshold voltage drift when the SBFET is subjected to a transfer characteristic test in the prior art is solved, and the influence on the SBFET radiation test is avoided.

[0086] In practical applications, in order to achieve the above purpose, we conducted a detailed analysis of the drift caused by repeated tests, and combined with the simulation results to obtain the source of the drift introduced by the test, and found that the threshold voltage drift caused by repeated tests originated from the slow interface state traps at the SOI / BOX interface. Finally, based on the combination of simulation and actual measurement, a test scheme for charging the slow interface traps was obtained, which can effectively suppress the drift of the threshold voltage during the transfer characteristic test of SBFET, and can effectively eliminate the influence of the slow interface state before irradiation. The test results after irradiation are only the negative drift of the threshold voltage and flat band voltage caused by irradiation.

[0087] Preferably, before step 320, that is, obtaining simulation test data of SBFET interface traps and oxide layer traps, the process may include: setting uniformly distributed oxide layer traps in the oxide layer of the SBFET within the entire bandgap range, performing gate voltage and drain current transfer characteristic simulation tests on the SBFET, and obtaining simulation test data of oxide layer traps; setting uniformly distributed interface traps in the oxide layer and semiconductor interface of the SBFET within the entire bandgap range, performing gate voltage and drain current transfer characteristic simulation tests on the SBFET, and obtaining simulation test data of interface traps.

[0088] Preferably, uniformly distributed oxide layer traps are set in the oxide layer of the SBFET within the entire bandgap range, and the gate voltage and drain current transfer characteristics of the SBFET are simulated and tested to obtain simulation test data of the oxide layer traps, which may include: uniformly distributed oxide layer traps are set in the oxide layers of multiple SBFETs within the entire bandgap range to obtain multiple first SBFET test samples; the oxide layer traps of the multiple first SBFET test samples have different charge densities; and gate voltage and drain current transfer characteristics are simulated and tested to obtain simulation test data of the oxide layer traps.

[0089] Preferably, uniformly distributed interface traps are set in the entire bandgap range at the interface between the oxide layer and the semiconductor of the SBFET, and the gate voltage and drain current transfer characteristics of the SBFET are simulated and tested to obtain simulation test data of the interface traps, which may include: uniformly distributed interface traps are set in the entire bandgap range at the interface between the oxide layer and the semiconductor of multiple SBFETs to obtain multiple second SBFET test samples; the interface traps of the multiple second SBFET test samples have different charge densities; the gate voltage and drain current transfer characteristics of the multiple second SBFET test samples are simulated and tested to obtain simulation test data of donor interface traps and simulation test data of acceptor interface traps; the simulation test data of the donor interface traps and the simulation test data of the acceptor interface traps are used as simulation test data of the interface traps.

[0090] It should be noted that interface traps can include donor interface traps and acceptor interface traps, and acceptor interface traps can include slow interface traps or deep energy level traps. When two types of interface traps are uniformly distributed in the entire bandgap width, the donor interface trap will gradually accumulate positive trap charges due to the change of gate voltage from 0V to negative, and the acceptor interface trap will gradually accumulate negative trap charges due to the change of gate voltage from 0V to positive; based on this, the simulation test data of interface traps are obtained; the donor interface trap can be referred to as the donor trap, and the acceptor interface trap can be referred to as the acceptor trap.

[0091] Preferably, in step 330, based on the simulation test data and the measured data, determining the target trap that affects the SBFET threshold voltage drift can include: comparing the simulation test data of the oxide layer trap with the measured data to obtain a first comparison result; comparing the simulation test data of the interface trap with the measured data to obtain a second comparison result; based on the first comparison result and the second comparison result, obtaining the target trap that affects the SBFET threshold voltage drift; the target trap is a slow interface trap among the interface traps.

[0092] As an example, see Figure 4 , Figure 4 A schematic diagram of a transfer characteristic curve simulation result of setting uniformly distributed oxide layer traps in the oxide layer of the SBFET within the entire forbidden band in the method for suppressing the threshold voltage drift of the SBFET provided by the present invention; Figure 4 In the figure, the horizontal axis represents the gate voltage in V, and the vertical axis represents the drain current in A. The oxide layer trap charge density (D ox ) are 0cm -3 , and 1*10 18 cm -3 The corresponding transfer characteristic curve simulation results. The oxide layer trap charge density is 0 cm -3 The corresponding transfer characteristic curve simulation results are as follows: The oxide layer trap charge density is 1*10 18 cm -3 When the oxide trap charge is set, it is found that the positive and negative gate voltage transfer characteristic curves shift as a whole, corresponding to the same degree of drift in the threshold voltage and the flat band voltage, which is inconsistent with the test results in Figure 2(a); therefore, it is judged that the oxide trap is not a factor affecting the threshold voltage drift.

[0093] For further information, see Figures 5 to 9 , Figure 5 A schematic diagram of the simulation results of the transfer characteristic curve of setting uniformly distributed interface traps in the entire forbidden band range at the interface between the oxide layer and the semiconductor of the SBFET in the method for suppressing the threshold voltage drift of the SBFET provided by the present invention; Figure 6 A schematic diagram of simulation results of gradual accumulation of acceptor trap charges during a forward gate voltage scanning process in the method for suppressing SBFET threshold voltage drift provided by the present invention; Figure 7 A schematic diagram of simulation results of gradual accumulation of donor trap charge during a negative gate voltage scanning process in the method for suppressing SBFET threshold voltage drift provided by the present invention; Figure 8 A schematic diagram of the simulation results of the energy band ranges of the donor interface trap and the acceptor interface trap in the method for suppressing the SBFET threshold voltage drift provided by the present invention;

[0094] Fig. 9 A schematic diagram of the simulation results of transfer characteristic curves corresponding to acceptor interface traps uniformly distributed at the center points of the forbidden bands in the same energy level range width and different energy level range widths in the method for suppressing SBFET threshold voltage drift provided by the present invention.

[0095] exist Figure 5 In the figure, the horizontal axis represents the gate voltage in V, and the vertical axis represents the drain current in A. The oxide layer trap charge density (D ox ) are 0cm -2 .eV -1 , and 1*10 13 cm -2 .eV -1 The corresponding transfer characteristic curve simulation results. The oxide layer trap charge density is 0 cm -2 .eV -1 The corresponding transfer characteristic curve simulation results are as follows: The oxide layer trap charge density is 1*10 13 cm -2 .eV -1 The simulation results of the transfer characteristic curve corresponding to the time; the two curves on the left side of the figure, that is, the two curves corresponding to the negative gate voltage, are the influence of the donor trap on the transfer characteristics, and the two curves on the right side of the figure, that is, the two curves corresponding to the positive gate voltage, are the influence of the acceptor trap on the transfer characteristics.

[0096] exist Figure 7 In the figure, the horizontal axis represents the gate voltage in V, and the vertical axis represents the acceptor trap charge density in 1*10 11 cm -2 ;exist Figure 8 In the figure, the horizontal axis represents the gate voltage in V, and the vertical axis represents the donor trap charge density in 1*10 11 cm -2 .

[0097] Combination Figure 5 and Figure 6 The curve shown can be obtained: Figure 5 The figure shows the case where two types of interface traps in the main interface traps are set to be uniformly distributed in the entire bandgap width, namely, donor traps and acceptor traps in the main interface traps; Figure 6 It is shown that the donor interface trap will gradually accumulate positive trap charge as the gate voltage changes from 0V to negative, which will lead to Figure 5 Each point in the left half of the transfer characteristic curve shown in the figure has a drifting trend compared to the previous point; that is, when the gate voltage is negative, the corresponding current curve eventually leads to the current turn-on voltage (flat band voltage V fb) also leads to an increase in the subthreshold slope SS.

[0098] Combination Figure 5 and Figure 7 The curve shown can be obtained: Figure 7 It is shown that the acceptor interface trap will gradually accumulate negative trap charge as the gate voltage changes from 0V to positive; this will lead to Figure 5 Each point in the right half of the transfer characteristic curve shown in the figure has a drifting trend compared to the previous point, that is, the current curve with positive gate voltage, which eventually leads to the current turn-on voltage (threshold voltage V th ) also leads to an increase in the subthreshold slope SS.

[0099] In the actual test results, only the threshold voltage drifts, which means that the threshold voltage drifts but the flat band voltage does not drift, which can only be caused by the acceptor type interface trap charge, but the change of the subthreshold slope SS is not desirable. Further, it can be obtained from the gradual increase of the gate voltage with the uniformly distributed trap charge in the bandgap: by limiting the interface trap energy level range in the bandgap width, only the variable acceptor interface traps near 0 gate voltage are introduced, so that the energy band distribution can be obtained as follows Figure 8 The graphic shown.

[0100] from Figure 8 The content shown is the donor and acceptor trap energy band range, where E i is the Fermi level of the semiconductor, E C is the bottom of the conduction band, E V At the top of the valence band, donor traps are often positively charged, while acceptor traps are often negatively charged.

[0101] For further information, please refer to Fig. 9 ,exist Fig. 9 In the graph, the horizontal axis represents the gate voltage in V, and the vertical axis represents the drain current in A. The curve represents the transfer characteristic curve between the simulated drain current and the gate voltage corresponding to the interface trap density of 0.0±0.05eV; The curve represents the transfer characteristic curve between the simulated drain current and the gate voltage corresponding to the interface trap density of 0.1±0.05eV; The curve represents the transfer characteristic curve between the simulated drain current and the gate voltage corresponding to the interface trap density of 0.2±0.05eV; The transfer characteristic curve between the simulated drain current and the gate voltage corresponding to the interface trap density of 0.3±0.05eV; Curve The transfer characteristic curve between the simulated drain current and the gate voltage corresponding to the interface trap density of 0.4±0.05eV; The curve represents the transfer characteristic curve between the simulated drain current and the gate voltage corresponding to the interface trap density of 0.5±0.05eV; The transfer characteristic curve between the simulated drain current and the gate voltage corresponding to the interface trap density of 0.5±0.05 eV is shown.

[0102] pass Fig. 9 From the content shown, we can get: after setting the acceptor-type interface traps with the same trap energy level range (plus or minus 0.05 eV) and different energy level center points and the same trap density, multiple transfer characteristic curves were obtained through simulation. It was found that when the trap energy level range is near the intrinsic Fermi level, the trap will only cause the off-state current to be widened before the current is turned on. The overall effect is that the on-state current is positively shifted compared to the case of 0 trap density, and the subsequent current curve is basically parallel to the curve when there is no interface trap; this is consistent with the actual test results of the transistor, and the closer the trap energy level is to the intrinsic Fermi level, the longer the time constant of the trap to capture and release carriers, so this part of the trap is a slow interface trap, also called a deep energy level trap (traps far from the conduction band or valence band are called deep energy level traps).

[0103] Based on this, it can be determined that the main reason affecting the threshold voltage drift of SBFET is due to the change of current in the slow interface trap in the interface trap, so we determine the target trap for optimization as the slow interface trap in the interface trap.

[0104] After determining the specific reasons that affect the threshold voltage drift caused by repeated testing of SBFET, a method of charging the slow interface traps is further adopted, which can solve the problem of threshold voltage drift caused by repeated testing of SBFET.

[0105] Preferably, in step 340, determining the target charging voltage and target charging time of the target trap may include: providing multiple SBFET charging test samples; determining the target charging voltage acting on the source and gate of multiple SBFETs based on the voltage withstand capabilities of the multiple SBFET charging test samples; pre-charging the multiple SBFET charging test samples according to different charging times based on the target charging voltage; repeatedly testing the gate voltage and drain current transfer characteristics of the multiple SBFET charging test samples after pre-charging to obtain multiple target measured data; obtaining multiple target charging test samples based on the multiple target measured data; the multiple target charging test samples are samples whose threshold voltage has not drifted; sorting the charging time corresponding to the multiple target charging test samples, and taking the shortest charging time as the target charging time of the SBFET target trap.

[0106] Preferably, in step 340, based on the target charging voltage, multiple SBFET charging test samples are pre-charged according to different charging times, which can include: connecting the source and drain of the multiple SBFET charging test samples to a -10V voltage and the gate to a 0V voltage respectively; pre-charging the multiple SBFET charging test samples according to different charging times.

[0107] It should be noted that for transistors with different voltage resistance levels, the target charging voltage and target charging time may be different, and the specific charging voltage and charging time can be tested and verified by the simulation method provided by the present invention; in this scheme, the charging voltage is determined when the SBFET is in the transmission tube state, that is, the state with the largest drift.

[0108] As an example, the source and drain electrodes of the SBFET can be connected to -10V, and the gate to 0V. Under this bias condition, the energy band at the interface between silicon and oxide layer bends downward, which will increase the charge of the interface donor trap, that is, charge the acceptor interface traps of multiple target charge test samples. Fig.10 , Fig.10 A schematic diagram of the threshold voltage drift results after repeated transfer characteristic tests on samples with different charging times in the method for suppressing SBFET threshold voltage drift provided by the present invention.

[0109] exist Fig.10 Middle, curve The threshold voltage drift curve of the sample with a charging time of 10s after repeated transfer characteristic test; The threshold voltage drift curve of the sample with a charging time of 30s after repeated transfer characteristic test; The threshold voltage drift curve of the sample with a charging time of 90s after repeated transfer characteristic test; The curve represents the threshold voltage drift curve after repeated transfer characteristic test of the sample with a charging time of 2 minutes; The curve represents the threshold voltage drift curve after repeated transfer characteristic test of the sample with a charging time of 3 minutes; The curve represents the threshold voltage drift curve after repeated transfer characteristic test of the sample with a charging time of 4 minutes; It shows the threshold voltage drift curve after repeated transfer characteristic test of the sample with a charging time of 10 minutes.

[0110] from Fig.10It can be obtained that after processing multiple groups of SBFET devices with different charging times, when the charging time is greater than or equal to 4 minutes, it can be ensured that multiple repeated electrical tests after charging will not cause the threshold voltage to continue to drift. Therefore, the target charging time can be set to be greater than or equal to 4 minutes.

[0111] Based on this, the source and drain of the SBFET charging test sample can be connected to a -10V voltage and the gate to a 0V voltage respectively, and the charging time is greater than or equal to 4 minutes, so as to charge the target traps of the SBFET respectively, thereby suppressing the drift of the threshold voltage when the SBFET is subjected to the transfer characteristic test.

[0112] Further, in order to verify the effectiveness of a method for suppressing SBFET threshold voltage drift provided by the present solution, preferably, after step 350, that is, based on the target charging time, the SBFET target trap is charged, which may then include: performing an irradiation effect test on the charged SBFET according to multiple target cumulative irradiation dose nodes to obtain irradiation test data; based on the irradiation test data, verifying the drift of the threshold voltage and flat-band voltage of the charged SBFET.

[0113] Specifically, according to the SBFET bias states shown in Table 1, the radiation effect test of the SBFET under different bias states is performed.

[0114] Table 1 shows the bias state of SBFET during the irradiation experiment

[0115]

[0116] It should be noted that, during the irradiation test, the position where the voltage is applied corresponds to the position of the Schottky barrier field effect transistor shown in FIG. 1 .

[0117] Preferably, the cumulative dose nodes during the irradiation process are 0, 100, 300, and 500 rad(Si), and the dose rate is 200 rad(Si) / s. The threshold voltage and flat band voltage extraction results before and after irradiation are as follows: Fig.11 As shown, Fig.11 A schematic diagram of irradiation test results of the method for suppressing SBFET threshold voltage drift provided by the present invention.

[0118] exist Fig.11 The left half (a) shows the positive gate voltage (V) caused by connecting the SBFET to different bias states (Table 1) during irradiation. g ) Current turn-on voltage drift, that is, threshold voltage V th The amount of drift; Fig.11 The right half (b) shows the negative gate voltage (V) caused by connecting the SBFET to different bias states (Table 1) during irradiation.g ) Current turn-on voltage drift, that is, flat band voltage V fb By comparison, we found that the bias state of the SB-TG state will cause the threshold voltage and flat-band voltage of the SBFET to drift in a single direction with the largest amplitude. We define this bias as the worst bias of the SBFET structure.

[0119] Further, we conducted SB-TG state irradiation experiments on another group of samples that were slow interface state charged using the method for suppressing SBFET threshold voltage drift provided by the present invention. The experimental results are as follows: Fig.12 As shown, Fig.12 Schematic diagram of the irradiation experimental results of SBFET in SB-TG state without slow interface state charging before irradiation.

[0120] pass Fig.12 It can be found that at the 100krad (Si) node, the threshold voltage first drifted positively, and then the subsequent metering node drifted negatively. The positive drift of the 100krad (Si) node is the result of the negative drift introduced by the weaker radiation effect being masked by the positive drift caused by the charging of the acceptor type slow interface state caused by electrical testing when the radiation effect is not obvious.

[0121] Based on this, through Fig.11 and Fig.12 The results shown clearly show that the method for suppressing SBFET threshold voltage drift provided by the present invention can effectively suppress the problem of voltage drift in the process of repeatedly testing the gate voltage and drain current transfer characteristics of SBFET before irradiation, and will not bring any impact on the irradiation test.

[0122] In a second aspect, the present invention provides a device for suppressing SBFET threshold voltage drift, please refer to Fig.13 , Fig.13 A schematic diagram of the structure of a device for suppressing SBFET threshold voltage drift provided by the present invention.

[0123] exist Fig.13 In the embodiment, the device may include:

[0124] The first acquisition module 1310 is used to acquire measured data of the gate voltage and drain current transfer characteristics of the SBFET.

[0125] The second acquisition module 1320 is used to acquire simulation test data of SBFET interface traps and oxide layer traps; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics.

[0126] The first determination module 1330 is used to determine a target trap that affects the SBFET threshold voltage drift based on the simulation test data and the measured data.

[0127] The second determination module 1340 is used to determine the target charging voltage and target charging time of the SBFET target well.

[0128] The charging module 1350 is used to charge the SBFET target trap based on the target charging voltage and the target charging time to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics.

[0129] Based on this, the present invention provides a device for suppressing SBFET threshold voltage drift, which obtains measured data of SBFET gate voltage and drain current transfer characteristics through a first acquisition module 1310; further uses a second acquisition module 1320 to obtain simulation test data of SBFET interface traps and oxide layer traps, wherein the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics; then uses a first determination module 1330 to determine a target trap that affects SBFET threshold voltage drift based on the simulation test data and the measured data, and uses a second determination module 1340 to determine a target charging voltage and a target charging time of the SBFET target trap; finally, based on a charging module 1350, the SBFET target trap is charged based on the target charging voltage and the target charging time to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics; the effective suppression of the threshold voltage drift when the SBFET is repeatedly tested for transfer characteristics is achieved; the test verifies that the threshold voltage drift of the SBFET after charging is completed when the transfer characteristics test is repeatedly performed is effectively suppressed; and the influence on the SBFET irradiation test is avoided.

[0130] In a third aspect, the present invention provides a device for suppressing SBFET threshold voltage drift, see Fig.14 , Fig.14 A schematic diagram of the structure of a device for suppressing SBFET threshold voltage drift provided by the present invention.

[0131] exist Fig.14 In the embodiment, the device 1400 includes a memory 1420, a processor, and a computer program stored in the memory 1420 and executable on the processor. When the processor executes the computer program, the method for suppressing the threshold voltage drift of the SBFET described in the first aspect is implemented.

[0132] Specifically, in Fig.14In the figure, device 1400 is a hardware structure of a simulation device of SBFET provided by the present invention. The device 1400 may include a memory 1420, a first processor 1410, a second processor 1450, and a computer program stored in the memory 1420 and executable on the first processor 1410 and / or the second processor 1450. When the first processor 1410 and / or the second processor 1450 executes the computer program, the simulation method of SBFET described in the first aspect is implemented.

[0133] Optionally, the device 1400 may include a communication interface 1430. There may be one or more communication interfaces 1430. The communication interface 1430 may use any transceiver or other device for communicating with other devices or communication networks.

[0134] Optionally, the device 1400 may further include a communication line 1440. The communication line 1440 may include a path for transmitting information between the above components.

[0135] It should be noted that the memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor through a communication line. The memory may also be integrated with the processor.

[0136] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0137] In a specific implementation, as an example, Fig.14 As shown, the first processor 1410 and the second processor 1450 may include one or more CPUs, such as Fig.14 CPU0 and CPU1 in.

[0138] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0139] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A method for suppressing SBFET threshold voltage drift, characterized in that: include: Obtain measured data of SBFET gate voltage and drain current transfer characteristics; Obtain simulation test data of SBFET interface traps and oxide layer traps; The simulation test data includes simulation test data of gate voltage and drain current transfer characteristics; Based on the simulation test data and the measured data, determining a target trap that affects a threshold voltage drift of a SBFET; Determining a target charging voltage and a target charging duration of the target trap; Based on the target charging voltage and the target charging time, the target trap is charged to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics.

2. The method according to claim 1, characterized in that The acquisition of simulation test data of SBFET interface traps and oxide layer traps previously includes: Setting uniformly distributed oxide layer traps in the oxide layer of the SBFET within the entire bandgap, performing a gate voltage and drain current transfer characteristic simulation test on the SBFET, and obtaining simulation test data of the oxide layer traps; Uniformly distributed interface traps are set in the entire forbidden band range at the interface between the oxide layer and the semiconductor of the SBFET, and the gate voltage and drain current transfer characteristics of the SBFET are simulated and tested to obtain simulation test data of the interface traps.

3. The method according to claim 2, characterized in that The step of setting uniformly distributed oxide layer traps in the oxide layer of the SBFET within the entire bandgap range, performing a gate voltage and drain current transfer characteristic simulation test on the SBFET, and obtaining simulation test data of the oxide layer traps includes: Setting uniformly distributed oxide layer traps in the oxide layers of the plurality of SBFETs in the entire bandgap range to obtain a plurality of first SBFET test samples; the oxide layer traps of the plurality of first SBFET test samples have different charge densities; A gate voltage and drain current transfer characteristic simulation test is performed on a plurality of the first SBFET test samples to obtain simulation test data of the oxide layer trap.

4. The method according to claim 2, characterized in that The method comprises setting uniformly distributed interface traps in the entire forbidden band range at the interface between the oxide layer and the semiconductor of the SBFET, performing a gate voltage and drain current transfer characteristic simulation test on the SBFET, and obtaining simulation test data of the interface traps, including: Setting uniformly distributed interface traps in the entire bandgap range at the interface between the oxide layer and the semiconductor of the plurality of SBFETs to obtain a plurality of second SBFET test samples; the interface traps of the plurality of second SBFET test samples have different charge densities; Performing gate voltage and drain current transfer characteristic simulation tests on a plurality of the second SBFET test samples to obtain simulation test data of donor interface traps and simulation test data of acceptor interface traps; The simulation test data of the donor interface trap and the simulation test data of the acceptor interface trap are used as the simulation test data of the interface trap.

5. The method according to claim 2, characterized in that Based on the simulation test data and the measured data, a target trap that affects the SBFET threshold voltage drift is determined, including: Comparing the simulation test data of the oxide layer trap with the measured data to obtain a first comparison result; Comparing the simulated test data of the interface trap with the measured data to obtain a second comparison result; Based on the first comparison result and the second comparison result, a target trap that affects the threshold voltage drift of the SBFET is obtained; the target trap is a slow interface trap among interface traps.

6. The method according to claim 1, characterized in that The determining of the target charging voltage and the target charging duration of the target trap includes: Provide multiple SBFET charging test samples; Determining a target charging voltage acting on the source and gate electrodes of the plurality of SBFETs based on the withstand voltage capabilities of the plurality of SBFET charging test samples; Based on the target charging voltage and according to different charging durations, pre-charging the plurality of SBFET charging test samples respectively; Repeatedly testing the gate voltage and drain current transfer characteristics of the plurality of SBFET charging test samples after pre-charging to obtain a plurality of target measured data; Based on the multiple target measured data, multiple target charging test samples are obtained; the multiple target charging test samples are samples whose threshold voltage does not drift; The charging time durations corresponding to the target charging test samples are sorted, and the shortest charging time duration is used as the target charging time duration of the SBFET target trap.

7. The method according to claim 6, characterized in that The pre-charging of the plurality of SBFET charging test samples respectively according to different charging durations based on the target charging voltage includes: Connecting the source and drain of the plurality of SBFET charging test samples to a voltage of -10V and the gate to a voltage of 0V; According to different charging durations, the plurality of SBFET charging test samples are pre-charged respectively.

8. The method according to claim 1, characterized in that The step of charging the SBFET target well based on the target charging duration may then include: According to a plurality of target cumulative radiation dose nodes, performing a radiation effect test on the charged SBFET to obtain radiation test data; Based on the radiation test data, the drift amounts of the threshold voltage and the flat-band voltage of the charged SBFET are verified.

9. A device for suppressing SBFET threshold voltage drift, characterized in that: include: A first acquisition module, the first acquisition module is used to obtain measured data of SBFET gate voltage and drain current transfer characteristics; A second acquisition module, the second acquisition module is used to acquire simulation test data of SBFET interface traps and oxide layer traps; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics; A first determination module, the first determination module is used to determine a target trap that affects the SBFET threshold voltage drift based on the simulation test data and the measured data; A second determination module, the second determination module is used to determine a target charging voltage and a target charging time of the SBFET target trap; A charging module is used to charge the SBFET target trap based on the target charging voltage and the target charging time to suppress the drift of the threshold voltage when the SBFET is tested for transfer characteristics.

10. A device for suppressing SBFET threshold voltage drift, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the method for suppressing SBFET threshold voltage drift as claimed in any one of claims 1 to 8 is implemented when the processor executes the computer program.

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