A method, apparatus and device for suppressing threshold voltage drift of an SBFET

Abstract

The application discloses a method, device and equipment for inhibiting threshold voltage drift of SBFET, and relates to the technical field of semiconductors, to solve the problem of threshold voltage drift when the SBFET is tested for transfer characteristics in the prior art. The method comprises the following steps: acquiring measured data of the gate voltage and the drain current transfer characteristics of the SBFET, and acquiring simulation test data of the interface traps and the oxide layer traps of the SBFET; the simulation test data comprises simulation test data of the gate voltage and the drain current transfer characteristics; based on the simulation test data and the measured data, a target trap affecting the threshold voltage drift of the SBFET is determined; the target charging voltage and the target charging duration of the target trap are further determined; finally, the target trap is charged based on the target charging voltage and the target charging duration, so as to inhibit the threshold voltage drift when the SBFET is tested for transfer characteristics; based on this, the effective inhibition of the threshold voltage drift when the SBFET is repeatedly tested for transfer characteristics is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Schottky barrier diode, and particularly to a method, device and equipment for suppressing threshold voltage drift of SBFET. BACKGROUND

[0002] During repeated transfer characteristic curve testing of SBFET (Schottky barrier field effect transistor) structure, a one-way threshold voltage drift occurs, which is a great interference to threshold voltage drift after irradiation. If this interference cannot be solved before irradiation experiment, it will have a great impact on total dose effect research of SBFET device.

[0003] Therefore, a technical solution for suppressing threshold voltage drift of SBFET is urgently needed to solve the problem of threshold voltage drift during transfer characteristic testing of Schottky barrier field effect transistor in the prior art. SUMMARY

[0004] The present application aims to provide a method, device and equipment for suppressing threshold voltage drift of SBFET, which compares simulation test data of interface traps and oxide layer traps of Schottky barrier field effect transistor with actual measurement data to determine target traps affecting threshold voltage drift of SBFET, and further charges the target traps to suppress threshold voltage drift of SBFET during transfer characteristic testing, thereby solving the problem of threshold voltage drift during transfer characteristic testing of SBFET in the prior art.

[0005] To achieve the above-mentioned purpose, the present application provides the following technical solution:

[0006] In a first aspect, the present application provides a method for suppressing threshold voltage drift of SBFET, which can include:

[0007] Obtaining actual measurement data of gate voltage and drain current transfer characteristics of SBFET;

[0008] Obtaining simulation test data of interface traps and oxide layer traps of SBFET; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics;

[0009] Based on the simulation test data and the actual measurement data, determining target traps affecting threshold voltage drift of SBFET;

[0010] Determining target charging voltage and target charging duration of the target traps;

[0011] Based on the target charging voltage and the target charging duration, charging the target traps to suppress threshold voltage drift of SBFET during transfer characteristic testing.

[0012] Preferably, the simulation test data of the SBFET interface traps and the oxide layer traps can include:

[0013] The oxide layer traps in the oxide layer of the SBFET are uniformly distributed in the entire band gap range, and the gate voltage and drain current transfer characteristics of the SBFET are simulated and tested to obtain the simulation test data of the oxide layer traps.

[0014] The interface traps in the oxide layer and the semiconductor interface of the SBFET are uniformly distributed in the entire band gap range, and the gate voltage and drain current transfer characteristics of the SBFET are simulated and tested to obtain the simulation test data of the interface traps.

[0015] Preferably, the simulation test data of the SBFET interface traps and the oxide layer traps can include:

[0016] A plurality of oxide layer traps in the oxide layer of the SBFET are uniformly distributed in the entire band gap range to obtain a plurality of first SBFET test samples; the oxide layer traps of the plurality of first SBFET test samples have different charge densities.

[0017] The gate voltage and drain current transfer characteristics of the plurality of first SBFET test samples are simulated and tested to obtain the simulation test data of the oxide layer traps.

[0018] Preferably, the simulation test data of the SBFET interface traps and the oxide layer traps can include:

[0019] A plurality of interface traps in the oxide layer and the semiconductor interface of the SBFET are uniformly distributed in the entire band gap range to obtain a plurality of second SBFET test samples; the interface traps of the plurality of second SBFET test samples have different charge densities.

[0020] The gate voltage and drain current transfer characteristics of the plurality of second SBFET test samples are simulated and tested to obtain the simulation test data of the donor interface traps and the simulation test data of the acceptor interface traps.

[0021] The simulation test data of the donor interface traps and the simulation test data of the acceptor interface traps are used as the simulation test data of the interface traps.

[0022] Preferably, determining the target trap affecting the threshold voltage drift of the SBFET based on the simulation test data and the measured data can include:

[0023] data comparison between the simulation test data of the oxide layer trap and the measured data to obtain a first comparison result;

[0024] data comparison between the simulation test data of the interface trap and the measured data to obtain a second comparison result;

[0025] Based on the first comparison result and the second comparison result, the target trap affecting the threshold voltage drift of the SBFET is obtained; the target trap is a slow interface trap in the interface trap.

[0026] Preferably, the determination of the target charging voltage and the target charging time of the target trap can include:

[0027] A plurality of SBFET charging test samples are provided;

[0028] Based on the voltage withstand capability of a plurality of SBFET charging test samples, a target charging voltage acting on the source and gate of a plurality of SBFETs is determined;

[0029] Based on the target charging voltage, a plurality of SBFET charging test samples are pre-charged according to different charging times;

[0030] The gate voltage and drain current transfer characteristics of the plurality of SBFET charging test samples after pre-charging are repeatedly tested to obtain a plurality of target measured data;

[0031] Based on a plurality of target measured data, a plurality of target charging test samples are obtained; a plurality of target charging test samples are threshold voltage drift-free samples;

[0032] The charging time corresponding to a plurality of target charging test samples is sorted, and the shortest charging time is taken as the target charging time of the SBFET target trap.

[0033] Preferably, based on the target charging voltage, a plurality of SBFET charging test samples are pre-charged according to different charging times, which can include:

[0034] The source and drain of a plurality of SBFET charging test samples are connected to -10V voltage, and the gate is connected to 0V voltage;

[0035] According to different charging times, a plurality of SBFET charging test samples are pre-charged.

[0036] Preferably, the charging the target traps of the SBFET based on the target charging time length can include:

[0037] According to the plurality of target cumulative irradiation dose nodes, the charged SBFET is subjected to irradiation effect test to obtain irradiation test data;

[0038] Based on the irradiation test data, the drift amount of threshold voltage and flat-band voltage of the charged SBFET is verified.

[0039] In a second aspect, the present application provides a device for inhibiting threshold voltage drift of SBFET, which can include:

[0040] A first acquisition module is configured to acquire measured data of gate voltage and drain current transfer characteristics of SBFET;

[0041] A second acquisition module is configured to acquire simulation test data of interface traps and oxide layer traps of SBFET; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics;

[0042] A first determination module is configured to determine target traps affecting threshold voltage drift of SBFET based on the simulation test data and the measured data;

[0043] A second determination module is configured to determine target charging voltage and target charging time length of the target traps of the SBFET;

[0044] A charging module is configured to charge the target traps of the SBFET based on the target charging voltage and the target charging time length, so as to inhibit threshold voltage drift of the SBFET during transfer characteristic test.

[0045] In a third aspect, the present application provides a device for inhibiting threshold voltage drift of SBFET, which can include a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for inhibiting threshold voltage drift of SBFET according to the first aspect.

[0046] Compared with the prior art, the method for inhibiting threshold voltage drift of the SBFET provided by the application comprises the following steps: obtaining measured data of gate voltage and drain current transfer characteristics of the SBFET, and obtaining simulation test data of interface traps and oxide layer traps of the SBFET; the simulation test data comprises simulation test data of the gate voltage and the drain current transfer characteristics; determining target traps affecting threshold voltage drift of the SBFET based on the simulation test data and the measured data; determining target charging voltage and target charging duration of the target traps; and charging the target traps according to the target charging voltage and the target charging duration, so as to inhibit threshold voltage drift of the SBFET during transfer characteristic testing. Based on this, the band at the silicon and oxide layer interface is bent downward under the bias condition of charging the target traps, and the charge of the target traps is increased, so that effective inhibition of threshold voltage drift of the SBFET during repeated transfer characteristic testing is realized. Test verification shows that threshold voltage drift of the SBFET after charging is effectively inhibited during repeated transfer characteristic testing. BRIEF DESCRIPTION OF DRAWINGS

[0047] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0048] Figure 1a It is a top view of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0049] Figure 1b It is a sectional view of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0050] Figure 2a It is a schematic diagram of transfer characteristic drift caused by repeated transfer characteristic testing of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0051] Figure 2b It is a schematic diagram of variation curves of positive gate voltage current turn-on voltage drift and negative gate voltage current turn-on voltage drift of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0052] Figure 3 It is a main flow schematic diagram of a method for inhibiting threshold voltage drift of a Schottky barrier field effect transistor (SBFET) provided by the application;

[0053] Figure 4 It is a transfer characteristic curve simulation result schematic diagram of a method for inhibiting threshold voltage drift of a Schottky barrier field effect transistor (SBFET) provided by the application, in which oxide layer traps are uniformly distributed in the entire band gap range of an oxide layer of the SBFET;

[0054] Figure 5The simulation result schematic diagram of the transfer characteristic curve of the donor interface trap and the acceptor interface trap in the method for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0055] Figure 6 The simulation result schematic diagram of the gradual accumulation of the donor trap charge in the process of forward scanning of the gate voltage in the method for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0056] Figure 7 The simulation result schematic diagram of the gradual accumulation of the donor trap charge in the process of forward scanning of the gate voltage in the method for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0057] Figure 8 The simulation result schematic diagram of the energy band range of the donor interface trap and the acceptor interface trap in the method for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0058] Figure 9 The simulation result schematic diagram of the transfer characteristic curve of the acceptor interface trap corresponding to the different energy level range width center points of the same energy level range width in the method for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0059] Figure 10 The threshold voltage drift result schematic diagram of the sample piece with different charging time after repeated transfer characteristic tests in the method for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0060] Figure 11 The irradiation test result schematic diagram of the method for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0061] Figure 12 The irradiation test result schematic diagram of the SBFET without slow interface state charging before irradiation in the SB-TG state is shown in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0062] Figure 13 The structure schematic diagram of the device for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the device for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0063] Figure 14 The structure schematic diagram of the device for inhibiting the threshold voltage drift of the SBFET provided by the application is shown in the device for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0064] The drawing label: 1-source, 2-drain, 3-silicon island, 4-substrate, 5-oxide layer, 6-gate. DETAILED DESCRIPTION

[0065] For the convenience of clearly describing the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms of "first", "second", etc. are used to distinguish the same or similar items with basically the same functions and effects. For example, the first threshold value and the second threshold value are merely used to distinguish different threshold values, and the order of the first threshold value and the second threshold value is not limited. Those skilled in the art can understand that the terms of "first", "second", etc. do not limit the quantity and the execution order, and the terms of "first", "second", etc. do not necessarily mean different.

[0066] It should be noted that in the present application, the words of "exemplary" or "for example" are used to represent an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. In fact, the words of "exemplary" or "for example" are intended to present the relevant concept in a specific way.

[0067] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents that the associated objects are in an "or" relationship. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be single or multiple.

[0068] Firstly, some English abbreviations involved in the present application are described as follows:

[0069]

[0070] In the prior art, it is generally believed that a Schottky junction will be formed when a metal contacts a semiconductor. Please refer to Figures 1a to 1b , Figure 1a is a top view of a Schottky barrier field effect transistor (SBFET) in the prior art;

[0071] Figure 1b is a sectional view of a Schottky barrier field effect transistor (SBFET) in the prior art; wherein, Figure 1b the figure shown is a sectional view at the position of the dashed line in Figure 1a . Figures 1a to 1bIn order to simulate the Schottky barrier field effect transistor by using the TCAD simulation model, the internal structure of the Schottky barrier field effect transistor obtained can be simulated and tested, which is helpful to improve the design optimization of the Schottky barrier field effect transistor. Figure 1a In the left white background black point area, the drain 2 is on the right white background black point area, and the source 1 is on the middle black square area. Figure 1b The lowermost black bar area is the gate 6, the upper surface of the gate 6 is deposited with the substrate 4, and the upper surface of the substrate 4 is deposited with the oxide layer 5.

[0072] In the actual test process, the SBFET structure is repeatedly tested, and the test result as shown in Figures 2a to 2b can be obtained. Figures 2a to 2b , Figure 2a is a schematic diagram of the transfer characteristic drift caused by the repeated transfer characteristic test of the SBFET in the prior art. Figure 2b is a schematic diagram of the change curve of the positive gate voltage current opening voltage drift amount and the negative gate voltage current opening voltage drift amount of the SBFET in the prior art. Figure 2a In the drawing (1), the negative gate voltage transfer characteristic curve has no regular drift, and the right half of the drawing (2) has a regular positive drift. Figure 2a As shown in the content, the SBFET has good current regulation ability under positive and negative gate voltage, the threshold voltage and the flat band voltage of the SBFET are extracted by the Y-function method, repeated testing will cause the right current opening voltage threshold voltage (V th ) to regularly drift positively, and the drift amount reaches about 0.3V and reaches saturation. However, the left current opening voltage, i.e. the flat band voltage (V fb ) has no regular one-way drift.

[0073] By arranging a plurality of groups of SBFET device test results, similar problems are shown in Figure 2b . Therefore, we determine that the repeated test of the SBFET will only cause the drift of the current opening voltage (threshold voltage V th ) of the transfer characteristic curve of the positive gate voltage side, and cannot cause the one-way drift of the current opening voltage (flat band voltage V fb ) of the transfer characteristic curve of the negative gate voltage.

[0074] Therefore, the present application provides a method, device and equipment for inhibiting the threshold voltage drift of the SBFET, to solve the problem of threshold voltage drift in the prior art when the transfer characteristic of the SBFET is tested.

[0075] Next, the technical solutions of the present application will be described in detail in combination with the drawings:

[0076] In a first aspect, the present application provides a method for inhibiting threshold voltage drift of SBFET; please refer to Figure 3 , Figure 3 The main flowchart of the method for inhibiting threshold voltage drift of SBFET provided by the present application; the main body of the execution is a server or terminal device carrying the technical solutions disclosed in the embodiments of the present application, such as a service platform or a handheld device, etc.

[0077] In Figure 3 , the method can include:

[0078] Step 310: obtaining measured data of gate voltage and drain current transfer characteristics of SBFET.

[0079] Step 320: obtaining simulation test data of interface traps and oxide layer traps of SBFET; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristics.

[0080] Step 330: determining target traps affecting threshold voltage drift of SBFET based on the simulation test data and the measured data.

[0081] In steps 310 to 330, first, the measured data of gate voltage and drain current transfer characteristics of SBFET in the actual test process is obtained; further, simulation test data consistent with the size of the measured sample is obtained, which includes simulation test data of interface traps and oxide layer traps; the simulation test data and the measured data are compared and analyzed to determine the target traps of the threshold voltage drift of SBFET; it is determined that the target trap is a slow interface trap in the interface trap. It can be understood that the measured data and simulation test data obtained in steps 310 and 320 are respectively measured data obtained by actually testing a plurality of SBFET sample pieces with the same size parameters, and simulation test data obtained by simulating a plurality of SBFET simulation sample pieces with the same size parameters as the size parameters in the actual test process.

[0082] Step 340: determining target charging voltage and target charging time length of the target trap.

[0083] Step 350: charging the target trap based on the target charging voltage and the target charging time length to inhibit the threshold voltage drift of the SBFET during the transfer characteristic test.

[0084] In steps 340 to 350, firstly, the bias voltage for charging the target trap needs to be determined, and the conventional charging method is to connect -10V voltage to the source electrode and the drain electrode and connect 0V voltage to the gate electrode, under this bias condition, the energy band at the silicon and oxide layer interface is bent downward, which increases the interface donor trap charge, that is, the target trap is charged; further, the target charging time needs to be determined, that is, how long after the target charging voltage is applied can the threshold voltage drift be suppressed, and the target charging time is obtained after verification; finally, based on the target charging voltage and the target charging time, the target trap is charged, and the SBFET after charging will not have threshold voltage drift in the repeated gate voltage and drain current transfer characteristic test process.

[0085] Based on this, the present application provides a method for suppressing the threshold voltage drift of SBFET, by obtaining the measured data of the gate voltage and drain current transfer characteristic of SBFET, and the simulation test data of the interface trap and the oxide layer trap of SBFET; based on the simulation test data and the measured data, the target trap affecting the threshold voltage drift of SBFET is determined; further, the target charging voltage and the target charging time of the target trap are determined; finally, based on the target charging voltage and the target charging time, the target trap is charged to suppress the threshold voltage drift of SBFET during the transfer characteristic test; based on this, the threshold voltage drift during the repeated transfer characteristic test of SBFET is effectively suppressed, the problem of threshold voltage drift during the transfer characteristic test of SBFET in the prior art is solved, and the irradiation test of SBFET is avoided.

[0086] In actual application, in order to achieve the above purpose, we have analyzed the drift amount caused by repeated tests in detail, and combined with the simulation results to obtain the source of the test-induced drift, and found that the threshold voltage drift of repeated tests is caused by the slow interface state trap of SOI / BOX interface. Finally, based on the combination of simulation and measurement, a test scheme for charging the slow interface trap is obtained, which can effectively suppress the threshold voltage drift of SBFET during the transfer characteristic test, and can effectively eliminate the influence of the slow interface state before irradiation, and the test result after irradiation is only the negative drift of the threshold voltage and the flat-band voltage caused by irradiation.

[0087] Preferably, before step 320, i.e. obtaining the simulation test data of the SBFET interface traps and the oxide layer traps, can include: setting uniformly distributed oxide layer traps in the oxide layer of the SBFET in the whole band gap range, performing simulation test on the gate voltage and drain current transfer characteristics of the SBFET, and obtaining the simulation test data of the oxide layer traps; setting uniformly distributed interface traps in the oxide layer and the semiconductor interface of the SBFET in the whole band gap range, performing simulation test on the gate voltage and drain current transfer characteristics of the SBFET, and obtaining the simulation test data of the interface traps.

[0088] Preferably, setting uniformly distributed oxide layer traps in the oxide layer of the SBFET in the whole band gap range, performing simulation test on the gate voltage and drain current transfer characteristics of the SBFET, and obtaining the simulation test data of the oxide layer traps can include: setting uniformly distributed oxide layer traps in the oxide layer of a plurality of SBFETs in the whole band gap range, and obtaining a plurality of first SBFET test samples; the oxide layer traps of the plurality of first SBFET test samples have different charge densities; performing simulation test on the gate voltage and drain current transfer characteristics of the plurality of first SBFET test samples, and obtaining the simulation test data of the oxide layer traps.

[0089] Preferably, setting uniformly distributed interface traps in the oxide layer and the semiconductor interface of the SBFET in the whole band gap range, performing simulation test on the gate voltage and drain current transfer characteristics of the SBFET, and obtaining the simulation test data of the interface traps can include: setting uniformly distributed interface traps in the oxide layer and the semiconductor interface of a plurality of SBFETs in the whole band gap range, and obtaining a plurality of second SBFET test samples; the interface traps of the plurality of second SBFET test samples have different charge densities; performing simulation test on the gate voltage and drain current transfer characteristics of the plurality of second SBFET test samples, and obtaining the simulation test data of the donor interface traps and the simulation test data of the acceptor interface traps; taking the simulation test data of the donor interface traps and the simulation test data of the acceptor interface traps as the simulation test data of the interface traps.

[0090] It should be noted that the interface traps can include donor interface traps and acceptor interface traps, and the acceptor interface traps can further include slow interface traps or deep level traps. When setting two kinds of interface traps that are uniformly distributed in the whole band gap range, the donor interface traps will gradually accumulate positive trap charges during the process of changing the gate voltage from 0V to negative, and the acceptor interface traps will gradually accumulate negative trap charges during the process of changing the gate voltage from 0V to positive; based on this, the simulation test data of the interface traps are obtained; the donor interface traps can be referred to as donor traps, and the acceptor interface traps can be referred to as acceptor traps.

[0091] Preferably, in step 330, based on the simulation test data and the measured data, determining the target trap affecting the threshold voltage drift of the SBFET can include: performing data comparison on the simulation test data and the measured data of the oxide layer trap to obtain a first comparison result; performing data comparison on the simulation test data and the measured data of the interface trap to obtain a second comparison result; based on the first comparison result and the second comparison result, obtaining the target trap affecting the threshold voltage drift of the SBFET; and the target trap is a slow interface trap in the interface trap.

[0092] As an example, refer to Figure 4 , Figure 4 The simulation result schematic diagram of the transfer characteristic curve of the oxide layer trap uniformly distributed in the entire band gap range in the oxide layer of the SBFET in the method for suppressing the threshold voltage drift of the SBFET provided by the application; in Figure 4 , the horizontal axis represents the gate voltage, and the unit is V, and the vertical axis represents the drain current, and the unit is A; when the oxide layer trap charge density (D ox ) is respectively 0 cm -3 , and 1*10 18 cm -3 , the corresponding transfer characteristic curve simulation results are set. Among them, the curve is the transfer characteristic curve simulation result corresponding to the oxide layer trap charge density of 0 cm -3 , and the curve is the transfer characteristic curve simulation result corresponding to the oxide layer trap charge density of 1*10 18 cm -3 ; when the oxide layer trap charge is set, it is found that the positive and negative gate voltage transfer characteristic curves are shifted as a whole, and the threshold voltage and the flat band voltage have the same degree of drift, which is inconsistent with the test result in FIG. 2(a); therefore, it is judged that the oxide layer trap is not the factor affecting the threshold voltage drift.

[0093] Further, refer to Figures 5 to 9 , Figure 5 The simulation result schematic diagram of the transfer characteristic curve of the interface trap uniformly distributed in the entire band gap range in the oxide layer and the semiconductor interface of the SBFET in the method for suppressing the threshold voltage drift of the SBFET provided by the application; Figure 6 The simulation result schematic diagram of the gradual accumulation of the acceptor trap charge in the process of forward scanning of the gate voltage in the method for suppressing the threshold voltage drift of the SBFET provided by the application; Figure 7 The simulation result schematic diagram of the gradual accumulation of the donor trap charge in the process of negative scanning of the gate voltage in the method for suppressing the threshold voltage drift of the SBFET provided by the application; Figure 8 The simulation result schematic diagram of the energy band range of the donor interface trap and the acceptor interface trap in the method for suppressing the threshold voltage drift of the SBFET provided by the application;

[0094] Figure 9 The simulation results of the transfer characteristic curve corresponding to the uniform distribution of the acceptor interface traps in the same energy level range and the different energy level range center points in the method for inhibiting the threshold voltage drift of the SBFET provided by the application.

[0095] In Figure 5 , the horizontal axis represents the gate voltage, and the unit is V, and the vertical axis represents the drain current, and the unit is A; when the oxide trap charge density (D ox ) is respectively 0 cm -2 .eV -1 , and 1*10 13 cm -2 .eV -1 , the corresponding transfer characteristic curve simulation results are shown in the figure. The curve corresponds to the transfer characteristic curve simulation result when the oxide trap charge density is 0 cm -2 .eV -1 , and the curve corresponds to the transfer characteristic curve simulation result when the oxide trap charge density is 1*10 13 cm -2 .eV -1 ; wherein the two curves on the left side of the figure, that is, the two curves corresponding to the negative gate voltage, are the influence of the donor traps on the transfer characteristic, and the two curves on the right side of the figure, that is, the two curves corresponding to the positive gate voltage, are the influence of the acceptor traps on the transfer characteristic.

[0096] In Figure 7 , the horizontal axis represents the gate voltage, and the unit is V, and the vertical axis represents the acceptor trap charge density, and the unit is 1*10 11 cm -2 ; in Figure 8 , the horizontal axis represents the gate voltage, and the unit is V, and the vertical axis represents the donor trap charge density, and the unit is 1*10 11 cm -2 .

[0097] The curves shown in Figure 5 and Figure 6 can be obtained: Figure 5 shown is the two kinds of interface traps in the donor interface traps and the acceptor interface traps in the donor interface traps when the donor interface traps are uniformly distributed in the entire forbidden band width; Figure 6 shown is that the donor interface traps will gradually accumulate positive trap charges in the process of changing from 0V to negative gate voltage, which will cause the left half of the transfer characteristic curve shown in Figure 5 to increase the drift trend compared with the previous point at each point; that is, when the gate voltage is negative, the corresponding current curve will eventually lead to the opening voltage (flat band voltage V fbThe drift of ) also leads to an increase in the subthreshold slope SS.

[0098] Combination Figure 5 and Figure 7 The curve shown can be used to obtain: Figure 7 The diagram shows that the traps at the main interface gradually accumulate negative trap charges as the gate voltage changes from 0V to positive; this leads to... Figure 5 The right half of the transfer characteristic curve shown in the figure shows an increasing drift trend at each point compared to the previous point, i.e., the current curve when the gate voltage is positive, which ultimately leads to the current turn-on voltage (threshold voltage V) corresponding to the positive gate voltage side. th The drift of ) also leads to an increase in the subthreshold slope SS.

[0099] The actual test results show only threshold voltage drift, indicating that the only cause of threshold voltage drift without flat-band voltage drift is acceptor-type interface trap charges. However, the change in the subthreshold slope SS is undesirable. Furthermore, the gradual increase in trap charges uniformly distributed within the bandgap with increasing gate voltage suggests that by limiting the range of interface trap energy levels within the bandgap to introduce only variable acceptor interface traps near the 0 gate voltage, the bandgap distribution can be obtained as shown... Figure 8 The diagram shown.

[0100] from Figure 8 The content shown represents the band structure of the donor and receiver traps, where E i For the Fermi level of this semiconductor, E C At the very bottom of the conductor band, E V At the very top of the price band, donor traps are often positively charged, while receiver traps are often negatively charged.

[0101] For further details, please refer to the following: Figure 9 ,exist Figure 9 In the graph, the horizontal axis represents the gate voltage (V), and the vertical axis represents the drain current (A). (Curve) The curves represent the simulated transfer characteristics between drain current and gate voltage when the interface trap density is 0.0 ± 0.05 eV; The curves represent the simulated transfer characteristics between drain current and gate voltage when the interface trap density is 0.1 ± 0.05 eV; The curves represent the simulated transfer characteristics between drain current and gate voltage when the interface trap density is 0.2 ± 0.05 eV; The curves represent the simulated transfer characteristics between drain current and gate voltage when the interface trap density is 0.3 ± 0.05 eV; The curves represent the simulated transfer characteristics between drain current and gate voltage when the interface trap density is 0.4 ± 0.05 eV; a transfer characteristic curve between simulated drain current and gate voltage corresponding to the interface trap density of 0.5±0.05eV; and a transfer characteristic curve between simulated drain current and gate voltage corresponding to the interface trap density of 0.5±0.05eV.

[0102] By Figure 9 It can be seen from the content shown that after setting the acceptor type interface traps with the same trap energy level range (plus or minus 0.05eV), different center points of the energy level and the same trap density, a plurality of transfer characteristic curves are simulated, and it is found that when the trap energy level range is located near the intrinsic Fermi level, the trap only causes the off-state current to be widened before the current is turned on, and the overall effect is that the on-state current is positively translated compared to the 0 trap density, and the subsequent current curve is basically parallel to the curve without interface traps. This is consistent with the actual test results of the transistor, and the closer the trap energy level is to the intrinsic Fermi level, the longer the time constant of the trap for capturing and releasing carriers, so this part of the trap is a slow interface trap, also known as a deep level trap (a trap far from the conduction band or valence band is called a deep level trap).

[0103] Based on this, it can be determined that the main reason affecting the threshold voltage drift of the SBFET is the change of the current in the slow interface trap in the interface trap, so the target trap for optimization is determined as the slow interface trap in the interface trap.

[0104] After determining the specific reason for the threshold voltage drift caused by the repeated tests of the SBFET, a method of charging the slow interface trap is further adopted, which can solve the problem of the threshold voltage drift caused by the repeated tests of the SBFET.

[0105] Preferably, in step 340, determining the target charging voltage and the target charging duration of the target trap can include: providing a plurality of SBFET charging test samples; determining the target charging voltage acting on the source and gate of the plurality of SBFET charging test samples based on the voltage withstand capability of the plurality of SBFET charging test samples; pre-charging the plurality of SBFET charging test samples according to different charging durations based on the target charging voltage; repeatedly testing the gate voltage and the drain current transfer characteristic of the plurality of SBFET charging test samples after pre-charging is completed to obtain a plurality of target measured data; obtaining a plurality of target charging test samples based on the plurality of target measured data; the plurality of target charging test samples are samples whose threshold voltage has not drifted; and sorting the charging durations corresponding to the plurality of target charging test samples, and taking the shortest charging duration as the target charging duration of the SBFET target trap.

[0106] Preferably, in step 340, the pre-charging of the plurality of SBFET charging test samples according to different charging time lengths based on the target charging voltage can include: connecting the source and drain of the plurality of SBFET charging test samples to -10V voltage respectively, and connecting the gate to 0V voltage; and pre-charging the plurality of SBFET charging test samples according to different charging time lengths respectively.

[0107] It should be noted that the target charging voltage and the target charging time length of the transistor of different voltage withstand grades can be different, and the specific charging voltage and charging time can be obtained by test verification through the simulation method provided by the present application; in the present scheme, the charging voltage is determined when the SBFET is in the state of the maximum drift.

[0108] As an example, the source (Source) and drain (Drain) electrodes of the SBFET can be connected to -10V voltage respectively, and the gate can be connected to 0V voltage. Under this bias condition, the energy band at the silicon and oxide layer interface is bent downward, which will increase the interface donor trap charge, that is, the acceptor interface trap of the plurality of target charging test samples is charged. Please refer to Figure 10 , Figure 10 The threshold voltage drift results after the repeated transfer characteristic test of the test sample of different charging time lengths in the method for suppressing the threshold voltage drift of the SBFET provided by the present application are shown in the schematic diagram.

[0109] In the Figure 10 , the curve represents the threshold voltage drift curve of the test sample with a charging time length of 10s after the repeated transfer characteristic test; the curve represents the threshold voltage drift curve of the test sample with a charging time length of 30s after the repeated transfer characteristic test; the curve represents the threshold voltage drift curve of the test sample with a charging time length of 90s after the repeated transfer characteristic test; the curve represents the threshold voltage drift curve of the test sample with a charging time length of 2min after the repeated transfer characteristic test; the curve represents the threshold voltage drift curve of the test sample with a charging time length of 3min after the repeated transfer characteristic test; the curve represents the threshold voltage drift curve of the test sample with a charging time length of 4min after the repeated transfer characteristic test; the curve represents the threshold voltage drift curve of the test sample with a charging time length of 10min after the repeated transfer characteristic test.

[0110] From Figure 10It can be obtained in the embodiment that after the multiple groups of SBFET devices are processed with different charging time, when the charging time is greater than or equal to 4 minutes, the multiple repeated electrical tests after charging can not cause the threshold voltage to continue to drift. Therefore, the target charging time can be set to be greater than or equal to 4 minutes.

[0111] Based on this, the source and the drain of the SBFET charging test sample are respectively connected with a voltage of-10V, the gate is connected with a voltage of 0V, the charging time is greater than or equal to 4 minutes, and the target trap of the SBFET is charged, so as to suppress the drift of the threshold voltage of the SBFET during the transfer characteristic test.

[0112] Further, in order to verify the method for suppressing the drift of the threshold voltage of the SBFET provided in the embodiment, preferably, after step 350, that is, based on the target charging time, the target trap of the SBFET is charged, and then the method can further include: performing irradiation effect test on the charged SBFET according to multiple target cumulative irradiation dose nodes to obtain irradiation test data; and verifying the drift amount of the threshold voltage and the flat band voltage of the charged SBFET based on the irradiation test data.

[0113] Specifically, the irradiation effect test on the SBFET under different bias states is performed according to the bias states of the SBFET shown in Table 1.

[0114] Table 1 is the bias state of the SBFET during the irradiation experiment

[0115]

[0116] It should be noted that the position of the applied voltage in the irradiation experiment corresponds to the position of the Schottky barrier field effect transistor shown in FIG. 1.

[0117] Preferably, the cumulative dose nodes during the irradiation process are 0, 100, 300 and 500 krad(Si), and the dose rate is 200 rad(Si) / s. The threshold voltage and the flat band voltage extraction results before and after the irradiation are as shown in Figure 11 Figure 11 is the irradiation test result diagram of the method for suppressing the drift of the threshold voltage of the SBFET provided in the embodiment.

[0118] In Figure 11 , the left half part (a) of the figure is the positive gate voltage (V g ) current opening voltage drift amount, that is, the drift amount of the threshold voltage V th ; Figure 11 The right half part (b) of the figure is the negative gate voltage (V​g ) current on voltage drift, i.e. flat band voltage V fb By comparison, it is found that the bias state of the SB-TG state causes the threshold voltage and the flat band voltage of the SBFET to have a single direction maximum amplitude drift, and we define this bias as the worst bias of the SBFET structure.

[0119] Further, we carried out SB-TG state irradiation experiments on another group of samples that were charged with slow interface states by using the method for suppressing threshold voltage drift of the SBFET provided in the application, and the experimental results are shown in Figure 12 , Figure 12 The SB-TG state irradiation experimental results of the SBFET that was not charged with slow interface states before irradiation are shown in the schematic diagram of

[0120] It can be found from Figure 12 that the threshold voltage first has a positive drift at a 100krad(Si) node, and subsequent measurement nodes have a negative drift, and the positive drift at the 100krad(Si) node is the result of the positive drift caused by the charging of the acceptor type slow interface state after the electrical test covering the negative drift introduced by the weak irradiation effect.

[0121] Based on this, through the results shown in Figure 11 and Figure 12 , it can be concluded without any doubt that the method for suppressing threshold voltage drift of the SBFET provided in the application can effectively suppress the problem of voltage drift of the SBFET during repeated gate voltage and drain current transfer characteristic tests before irradiation, and will not have any impact on the irradiation test.

[0122] In a second aspect, the application provides a device for suppressing threshold voltage drift of an SBFET, please refer to Figure 13 , Figure 13 for a structural schematic diagram of a device for suppressing threshold voltage drift of an SBFET provided in the application.

[0123] In Figure 13 , the device can include:

[0124] A first acquisition module 1310 is configured to acquire measured data of the gate voltage and the drain current transfer characteristics of the SBFET.

[0125] A second acquisition module 1320 is configured to acquire simulation test data of interface traps and oxide layer traps of the SBFET; the simulation test data includes simulation test data of the gate voltage and the drain current transfer characteristics.

[0126] The first determination module 1330 is configured to determine a target trap affecting the threshold voltage drift of the SBFET based on the simulation test data and the measured data.

[0127] The second determination module 1340 is configured to determine a target charging voltage and a target charging duration of the target trap of the SBFET.

[0128] The charging module 1350 is configured to charge the target trap of the SBFET based on the target charging voltage and the target charging duration, so as to suppress the threshold voltage drift of the SBFET during the transfer characteristic test.

[0129] Based on the above, the application provides a device for suppressing the threshold voltage drift of the SBFET. The first acquisition module 1310 is configured to acquire measured data of the gate voltage and the drain current transfer characteristic of the SBFET. The second acquisition module 1320 is further configured to acquire simulation test data of the interface trap and the oxide layer trap of the SBFET, wherein the simulation test data comprises simulation test data of the gate voltage and the drain current transfer characteristic. The first determination module 1330 is configured to determine a target trap affecting the threshold voltage drift of the SBFET based on the simulation test data and the measured data. The second determination module 1340 is configured to determine a target charging voltage and a target charging duration of the target trap of the SBFET. The charging module 1350 is configured to charge the target trap of the SBFET based on the target charging voltage and the target charging duration, so as to suppress the threshold voltage drift of the SBFET during the transfer characteristic test. The device realizes effective suppression of the threshold voltage drift of the SBFET during repeated transfer characteristic tests. The test verification shows that the threshold voltage drift of the SBFET after the charging is effectively suppressed during repeated transfer characteristic tests, and the influence of the irradiation test on the SBFET is avoided.

[0130] In a third aspect, the application provides a device for suppressing the threshold voltage drift of the SBFET. Please refer to Figure 14 , Figure 14 The device for suppressing the threshold voltage drift of the SBFET provided by the application has the structure shown in the accompanying drawings.

[0131] In Figure 14 , the device 1400 comprises a memory 1420, a processor, and a computer program stored in the memory 1420 and executable on the processor. When the processor executes the computer program, the method for suppressing the threshold voltage drift of the SBFET in the first aspect is realized.

[0132] Specifically, in Figure 14In some embodiments, the device 1400 can include a memory 1420, a first processor 1410, a second processor 1450, and a computer program stored in the memory 1420 and executable on the first processor 1410 and / or the second processor 1450, and the first processor 1410 and / or the second processor 1450 implement the simulation method of the SBFET according to the first aspect of the present application when executing the computer program.

[0133] Optionally, the device 1400 can include a communication interface 1430. The communication interface 1430 can be one or more. The communication interface 1430 can use any transceiver-like device for communicating with other devices or communication networks.

[0134] Optionally, the device 1400 can also include a communication line 1440. The communication line 1440 can include a path for transmitting information between the above-mentioned components.

[0135] It should be noted that the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magneto-optical disk, a magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through the communication line. The memory can also be integrated with the processor.

[0136] Optionally, the computer-executable instructions in the embodiments of the present application can also be referred to as application program codes, and the embodiments of the present application do not make specific limitations on this.

[0137] In a specific implementation, as an embodiment, as shown in Figure 14 , the first processor 1410 and the second processor 1450 can include one or more CPUs, such as CPU0 and CPU1 in Figure 14 .

[0138] Although the application has been described in connection with various embodiments thereof, it will be understood that the application is capable of further modifications and that this application is intended to cover any and all such variations, using the scope of the claims. In the claims, the term comprising does not exclude the presence of other elements or steps than those listed in a claim. The term "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. A single processor or other unit can fulfil the functions of several items recited in the claims. The terms "first", "second" and the like in the description do not necessarily imply that there are two or more items. Embodiments of the application can relate to any of the specific features and combinations thereof without necessarily referring to the corresponding drawings.

[0139] Although the application has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modifications and this application is intended to cover any and all such variations, using the scope of the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Therefore, it is intended that the present application cover all such modifications and variations of the application that come within the scope of the appended claims and their equivalents.

Claims

1. A method of suppressing threshold voltage drift in an SBFET, comprising: The method comprises the following steps: obtaining measured data of gate voltage and drain current transfer characteristics of the SBFET; obtaining simulation test data of interface traps and oxide layer traps of the SBFET; the simulation test data comprises simulation test data of gate voltage and drain current transfer characteristics; based on the simulation test data and the measured data, determining target traps affecting threshold voltage drift of the SBFET; the determination of the target traps affecting threshold voltage drift of the SBFET based on the simulation test data and the measured data comprises the following steps: comparing the simulation test data of the oxide layer traps with the measured data to obtain a first comparison result; comparing the simulation test data of the interface traps with the measured data to obtain a second comparison result; and based on the first comparison result and the second comparison result, obtaining the target traps affecting threshold voltage drift of the SBFET; the target traps are slow interface traps in the interface traps; determining a target charging voltage and a target charging time length of the target traps; based on the target charging voltage and the target charging time length, charging the target traps to suppress threshold voltage drift of the SBFET during transfer characteristic testing.

2. The method of claim 1, wherein, The method for obtaining simulation test data of interface traps and oxide layer traps of the SBFET comprises the following steps: uniformly distributing oxide layer traps in the oxide layer of the SBFET within the entire band gap range, and performing gate voltage and drain current transfer characteristic simulation test on the SBFET to obtain simulation test data of the oxide layer traps; uniformly distributing interface traps in the oxide layer and the semiconductor interface of the SBFET within the entire band gap range, and performing gate voltage and drain current transfer characteristic simulation test on the SBFET to obtain simulation test data of the interface traps.

3. The method of claim 2, wherein, The method for obtaining simulation test data of interface traps and oxide layer traps of the SBFET comprises the following steps: uniformly distributing oxide layer traps in the oxide layer of the SBFET within the entire band gap range, and performing gate voltage and drain current transfer characteristic simulation test on the SBFET to obtain simulation test data of the oxide layer traps; uniformly distributing interface traps in the oxide layer and the semiconductor interface of the SBFET within the entire band gap range, and performing gate voltage and drain current transfer characteristic simulation test on the SBFET to obtain simulation test data of the interface traps.

4. The method of claim 2, wherein, The method for obtaining simulation test data of interface traps and oxide layer traps of the SBFET comprises the following steps: uniformly distributing oxide layer traps in the oxide layer of the SBFET within the entire band gap range, and performing gate voltage and drain current transfer characteristic simulation test on the SBFET to obtain simulation test data of the oxide layer traps; uniformly distributing interface traps in the oxide layer and the semiconductor interface of the SBFET within the entire band gap range, and performing gate voltage and drain current transfer characteristic simulation test on the SBFET to obtain simulation test data of the interface traps. Performing gate voltage and drain current transfer characteristic simulation tests on the plurality of second SBFET test samples to obtain simulation test data of donor interface traps and simulation test data of acceptor interface traps; The simulation test data of the donor interface traps and the simulation test data of the acceptor interface traps are used as the simulation test data of the interface traps.

5. The method of claim 1, wherein, The determining of the target charging voltage and the target charging duration of the target trap includes: A plurality of SBFET charging test samples are provided; Based on the voltage withstand capability of the plurality of SBFET charging test samples, a target charging voltage acting on the plurality of SBFET sources and gates is determined; Based on the target charging voltage, the plurality of SBFET charging test samples are pre-charged in different charging durations, respectively; After the pre-charging is completed, the plurality of SBFET charging test samples are repeatedly tested for gate voltage and drain current transfer characteristics to obtain a plurality of target measured data; Based on the plurality of target measured data, a plurality of target charging test samples are obtained; the plurality of target charging test samples are threshold voltage drift-free samples; The charging durations corresponding to the plurality of target charging test samples are sorted, and the shortest charging duration is used as the target charging duration of the SBFET target trap.

6. The method of claim 5, wherein, The pre-charging of the plurality of SBFET charging test samples in different charging durations based on the target charging voltage includes: The source and the drain of the plurality of SBFET charging test samples are respectively connected to -10V voltage, and the gate is connected to 0V voltage; The plurality of SBFET charging test samples are pre-charged in different charging durations, respectively.

7. The method of claim 1, wherein, After the SBFET target trap is charged based on the target charging duration, the following includes: According to a plurality of target cumulative irradiation dose nodes, irradiation effect tests are performed on the charged SBFET to obtain irradiation test data; Based on the irradiation test data, the drift amount of the threshold voltage and the flat-band voltage of the charged SBFET is verified.

8. An apparatus for suppressing threshold voltage drift of an SBFET, the apparatus comprising: It includes: A first acquisition module, the first acquisition module is used for acquiring the measured data of SBFET gate voltage and drain current transfer characteristic; A second acquisition module, the second acquisition module is used for acquiring simulation test data of SBFET interface traps and oxide layer traps; the simulation test data includes simulation test data of gate voltage and drain current transfer characteristic; A first determination module, the first determination module is used for determining the target trap affecting the threshold voltage drift of SBFET based on the simulation test data and the measured data; The determining the target trap affecting the threshold voltage drift of the SBFET based on the simulation test data and the measured data comprises: performing data comparison between the simulation test data of the oxide layer trap and the measured data to obtain a first comparison result; performing data comparison between the simulation test data of the interface trap and the measured data to obtain a second comparison result; and obtaining the target trap affecting the threshold voltage drift of the SBFET based on the first comparison result and the second comparison result; the target trap is a slow interface trap in the interface trap. The second determining module is configured to determine a target charging voltage and a target charging time length of the SBFET target trap. The charging module is configured to charge the SBFET target trap based on the target charging voltage and the target charging time length, so as to suppress the threshold voltage drift of the SBFET during the transfer characteristic test.

9. An apparatus to suppress SBFET threshold voltage drift, comprising: The computer program is stored in the memory and executable on the processor, and when the processor executes the computer program, the method for suppressing the threshold voltage drift of the SBFET according to any one of claims 1 to 7 is implemented.

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