Double pulse and short circuit test method and device for NPC T-type three-level circuit

Abstract

The present application belongs to the field of inverter circuits, and includes a double pulse and short circuit test method for an NPC T-type three-level circuit, which is used to perform a half-bus voltage double pulse and short circuit test on a first IGBT tube Q1 in a test circuit of an NPC T-type three-level circuit, and a third selection device S3 is arranged in parallel at both ends of a third IGBT tube Q3 and a fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit, which is used to select a half-bus voltage double pulse test or a short circuit test for the first IGBT tube Q1; when the third selection device S3 is set to a half-bus voltage double pulse test, a double pulse signal is simultaneously sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4. The present application is used to avoid the test process from taking too long, so that the test process can be switched quickly.

Description

Technical Field

[0001] The present application belongs to the field of inverter circuits, and specifically relates to a double pulse and short circuit test method for an NPC T-type three-level circuit and a double pulse and short circuit test device for an NPC T-type three-level circuit. Background Art

[0002] The NPC T-type three-level circuit is a multi-level inverter topology. Figure 1 As shown, the T-type three-level circuit consists of two half-bridge inverter units and a neutral point (usually coupled by capacitors), forming a "T"-shaped circuit topology. Each half-bridge contains two switching elements (such as IGBTs) and corresponding freewheeling diodes, and the neutral point capacitor is used for voltage support and level switching. The working principle of the T-type three-level inverter circuit is based on the resonance principle and the capacitor charging and discharging principle. By controlling the switching state of the two half-bridges, the T-type three-level circuit can generate a five-level line voltage waveform at the load end. The coordination of the capacitor charging and discharging process and the switching state enables the output voltage to smoothly transition between three different levels, reducing the harmonic content caused by the step waveform in the traditional two-level inverter. In the prior art, the IGBT in the NPC T-type three-level is tested for double pulses and short circuits, and the required data needs to be obtained by testing separately, which has low test efficiency; the inductor position and the position to be shorted in the short-circuit test need to be manually changed, so the test process steps are cumbersome, the integration is low, and the reliability is low. Summary of the invention

[0003] In order to solve the technical problems of complicated steps, low integration and low reliability in the test process, the present application proposes a double pulse and short circuit test method for an NPC T-type three-level circuit and a double pulse and short circuit test device for an NPC T-type three-level circuit.

[0004] In a first aspect, a double pulse and short circuit test method for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a first IGBT tube Q1 in a test circuit of the NPC T-type three-level circuit, and comprises the following steps:

[0005] A third selection device S3 is provided in parallel at both ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short-circuit test for the first IGBT tube Q1;

[0006] When the third selection device S3 is set to the half bus voltage double pulse test, a double pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4;

[0007] When the third selection device S3 is set to the half bus voltage short-circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4.

[0008] In a second aspect, a double pulse and short circuit test method for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a second IGBT tube Q2 in a test circuit of the NPCT-type three-level circuit, and comprises the following steps:

[0009] A third selection device S3 is provided in parallel at both ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short-circuit test for the second IGBT tube Q2;

[0010] When the third selection device S3 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4;

[0011] When the third selection device S3 is set to the half-bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0012] In a third aspect, a double pulse and short circuit test method for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a third IGBT tube Q3 in a test circuit of the NPCT-type three-level circuit, and comprises the following steps:

[0013] A first selection device S1 is provided in parallel at both ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, for selecting a half-bus voltage double pulse test or a short circuit test for the third IGBT tube Q3;

[0014] When the first selection device S1 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a double pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4;

[0015] When the first selection device S1 is set to the half-bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a single pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4.

[0016] In a fourth aspect, a double pulse and short circuit test method for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a fourth IGBT tube Q4 in a test circuit of the NPCT-type three-level circuit, and comprises the following steps:

[0017] A second selection device S2 is provided in parallel at both ends of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, for selecting a half-bus voltage double pulse test or a short circuit test for the second IGBT tube Q2;

[0018] When the second selection device S2 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4;

[0019] When the second selection device S2 is set to the half-bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4.

[0020] In a fifth aspect, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used to perform a full bus voltage double pulse and short circuit test on a first IGBT tube Q1 in an NPCT-type three-level circuit, comprising the following steps:

[0021] A second selection device S2 is provided in parallel at both ends of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, for selecting the first IGBT tube Q1 to perform a full bus voltage double pulse test or a short circuit test;

[0022] When the second selection device S2 is set to the full bus voltage double pulse test, a double pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4;

[0023] When the second selection device S2 is set to the full bus voltage short-circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0024] In a sixth aspect, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used to perform a full bus voltage double pulse and short circuit test on a second IGBT tube Q2 in the NPCT-type three-level circuit, comprising the following steps:

[0025] A first selection device S1 is provided in parallel at both ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, for selecting the second IGBT tube Q2 to perform a full bus voltage double pulse test or a short circuit test;

[0026] When the first selection device S1 is set to the full bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4;

[0027] When the first selection device S1 is set to the full bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0028] Preferably, the first selection device S1 comprises: a first converter SW1, a first inductor L1 and a first copper sheet U1; the first converter SW1 is used to connect the first inductor L1 in parallel to the two ends of the first IGBT tube Q1 during a full bus voltage or half bus voltage double pulse test; or to connect the first copper sheet U1 in parallel to the two ends of the first IGBT tube Q1 during a full bus voltage or half bus voltage short circuit test;

[0029] The second selection device S2 includes: a second converter SW2, a second inductor L2 and a second copper sheet U2; the second converter SW2 is used to connect the second inductor L2 in parallel to the two ends of the second IGBT tube Q2 during a full bus voltage or half bus voltage double pulse test; or to connect the second copper sheet U2 in parallel to the two ends of the second IGBT tube Q2 during a full bus voltage or half bus voltage short circuit test;

[0030] The third selection device S3 includes: a third converter SW3, a third inductor L3 and a third copper sheet U3; the third converter SW3 is used to connect the third inductor L3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during the half-bus double pulse test; or to connect the third copper sheet U3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during the half-bus short circuit test.

[0031] In a seventh aspect, a double pulse and short circuit test device for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a first IGBT tube Q1 or a second IGBT tube Q2 in a test circuit of the NPCT-type three-level circuit, comprising:

[0032] The third selection device S3 is arranged in parallel between the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 which are connected in sequence in the test circuit of the NPC T-type three-level circuit; it is used to select the first IGBT tube Q1 or the second IGBT tube Q2 to perform half-bus voltage double pulse test and short circuit test.

[0033] In an eighth aspect, a double pulse and short circuit test device for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a third IGBT tube Q3 in a test circuit of the NPC T-type three-level circuit, or to perform a full-bus voltage double pulse and short circuit test on a second IGBT tube Q2 in a test circuit of the NPC T-type three-level circuit, comprising:

[0034] The first selection device S1 is arranged in parallel at both ends of the first IGBT tube Q1; it is used to select the half bus voltage double pulse test and short circuit test for the third IGBT tube Q3, or to perform the full bus voltage double pulse and short circuit test for the second IGBT tube Q2.

[0035] In a ninth aspect, a double pulse and short circuit test device for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a fourth IGBT tube Q4 in a test circuit of the NPC T-type three-level circuit, or to perform a full-bus voltage double pulse and short circuit test on a first IGBT tube Q1 in a test circuit of the NPC T-type three-level circuit, comprising:

[0036] The second selection device S2 is arranged in parallel at both ends of the second IGBT tube Q2; it is used to select the half bus voltage double pulse test and short circuit test for the fourth IGBT tube Q4, or to perform the full bus voltage double pulse and short circuit test on the first IGBT tube Q1.

[0037] In summary, the present application includes at least one of the following beneficial technical effects:

[0038] 1. By using the first selection device S1, the second selection device S2 or the third selection device S3, the half bus voltage double pulse test and the short circuit test of the IGBT tube can be quickly switched, thereby avoiding the technical problems of high test cost and low test efficiency;

[0039] 2. By using the first selection device S1 and the second selection device S2, the IGBT tube can be quickly switched between the full bus voltage double pulse test and the short circuit test, thus avoiding the technical problems of high test cost and low test efficiency;

[0040] 3. This solution has high integration and improves the reliability of the test system. The test steps are concise and clear. While improving the test efficiency, it optimizes the test method of the NPC T-type module under full bus voltage and improves data accuracy. By obtaining full bus voltage and half bus voltage data in the same test process, more accurate comparative analysis can be performed to discover potential problems and improvement points. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is the NPC T-type three-level circuit diagram;

[0042] Figure 2 It is a diagram for performing half bus voltage double pulse and short circuit tests on the first IGBT tube Q1 and the second IGBT tube Q2 respectively;

[0043] Figure 3 This is a diagram of performing a half bus voltage double pulse and short circuit test on the third IGBT tube Q3, or performing a full bus voltage double pulse and short circuit test on the second IGBT tube Q2;

[0044] Figure 4 This is a diagram of performing a half bus voltage double pulse and short circuit test on the fourth IGBT tube Q4, or performing a full bus voltage double pulse and short circuit test on the first IGBT tube Q1;

[0045] Figure 5 is a diagram of the structure of the first selection device S1, the second selection device S2 and the third selection device S3;

[0046] Figure 6It is a composition diagram of the third selection device S3 when performing half bus voltage double pulse and short circuit tests on the first IGBT tube Q1 and the second IGBT tube Q2 respectively;

[0047] Figure 7 This is a diagram of the composition of the first selection device S1 when a half bus voltage double pulse and short circuit test is performed on the third IGBT tube Q3, or a full bus voltage double pulse and short circuit test is performed on the second IGBT tube Q2;

[0048] Figure 8 This is a diagram showing the structure of the second selection device S2 when the fourth IGBT tube Q4 is subjected to a half-bus voltage double pulse and short-circuit test, or the first IGBT tube Q1 is subjected to a full-bus voltage double pulse and short-circuit test. DETAILED DESCRIPTION

[0049] Terminology explanation:

[0050] NPC T-type three-level circuit: NPC (Neutral Point Clamped) is a neutral point clamped circuit; that is, a T-shaped NPC circuit.

[0051] The present application proposes a double pulse and short circuit test method for an NPC T-type three-level circuit and a double pulse and short circuit test device for an NPC T-type three-level circuit.

[0052] First, as Figure 2 As shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is provided, which is used to perform a half-bus voltage double pulse and short circuit test on a first IGBT tube Q1 in a test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0053] A third selection device S3 is arranged in parallel at both ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected sequentially in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short circuit test for the first IGBT tube Q1; the third selection device S3 can be implemented in a variety of ways, for example, by an active device or a switch circuit; whether it is an active device or a switch circuit, it can be controlled by the control circuit so that the third selection device S3 is in a conducting, short-circuited or disconnected state, so as to achieve the state of double pulse test, short circuit test or disconnection for the first IGBT tube Q1.

[0054] When the third selection device S3 is set to the half bus voltage double pulse test, a double pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4; at this time, the voltage applied between the gate and source of the first IGBT tube Q1 is half the bus voltage, that is, Figure 2 The voltage between the DC+ and 0 terminals described in the figure. At this time, the current flows as follows: DC+ terminal - first IGBT tube Q1 - third selection device S3 - 0 terminal. Since the gate of the fourth IGBT tube Q4 is at a high level and is normally open, and the diode connected in parallel with the third IGBT tube Q3 is used to complete the freewheeling circuit, the reverse recovery parameter of the diode FRD (Fast Recover Diode) connected in parallel with the third IGBT tube Q3 can also be tested at this time.

[0055] When the third selection device S3 is set to the half bus voltage short circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection of the third selection device S3 should be connected with a device with strong overcurrent capacity, and wire-type devices with poor current carrying capacity should not be used. At this time, the voltage is added to: DC+ terminal--0 terminal.

[0056] Second, as Figure 2 As shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used to perform a half-bus voltage double pulse and short circuit test on the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0057] A third selection device S3 is arranged in parallel at both ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected sequentially in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short circuit test for the second IGBT tube Q2; the third selection device S3 can be implemented in a variety of ways, for example, by an active device or a switch circuit; whether it is an active device or a switch circuit, it can be controlled by the control circuit so that the third selection device S3 is in a conducting, short-circuited or disconnected state, so as to achieve the state of double pulse test, short circuit test or disconnection for the second IGBT tube Q2.

[0058] When the third selection device S3 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4; at this time, the voltage applied between the gate and source of the second IGBT tube Q2 is half the bus voltage, that is, Figure 2 The voltage between the 0 terminal and DC- in the above description. At this time, the current flows as follows: 0 terminal--the third selection terminal S3--the second IGBT tube Q2--the DC- terminal. Since the gate of the third IGBT tube Q3 is at a high level and is normally open at this time, and the diode connected in parallel with the fourth IGBT tube Q4 is used to complete the freewheeling circuit, the reverse recovery parameter of the diode FRD (Fast Recover Diode) connected in parallel with the fourth IGBT tube Q4 can also be tested at this time.

[0059] When the third selection device S3 is set to the half bus voltage short circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection of the third selection device S3 should be connected with a device with strong overcurrent capacity, and wire-type devices with poor current carrying capacity should not be used. At this time, the voltage is applied to: 0 terminal--DC-terminal.

[0060] Thirdly, Figure 3 As shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used to perform a half-bus voltage double pulse and short circuit test on the third IGBT tube Q3 in the test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0061] A first selection device S1 is arranged in parallel at both ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short circuit test for the third IGBT tube Q3; the first selection device S1 can be implemented in a variety of ways, for example, by an active device or a switch circuit; whether it is an active device or a switch circuit, it can be controlled by a control circuit so that the first selection device S1 is in an on, short circuit or off state, so as to achieve a double pulse test, a short circuit test or a disconnected state for the third IGBT tube Q3.

[0062] When the first selection device S1 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a double pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4; at this time, the voltage applied between the gate and the source of the third IGBT tube Q3 is half the bus voltage, that is, Figure 3 The voltage between the DC+ and 0 terminals described in the figure. At this time, the current flows as follows: DC+ terminal - first selection device S1 - third IGBT tube Q3 - fourth IGBT tube Q4 - 0 terminal. Since the gate of the fourth IGBT tube Q4 is at a high level and is normally open, a pulse is applied to the third IGBT tube Q3, and the diode connected in parallel with the first IGBT tube Q1 is used to complete the freewheeling circuit. Therefore, the reverse recovery parameter of the diode FRD (Fast Recover Diode) connected in parallel with the first IGBT tube Q1 can also be tested at this time.

[0063] When the first selection device S1 is set to the half bus voltage short circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a single pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection of the first selection device S1 should be connected with a device with strong overcurrent capacity, and a device with poor current carrying capacity of a wire type should not be used. At this time, the voltage is applied to: DC+ terminal--0 terminal.

[0064] Fourthly, Figure 4 As shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used to perform a half-bus voltage double pulse and short circuit test on the fourth IGBT tube Q4 in the test circuit of the NPC T-type three-level circuit, including the following steps:

[0065] A second selection device S2 is arranged in parallel at both ends of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short circuit test for the second IGBT tube Q2; the second selection device S2 can be implemented in a variety of ways, for example, by an active device or a switch circuit; whether it is an active device or a switch circuit, it can be controlled by the control circuit so that the second selection device S2 is in a conducting, short-circuited or disconnected state, so as to achieve the double pulse test, short-circuit test or disconnected state for the fourth IGBT tube Q4.

[0066] When the second selection device S2 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4; at this time, the voltage applied between the gate and the source of the fourth IGBT tube Q4 is half the bus voltage, that is, Figure 4 The voltage between the 0 terminal and the DC- terminal described in . At this time, the current flow is: 0 terminal--the fourth IGBT tube Q4--the third IGBT tube Q3--the second selection device S2--the DC- terminal. Since the gate of the third IGBT tube Q3 is at a high level and is normally open at this time, a pulse is applied to the fourth IGBT tube Q4, and the diode connected in parallel with the second IGBT tube Q2 is used to complete the freewheeling circuit. Therefore, the reverse recovery parameter of the diode FRD (Fast Recover Diode) connected in parallel with the second IGBT tube Q2 can also be tested at this time.

[0067] When the second selection device S2 is set to half bus voltage short circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection of the second selection device S2 should be connected with a device with strong overcurrent capacity, and a device with poor current carrying capacity of the wire type should not be used. At this time, the voltage is applied to: 0 terminal--DC-terminal.

[0068] Fifthly, Figure 4 As shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used to perform a full bus voltage double pulse and short circuit test on the first IGBT tube Q1 in the NPC T-type three-level circuit, comprising the following steps:

[0069] A second selection device S2 is arranged in parallel at both ends of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, for selecting the first IGBT tube Q1 to be subjected to a full bus voltage double pulse test or a short circuit test; the second selection device S2 can be implemented in a variety of ways, for example, by an active device or a switch circuit; both active devices and switch circuits can be controlled by a control circuit so that the second selection device S2 is in a conducting or short circuit state, thereby achieving full bus voltage double pulse and short circuit tests on the first IGBT tube Q1.

[0070] When the second selection device S2 is set to the full bus voltage double pulse test, a double pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4; at this time, the current direction is: DC+ end--first IGBT tube Q1--second selection device S2--DC-end; obviously, the full bus voltage is applied between the gate and source of the first IGBT tube Q1. In actual application, if "abnormal blocking wave" occurs, that is, the horizontal tube (the third IGBT tube Q3 and the fourth IGBT tube Q4) is turned off first, the vertical tube (here: the first IGBT tube Q1) will directly commutate, and the voltage borne by the vertical tube (here: the first IGBT tube Q1) when it is turned off becomes the full bus voltage. It is also necessary to simulate this extreme working condition to perform double pulse testing in the test.

[0071] When the second selection device S2 is set to the full bus voltage short circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4. Here, the second selection device S2 should be connected with a conductor with strong overcurrent capacity, and a wire with poor current carrying capacity should not be used. At this time, the above current flow is: DC+ end--first IGBT tube Q1--second selection device S2--DC-end; what is tested is the state of the first IGBT tube Q1 when the full bus voltage is short-circuited.

[0072] Sixth, such as Figure 3 As shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used to perform a full bus voltage double pulse and short circuit test on the second IGBT tube Q2 in the NPC T-type three-level circuit, comprising the following steps:

[0073] A first selection device S1 is arranged in parallel at both ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, for selecting the second IGBT tube Q2 to be subjected to a full bus voltage double pulse test or a short circuit test; the first selection device S1 can be implemented in a variety of ways, for example, by an active device or a switch circuit; both active devices and switch circuits can be controlled by a control circuit, so that the first selection device S1 is in an on or short circuit state, so as to achieve the full bus voltage double pulse and short circuit test on the second IGBT tube Q2.

[0074] When the first selection device S1 is set to the full bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4; at this time, the current direction is: DC+ end--first selection device S1--second IGBT tube Q2--DC-end; obviously, the full bus voltage is applied between the gate and source of the second IGBT tube Q2. In actual application, if "abnormal blocking wave" occurs, that is, the horizontal tube (the third IGBT tube Q3 and the fourth IGBT tube Q4) is turned off first, then the vertical tube (here: the second IGBT tube Q2) will directly commutate, and the voltage borne by the vertical tube (here: the second IGBT tube Q2) when it is turned off becomes the full bus voltage. It is also necessary to simulate this extreme working condition to perform double pulse testing in the test.

[0075] When the first selection device S1 is set to the full bus voltage short circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4. Here, the first selection device S1 should be connected with a conductor with strong overcurrent capacity, and a wire with poor current carrying capacity should not be used. At this time, the above current flow is: DC+ end--first selection device S1--second IGBT tube Q2--DC-end; what is tested is the state of the second IGBT tube Q2 when the full bus voltage is short-circuited.

[0076] Preferably, Figure 5 As shown, the first selection device S1 includes: a first converter SW1, a first inductor L1 and a first copper sheet U1; the first converter SW1 is used to connect the first inductor L1 in parallel to the two ends of the first IGBT tube Q1 during a full bus voltage or half bus voltage double pulse test; or to connect the first copper sheet U1 in parallel to the two ends of the first IGBT tube Q1 during a full bus voltage or half bus voltage short circuit test;

[0077] The second selection device S2 includes: a second converter SW2, a second inductor L2 and a second copper sheet U2; the second converter SW2 is used to connect the second inductor L2 in parallel to the two ends of the second IGBT tube Q2 during a full bus voltage or half bus voltage double pulse test; or to connect the second copper sheet U2 in parallel to the two ends of the second IGBT tube Q2 during a full bus voltage or half bus voltage short circuit test;

[0078] The third selection device S3 includes: a third converter SW3, a third inductor L3 and a third copper sheet U3; the third converter SW3 is used to connect the third inductor L3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during the half-bus double pulse test; or to connect the third copper sheet U3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during the half-bus short circuit test.

[0079] Seventh, such as Figure 2 , Figure 6 As shown, a double pulse and short circuit test device for an NPC T-type three-level circuit is also provided, which is used to perform a half-bus voltage double pulse and short circuit test on a first IGBT tube Q1 or a second IGBT tube Q2 in a test circuit of the NPC T-type three-level circuit, comprising:

[0080] The third selection device S3 is arranged in parallel between the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 which are connected in sequence in the test circuit of the NPC T-type three-level circuit; it is used to select the first IGBT tube Q1 or the second IGBT tube Q2 to perform half-bus voltage double pulse test and short circuit test.

[0081] Eighth aspect, such as Figure 3 , Figure 7 A double pulse and short circuit test device for an NPC T-type three-level circuit is also provided, which is used to perform a half bus voltage double pulse and short circuit test on a third IGBT tube Q3 in a test circuit of the NPC T-type three-level circuit, or to perform a full bus voltage double pulse and short circuit test on a second IGBT tube Q2 in a test circuit of the NPC T-type three-level circuit, including:

[0082] The first selection device S1 is arranged in parallel at both ends of the first IGBT tube Q1; it is used to select the half bus voltage double pulse test and short circuit test for the third IGBT tube Q3, or to perform the full bus voltage double pulse and short circuit test for the second IGBT tube Q2.

[0083] Ninth aspect, such as Figure 4 , Figure 8 As shown, a double pulse and short circuit test device for an NPC T-type three-level circuit is also provided, which is used to perform a half-bus voltage double pulse and short circuit test on a fourth IGBT tube Q4 in a test circuit of the NPC T-type three-level circuit, or to perform a full-bus voltage double pulse and short circuit test on a first IGBT tube Q1 in a test circuit of the NPC T-type three-level circuit, comprising:

[0084] The second selection device S2 is arranged in parallel at both ends of the second IGBT tube Q2; it is used to select the half bus voltage double pulse test and short circuit test for the fourth IGBT tube Q4, or to perform the full bus voltage double pulse and short circuit test on the first IGBT tube Q1.

[0085] By obtaining full bus voltage and half bus voltage data in the same test process, more accurate comparative analysis can be performed to identify potential problems and improvement points. The above process does not require the replacement of components, saving time and improving detection efficiency.

[0086] In summary, the present application includes at least one of the following beneficial technical effects:

[0087] 1. By using the first selection device S1, the second selection device S2 or the third selection device S3, the half bus voltage double pulse test and the short circuit test of the IGBT tube can be quickly switched, thereby avoiding the technical problems of high test cost and low test efficiency;

[0088] 2. By using the first selection device S1 and the second selection device S2, the IGBT tube can be quickly switched between the full bus voltage double pulse test and the short circuit test, thus avoiding the technical problems of high test cost and low test efficiency;

[0089] 3. This solution has high integration and improves the reliability of the test system. The test steps are concise and clear. While improving the test efficiency, it optimizes the test method of the NPC T-type module under full bus voltage and improves data accuracy. By obtaining full bus voltage and half bus voltage data in the same test process, more accurate comparative analysis can be performed to discover potential problems and improvement points.

[0090] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A double pulse and short circuit test method for an NPC T-type three-level circuit, used to perform a half-bus voltage double pulse and short circuit test on a first IGBT tube Q1 in a test circuit of the NPC T-type three-level circuit, characterized in that: The steps include: A third selection device S3 is provided in parallel at both ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short-circuit test for the first IGBT tube Q1; When the third selection device S3 is set to the half bus voltage double pulse test, a double pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4; When the third selection device S3 is set to the half bus voltage short-circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4.

2. A double pulse and short circuit test method for an NPC T-type three-level circuit, used to perform a half-bus voltage double pulse and short circuit test on a second IGBT tube Q2 in a test circuit of the NPC T-type three-level circuit, characterized in that: The steps include: A third selection device S3 is provided in parallel at both ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit, for selecting the half-bus voltage double pulse test or the short-circuit test for the second IGBT tube Q2; When the third selection device S3 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4; When the third selection device S3 is set to the half-bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

3. A double pulse and short circuit test method for an NPC T-type three-level circuit, used to perform a half-bus voltage double pulse and short circuit test on the third IGBT tube Q3 in the test circuit of the NPC T-type three-level circuit, characterized in that: The steps include: A first selection device S1 is provided in parallel at both ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, for selecting a half-bus voltage double pulse test or a short circuit test for the third IGBT tube Q3; When the first selection device S1 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a double pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4; When the first selection device S1 is set to the half-bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a single pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4.

4. A double pulse and short circuit test method for an NPC T-type three-level circuit, used to perform a half-bus voltage double pulse and short circuit test on the fourth IGBT tube Q4 in the test circuit of the NPC T-type three-level circuit, characterized in that: The steps include: A second selection device S2 is provided in parallel at both ends of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, for selecting a half-bus voltage double pulse test or a short circuit test for the second IGBT tube Q2; When the second selection device S2 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4; When the second selection device S2 is set to the half-bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4.

5. A double pulse and short circuit test method for an NPC T-type three-level circuit, used to perform full bus voltage double pulse and short circuit tests on the first IGBT tube Q1 in the NPC T-type three-level circuit, characterized in that: The following steps are involved: A second selection device S2 is provided in parallel at both ends of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, for selecting the first IGBT tube Q1 to perform a full bus voltage double pulse test or a short circuit test; When the second selection device S2 is set to the full bus voltage double pulse test, a double pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4; When the second selection device S2 is set to the full bus voltage short-circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

6. A double pulse and short circuit test method for an NPC T-type three-level circuit, used to perform a full bus voltage double pulse and short circuit test on the second IGBT tube Q2 in the NPC T-type three-level circuit, characterized in that: The following steps are involved: A first selection device S1 is provided in parallel at both ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, for selecting the second IGBT tube Q2 to perform a full bus voltage double pulse test or a short circuit test; When the first selection device S1 is set to the full bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4; When the first selection device S1 is set to the full bus voltage short-circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

7. A double pulse and short circuit test method for an NPC T-type three-level circuit according to any one of claims 1 to 6, characterized in that: The first selection device S1 includes: a first converter SW1, a first inductor L1 and a first copper sheet U1; the first converter SW1 is used to connect the first inductor L1 in parallel to the two ends of the first IGBT tube Q1 during a full bus voltage or half bus voltage double pulse test; or to connect the first copper sheet U1 in parallel to the two ends of the first IGBT tube Q1 during a full bus voltage or half bus voltage short circuit test; The second selection device S2 includes: a second converter SW2, a second inductor L2 and a second copper sheet U2; the second converter SW2 is used to connect the second inductor L2 in parallel to the two ends of the second IGBT tube Q2 during a full bus voltage or half bus voltage double pulse test; or to connect the second copper sheet U2 in parallel to the two ends of the second IGBT tube Q2 during a full bus voltage or half bus voltage short circuit test; The third selection device S3 includes: a third converter SW3, a third inductor L3 and a third copper sheet U3; the third converter SW3 is used to connect the third inductor L3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during the half-bus double pulse test; or to connect the third copper sheet U3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during the half-bus short circuit test.

8. A double pulse and short circuit test device for an NPC T-type three-level circuit, used for performing a half-bus voltage double pulse and short circuit test on a first IGBT tube Q1 or a second IGBT tube Q2 in a test circuit of an NPC T-type three-level circuit, characterized in that: include: The third selection device S3 is arranged in parallel between the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 which are connected in sequence in the test circuit of the NPC T-type three-level circuit; it is used to select the first IGBT tube Q1 or the second IGBT tube Q2 to perform half-bus voltage double pulse test and short circuit test.

9. A double pulse and short circuit test device for an NPC T-type three-level circuit, used for performing a half bus voltage double pulse and short circuit test on a third IGBT tube Q3 in a test circuit of an NPC T-type three-level circuit, or for performing a full bus voltage double pulse and short circuit test on a second IGBT tube Q2 in a test circuit of an NPC T-type three-level circuit, characterized in that: include: The first selection device S1 is arranged in parallel at both ends of the first IGBT tube Q1; it is used to select the half bus voltage double pulse test and short circuit test for the third IGBT tube Q3, or to perform the full bus voltage double pulse and short circuit test for the second IGBT tube Q2.

10. A double pulse and short circuit test device for an NPC T-type three-level circuit, used for performing a half bus voltage double pulse and short circuit test on a fourth IGBT tube Q4 in a test circuit of an NPC T-type three-level circuit, or for performing a full bus voltage double pulse and short circuit test on a first IGBT tube Q1 in a test circuit of an NPC T-type three-level circuit, characterized in that: include: The second selection device S2 is arranged in parallel at both ends of the second IGBT tube Q2; it is used to select the half bus voltage double pulse test and short circuit test for the fourth IGBT tube Q4, or to perform the full bus voltage double pulse and short circuit test on the first IGBT tube Q1.

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