A method and device for testing thermal resistance of power semiconductor

Abstract

The present invention discloses a method and device for testing thermal resistance of power semiconductors. The first temperature data of a power semiconductor from a current-off state to a conducting state is obtained in a preset heat dissipation environment, and the first temperature data indicates the thermal resistance characteristics of the power semiconductor in the conducting state, and then a first thermal resistance curve of the power semiconductor is obtained based on the first temperature data; the second temperature data of a power semiconductor from a current-on state to a closed state is obtained in the preset heat dissipation environment, and the second temperature data indicates the thermal resistance characteristics of the power semiconductor in the current-off state, and then a second thermal resistance curve of the power semiconductor is obtained based on the second temperature data; the thermal resistance test result of the power semiconductor is obtained according to the first thermal resistance curve and the second thermal resistance curve, so that the thermal resistance test result fully describes the thermal behavior information of the power semiconductor in the process of different current state changes, so that the test result of the thermal resistance test of the power semiconductor is more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of thermal resistance testing, and in particular to a method and device for testing thermal resistance of a power semiconductor. Background Art

[0002] The electric vehicle motor drive system is an important part of the vehicle's power domain and is responsible for the vehicle's power conversion output. The power module is the core of the motor drive system, and the performance of the power module will directly affect the vehicle's power performance. For power semiconductors, the wafer junction temperature is an important factor in determining its reliability and life. Only by ensuring that the power semiconductors of the power module operate at a safe junction temperature can the vehicle be driven safely and reliably. It is particularly important to test and evaluate the junction temperature of the power module.

[0003] The existing semiconductor thermal resistance test method calculates the wafer junction temperature of the power semiconductor at a specific operating voltage through a test device, and then calculates the steady-state thermal resistance of the semiconductor based on the wafer junction temperature. However, in actual applications, power semiconductors often undergo rapid switching processes and their temperatures change rapidly. Steady-state thermal resistance cannot provide information about the thermal behavior of the device during these transient processes, resulting in inaccurate power semiconductor thermal resistance testing. Summary of the invention

[0004] The invention provides a method and a device for testing thermal resistance of a power semiconductor, so as to improve the accuracy and precision of the thermal resistance test of the power semiconductor.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a power semiconductor thermal resistance testing method, comprising:

[0006] Acquire first temperature data of the power semiconductor based on a preset first current change rule and a preset heat dissipation environment; and acquire a first thermal resistance curve of the power semiconductor based on the first temperature data; the first current change rule is that a preset test current changes from an off state to an on state;

[0007] Acquire second temperature data of the power semiconductor based on a preset second current change rule and the heat dissipation environment; and acquire a second thermal resistance curve of the power semiconductor based on the second temperature data; the second current change rule is that a preset test current changes from an on state to an off state;

[0008] A thermal resistance test result of the power semiconductor is obtained based on the first thermal resistance curve and the second thermal resistance curve.

[0009] The present invention obtains first temperature data of a power semiconductor from a current-off state to a current-on state in a preset heat dissipation environment, and the first temperature data indicates the thermal resistance characteristics of the power semiconductor in the on state, and then obtains a first thermal resistance curve of the power semiconductor based on the first temperature data, and the first thermal resistance curve reflects the thermal behavior information of the power semiconductor in the preset heat dissipation environment and the current conduction change process; obtains second temperature data of the power semiconductor from a current-on state to a closed state in the preset heat dissipation environment, and the second temperature data indicates the thermal resistance characteristics of the power semiconductor in the current-off state, and then obtains a second thermal resistance curve of the power semiconductor based on the second temperature data, and the second thermal resistance curve reflects the thermal behavior information of the power semiconductor in the preset heat dissipation environment and the current-off change process; obtains the thermal resistance test result of the power semiconductor according to the first thermal resistance curve and the second thermal resistance curve, so that the thermal resistance test result comprehensively describes the thermal behavior information of the power semiconductor in the process of different current state changes, so that the test result of the thermal resistance test of the power semiconductor is more accurate.

[0010] Further, the acquiring first temperature data of the power semiconductor based on a preset first current variation rule and a preset heat dissipation environment, and acquiring a first thermal resistance curve of the power semiconductor based on the first temperature data, includes:

[0011] Controlling the first test current of the power semiconductor to switch states based on the first current change rule, and obtaining the first heat dissipation, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the change of the first test current based on the heat dissipation environment and a preset synchronization clock signal;

[0012] First temperature data is acquired based on the first heat dissipation, the first heat dissipation temperature, and the first wafer junction temperature, and a first thermal resistance curve of the power semiconductor is generated by fitting based on the first temperature data.

[0013] The present invention controls the power semiconductor test current through a first current change rule, monitors and records the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor in the test current change process in real time through a synchronous clock signal, so as to obtain first temperature data, and the first temperature data reflects the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor in the process from when the test current is turned off to when the test current is turned on; and then generates a first thermal resistance curve according to the first temperature data, so as to represent the thermal behavior information of the power semiconductor in the process from when the current is turned off to when the test current is turned on according to the first thermal resistance curve.

[0014] Further, the acquiring second temperature data of the power semiconductor based on the preset second current change rule and the heat dissipation environment, and acquiring a second thermal resistance curve of the power semiconductor based on the second temperature data, includes:

[0015] Controlling the test current of the power semiconductor based on the second current change rule, and obtaining the first heat dissipation, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the first test current change process based on the heat dissipation environment and a preset synchronization clock signal;

[0016] Second temperature data is acquired based on the second heat dissipation, the second heat dissipation temperature and the second wafer junction temperature, and a second thermal resistance curve of the power semiconductor is generated by fitting based on the second temperature data.

[0017] The present invention controls the power semiconductor test current through a second current change rule, monitors and records the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor in the test current change process in real time through a synchronous clock signal, so as to obtain second temperature data, which reflects the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor in the process of changing from the test current being turned on to the test current being turned off; and then generates a first thermal resistance curve according to the first temperature data, so as to represent the thermal behavior information of the power semiconductor in the process of changing from the current being turned off to the test current being turned on according to the first thermal resistance curve.

[0018] Further, obtaining a thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve includes:

[0019] Acquire a first dynamic thermal impedance of the power semiconductor based on the first thermal resistance curve, and acquire a first equilibrium thermal resistance of the power semiconductor based on the first dynamic thermal impedance;

[0020] Acquire a second dynamic thermal impedance of the power semiconductor based on the second thermal resistance curve, and acquire a second equilibrium thermal resistance of the power semiconductor based on the second dynamic thermal impedance;

[0021] A thermal resistance test result of the power semiconductor is obtained based on the first balanced thermal resistance, the second balanced thermal resistance, the first dynamic thermal impedance, and the second dynamic thermal impedance.

[0022] The present invention obtains the dynamic thermal impedance and the balanced thermal resistance of the power semiconductor in the on and off states by analyzing the first thermal resistance curve and the second thermal resistance curve, and comprehensively evaluates the thermal resistance characteristics of the power semiconductor based on the dynamic thermal impedance and the balanced thermal resistance. The dynamic thermal impedance and the balanced thermal resistance accurately reflect the thermal behavior of the power semiconductor in the fast switching process, improve the accuracy and precision of the thermal resistance test, and provide an important basis for the thermal performance evaluation and optimization of the device.

[0023] Furthermore, before obtaining the thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve, the method further includes:

[0024] A steady-state thermal resistance of the power semiconductor is acquired based on the first temperature data and the second temperature data.

[0025] In a second aspect, the present invention provides a power semiconductor thermal resistance testing device, comprising: a first testing module, a second testing module and a testing result generating module;

[0026] The first test module is used to obtain first temperature data of the power semiconductor based on a preset first current change rule and a preset heat dissipation environment, and to obtain a first thermal resistance curve of the power semiconductor based on the first temperature data; the first current change rule is that a preset test current changes from an off state to an on state;

[0027] The second test module is used to obtain second temperature data of the power semiconductor based on a preset second current change rule and the heat dissipation environment, and to obtain a second thermal resistance curve of the power semiconductor based on the second temperature data; the second current change rule is that the preset test current changes from an on state to an off state;

[0028] The test generation is used to obtain a thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve.

[0029] Furthermore, the first test module is used to:

[0030] Controlling the first test current of the power semiconductor to switch states based on the first current change rule, and obtaining the first heat consumption, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the state switching of the first test current based on the heat dissipation environment and a preset first synchronization clock signal;

[0031] First temperature data is acquired based on the first heat dissipation, the first heat dissipation temperature, and the first wafer junction temperature, and a first thermal resistance curve of the power semiconductor is generated by fitting based on the first temperature data.

[0032] Furthermore, the second test module is used to:

[0033] Controlling the second test current of the power semiconductor to switch state based on the second current change rule, and obtaining the second heat dissipation, second heat dissipation temperature and second wafer junction temperature of the power semiconductor during the first test current state switching process based on the heat dissipation environment and a preset second synchronization clock signal;

[0034] Second temperature data is acquired based on the second heat dissipation, the second heat dissipation temperature and the second wafer junction temperature, and a second thermal resistance curve of the power semiconductor is generated by fitting based on the second temperature data.

[0035] Furthermore, the test generation is used to:

[0036] Acquire a first dynamic thermal impedance of the power semiconductor based on the first thermal resistance curve, and acquire a first equilibrium thermal resistance of the power semiconductor based on the first dynamic thermal impedance;

[0037] Acquire a second dynamic thermal impedance of the power semiconductor based on the second thermal resistance curve, and acquire a second equilibrium thermal resistance of the power semiconductor based on the second dynamic thermal impedance;

[0038] A thermal resistance test result of the power semiconductor is obtained based on the first balanced thermal resistance, the second balanced thermal resistance, the first dynamic thermal impedance, and the second dynamic thermal impedance.

[0039] Furthermore, the test generation is also used for:

[0040] A steady-state thermal resistance of the power semiconductor is acquired based on the first temperature data and the second temperature data. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a flow chart of a power semiconductor thermal resistance testing method provided by an embodiment of the present invention;

[0042] Figure 2 A schematic diagram of a thermal resistance curve provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0044] The terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0045] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] Example 1

[0047] See also Figure 1 , Figure 1 A schematic flow chart of a power semiconductor thermal resistance testing method provided by an embodiment of the present invention. The present invention provides a power semiconductor thermal resistance testing method, including steps 101 to 103, which are as follows:

[0048] Step 101: acquiring first temperature data of a power semiconductor based on a preset first current change rule and a preset heat dissipation environment, and acquiring a first thermal resistance curve of the power semiconductor based on the first temperature data; the first current change rule is that a preset test current changes from an off state to an on state;

[0049] Step 102: acquiring second temperature data of the power semiconductor based on a preset second current change rule and the heat dissipation environment, and acquiring a second thermal resistance curve of the power semiconductor based on the second temperature data; the second current change rule is that a preset test current changes from an on state to an off state;

[0050] Step 103: Acquire a thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve.

[0051] In this embodiment, before testing, the power semiconductor to be tested is pre-processed according to preset spraying rules so that the exposed wafer and bonding wires of the power semiconductor are evenly sprayed with a layer of insulating black paint, thereby making the heat spectrum of the exposed wafer of the power semiconductor balanced and improving the detection accuracy of the wafer junction temperature of the power semiconductor.

[0052] In this embodiment, the spray coating rule includes opening the power semiconductor package shell and uniformly spraying a layer of insulating black paint on the exposed wafer and bonding wire of the power semiconductor on the DBC substrate. And after the power semiconductor packaging process reaches the terminal ultrasonic welding, no subsequent silicone gel filling and curing treatment is performed.

[0053] In this embodiment, the power semiconductor includes a MOSFET / IGBT / DIODEC chip.

[0054] In this embodiment, during the test, the pre-treated power semiconductor is moved to a preset heat dissipation environment and subjected to a power semiconductor thermal resistance test.

[0055] In this embodiment, the step of acquiring first temperature data of the power semiconductor based on a preset first current variation rule and a preset heat dissipation environment, and acquiring a first thermal resistance curve of the power semiconductor based on the first temperature data includes:

[0056] Controlling the first test current of the power semiconductor to switch states based on the first current change rule, and obtaining the first heat consumption, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the state switching of the first test current based on the heat dissipation environment and a preset first synchronization clock signal;

[0057] First temperature data is acquired based on the first heat dissipation, the first heat dissipation temperature, and the first wafer junction temperature, and a first thermal resistance curve of the power semiconductor is generated by fitting based on the first temperature data.

[0058] In this embodiment, the power semiconductor test current is controlled by a first current change rule, and the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor during the test current change process are monitored and recorded in real time through a synchronous clock signal to obtain first temperature data, which reflects the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor during the process from when the test current is turned off to when the test current is turned on; and then a first thermal resistance curve is generated by fitting according to the first temperature data to represent the thermal behavior information of the power semiconductor during the process from when the current is turned off to when the test current is turned on according to the first thermal resistance curve.

[0059] In this embodiment, the pre-treated power semiconductor is moved to a preset heat dissipation environment, and the power semiconductor is forward-conducted in the circuit, at which time no current flows in the circuit. Subsequently, the external current source is turned on, so that the current state changes from the off state to the on state, so that a constant current flows into the power semiconductor; then a high-precision ammeter is used to detect the actual current value flowing into the power module, and a high-precision voltmeter is used to detect the actual on-state voltage drop across the power module.

[0060] In this embodiment, the first heat consumption of the current power module is calculated by the voltage drop across the power semiconductor.

[0061] In this embodiment, a high-precision infrared thermal imager is used to record a preset wafer area in a power semiconductor to detect the wafer junction temperature of the power semiconductor, and the highest junction temperature of the exposed wafer at each moment is used as the wafer junction temperature of the power semiconductor at that moment.

[0062] In this embodiment, a timing device is used to ensure that all monitoring devices are synchronized in the time domain so as to record the relationship between each data and time. When the test current is input into the power semiconductor, the heat dissipation, heat dissipation temperature and wafer junction temperature of the power semiconductor at each moment are monitored, and the first heat dissipation, first heat dissipation temperature and first wafer junction temperature of the power semiconductor are obtained to generate the first temperature data. That is, the first temperature data includes the first heat dissipation, first heat dissipation temperature and first wafer junction temperature corresponding to all moments from the start of the test to the end of the test, and the first temperature data is generated.

[0063] In this embodiment, the heat dissipation temperature is the cooling temperature of the heat dissipation environment. For example, if the heat dissipation environment is a cooling liquid, the heat dissipation temperature is the cooling liquid temperature.

[0064] Please refer to Figure 2 , Figure 2 A schematic diagram of a thermal resistance curve provided by an embodiment of the present invention.

[0065] In this embodiment, data fitting is performed according to the heat dissipation system temperature, wafer junction temperature, and heat consumption in the first temperature data to generate a first thermal resistance curve.

[0066] In this embodiment, the power semiconductor test current is controlled by a second current change rule, and the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor during the test current change process are monitored and recorded in real time through a synchronous clock signal to obtain second temperature data, which reflects the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor during the process from when the test current is turned on to when the test current is turned off; and then a second thermal resistance curve is generated by fitting according to the second temperature data to represent the thermal behavior information of the power semiconductor during the process from when the current is turned off to when the test current is turned on according to the second thermal resistance curve.

[0067] In this embodiment, the first thermal resistance curve represents the change of the thermal impedance of the power semiconductor over time during the process from current shut-off to current conduction.

[0068] In this embodiment, the acquiring second temperature data of the power semiconductor based on the preset second current change rule and the heat dissipation environment, and acquiring a second thermal resistance curve of the power semiconductor based on the second temperature data, includes:

[0069] Controlling the test current of the power semiconductor based on the second current change rule, and obtaining the first heat dissipation, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the first test current change process based on the heat dissipation environment and a preset synchronization clock signal;

[0070] Second temperature data is acquired based on the second heat dissipation, the second heat dissipation temperature and the second wafer junction temperature, and a second thermal resistance curve of the power semiconductor is generated by fitting based on the second temperature data.

[0071] In this embodiment, the pre-treated power semiconductor is moved to a preset heat dissipation environment, and the power semiconductor is forward-conducted into the circuit, and a preset constant test current is input into the power semiconductor. After a certain period of time, a constant current flows through the circuit. At this time, the external current source is disconnected, so that the current state changes from the on state to the off state; then a high-precision ammeter is used to detect the actual current value flowing into the power module, and a high-precision voltmeter is used to detect the actual on-state voltage drop across the power module.

[0072] In this embodiment, after the current input time reaches a preset time threshold, the first thermal resistance test is terminated.

[0073] In this embodiment, the second heat dissipation of the current power module is calculated by the voltage drop across the power semiconductor.

[0074] In this embodiment, a high-precision infrared thermal imager is used to record a preset wafer area in a power semiconductor to detect the wafer junction temperature of the power semiconductor, and the highest junction temperature of the exposed wafer at each moment is used as the wafer junction temperature of the power semiconductor at that moment.

[0075] In this embodiment, a timing device is used to ensure that all monitoring devices are synchronized in the time domain so as to record the relationship between each data and time. When the test current is input into the power semiconductor and the power connection is disconnected after a certain period of time, the power semiconductor's heat consumption, heat dissipation temperature and wafer junction temperature are monitored at each moment before the external power input is disconnected, and the second heat consumption, second heat dissipation temperature and second wafer junction temperature of the power semiconductor are obtained to generate the second temperature data. That is, the second temperature data includes the second heat consumption, second heat dissipation temperature and second wafer junction temperature corresponding to all moments from the start of the test to the end of the test, and the second temperature data is generated.

[0076] In this embodiment, after the current disconnection time reaches a preset time threshold, the first thermal resistance test is terminated.

[0077] In this embodiment, the heat dissipation temperature is the cooling temperature of the heat dissipation environment. For example, if the heat dissipation environment is a cooling liquid, the heat dissipation temperature is the cooling liquid temperature.

[0078] In this embodiment, the power semiconductor test current is controlled by a second current change rule, and the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor during the test current change process are monitored and recorded in real time through a synchronous clock signal to obtain second temperature data, which reflects the heat consumption, heat dissipation temperature and wafer junction temperature of the power semiconductor during the change from test current conduction to test current shutdown; and then a first thermal resistance curve is generated by fitting according to the first temperature data to represent the thermal behavior information of the power semiconductor during the change from current shutdown to test current conduction according to the first thermal resistance curve.

[0079] In this embodiment, before acquiring the thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve, the method further includes:

[0080] A steady-state thermal resistance of the power semiconductor is acquired based on the first temperature data and the second temperature data.

[0081] In this embodiment, the steady-state thermal resistance is calculated based on the heat dissipation system temperature, the wafer junction temperature, and the heat dissipation. Specifically:

[0082]

[0083] Where R th The steady-state thermal resistance of the power semiconductor wafer, T junction Represents the wafer junction temperature of the power semiconductor, T coolant Indicates the cooling temperature of the heat dissipation system, P calorific Indicates the heat generated by power semiconductors.

[0084] In this embodiment, since thermal resistance is a static parameter, it describes the material's ability to block heat flow under steady-state conditions. It does not consider the time factor and only reflects the performance of the system in a thermal equilibrium state. Thermal behavior cannot be fully described by thermal resistance analysis alone. Thermal impedance is a dynamic parameter that takes the time factor into account and describes the thermal response characteristics of the system under non-steady-state conditions. This makes thermal impedance more important in analyzing dynamic thermal processes, transient thermal management, and periodic heat loads.

[0085] In this embodiment, obtaining a thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve includes:

[0086] Acquire a first dynamic thermal impedance of the power semiconductor based on the first thermal resistance curve, and acquire a first equilibrium thermal resistance of the power semiconductor based on the first dynamic thermal impedance;

[0087] Acquire a second dynamic thermal impedance of the power semiconductor based on the second thermal resistance curve, and acquire a second equilibrium thermal resistance of the power semiconductor based on the second dynamic thermal impedance;

[0088] A thermal resistance test result of the power semiconductor is obtained based on the first balanced thermal resistance, the second balanced thermal resistance, the first dynamic thermal impedance, and the second dynamic thermal impedance.

[0089] In this embodiment, a dynamic thermal resistance equation is constructed, and a first thermal resistance curve is generated by fitting the dynamic thermal resistance equation and the first temperature data, so as to obtain the dynamic thermal impedance at each moment.

[0090] In this embodiment, the dynamic thermal resistance equation is:

[0091]

[0092] Among them, Z th (t) represents the dynamic thermal impedance from the power semiconductor wafer to the heat dissipation system, R th The thermal resistance of the power semiconductor wafer, C threpresents the thermal melting of the power semiconductor wafer, and τ represents the time constant τ=R th *C th .

[0093] In this embodiment, during the test current input process, the dynamic thermal impedance Z changes with time function. th (t) will eventually stabilize and form a steady-state thermal resistance R th .

[0094] In this embodiment, during the first current test, the current source is turned off and then on at a constant current, and the wafer junction temperature rises from the cooling temperature to the stable state to reach a dynamic thermal equilibrium. When the dynamic thermal equilibrium is reached, the dynamic thermal impedance Z th (t) will eventually stabilize and form a steady-state thermal resistance, i.e., the first equilibrium thermal resistance.

[0095] In this embodiment, during the second current test, the current source is continuously turned on and off from a constant current, accompanied by the change of the wafer junction temperature from reaching dynamic thermal equilibrium to dropping to the cooling temperature. When the wafer junction temperature is cooled, the test is stopped, and the dynamic thermal impedance of the wafer junction temperature in the dynamic thermal equilibrium state is several times the second equilibrium thermal resistance.

[0096] In this embodiment, by analyzing the first thermal resistance curve and the second thermal resistance curve, the dynamic thermal impedance and the balanced thermal resistance of the power semiconductor in the on and off states are obtained, and the thermal resistance characteristics of the power semiconductor are comprehensively evaluated based on the dynamic thermal impedance and the balanced thermal resistance. The dynamic thermal impedance and the balanced thermal resistance are used to accurately reflect the thermal behavior of the power semiconductor in the fast switching process, improve the accuracy and precision of the thermal resistance test, and provide an important basis for the thermal performance evaluation and optimization of the device.

[0097] The embodiment of the present invention further provides a power semiconductor thermal resistance testing device, comprising: a first testing module, a second testing module and a testing result generating module;

[0098] The first test module is used to obtain first temperature data of the power semiconductor based on a preset first current change rule and a preset heat dissipation environment, and to obtain a first thermal resistance curve of the power semiconductor based on the first temperature data; the first current change rule is that a preset test current changes from an off state to an on state;

[0099] The second test module is used to obtain second temperature data of the power semiconductor based on a preset second current change rule and the heat dissipation environment, and to obtain a second thermal resistance curve of the power semiconductor based on the second temperature data; the second current change rule is that the preset test current changes from an on state to an off state;

[0100] The test generation is used to obtain a thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve.

[0101] In this embodiment, the first test module is used to:

[0102] Controlling the first test current of the power semiconductor to switch states based on the first current change rule, and obtaining the first heat consumption, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the state switching of the first test current based on the heat dissipation environment and a preset first synchronization clock signal;

[0103] First temperature data is acquired based on the first heat dissipation, the first heat dissipation temperature, and the first wafer junction temperature, and a first thermal resistance curve of the power semiconductor is generated by fitting based on the first temperature data.

[0104] In this embodiment, the second test module is used to:

[0105] Controlling the second test current of the power semiconductor to switch state based on the second current change rule, and obtaining the second heat dissipation, second heat dissipation temperature and second wafer junction temperature of the power semiconductor during the first test current state switching process based on the heat dissipation environment and a preset second synchronization clock signal;

[0106] Second temperature data is acquired based on the second heat dissipation, the second heat dissipation temperature and the second wafer junction temperature, and a second thermal resistance curve of the power semiconductor is generated by fitting based on the second temperature data.

[0107] In this embodiment, the test generation is used to:

[0108] Acquire a first dynamic thermal impedance of the power semiconductor based on the first thermal resistance curve, and acquire a first equilibrium thermal resistance of the power semiconductor based on the first dynamic thermal impedance;

[0109] Acquire a second dynamic thermal impedance of the power semiconductor based on the second thermal resistance curve, and acquire a second equilibrium thermal resistance of the power semiconductor based on the second dynamic thermal impedance;

[0110] A thermal resistance test result of the power semiconductor is obtained based on the first balanced thermal resistance, the second balanced thermal resistance, the first dynamic thermal impedance, and the second dynamic thermal impedance.

[0111] In this embodiment, the test generation is also used for:

[0112] A steady-state thermal resistance of the power semiconductor is acquired based on the first temperature data and the second temperature data.

[0113] The embodiment of the present invention further provides a power semiconductor thermal resistance test circuit, which is used to implement the power semiconductor thermal resistance test method, and includes a current detection module, a voltage detection module, a constant current power supply, a module to be tested and a processing module;

[0114] The module to be tested is arranged in series with the current detection module to form a test loop, and the voltage detection module is arranged in series with the module to be tested; the module to be tested is placed in a heat dissipation module.

[0115] In this embodiment, the module to be tested is used to place the power semiconductor to be tested. The power semiconductor needs to be externally connected to a driving module, and the driving module is used to switch the current state of the input power semiconductor.

[0116] In this embodiment, the heat dissipation module can be configured as a water-cooled heat dissipation module, in which a coolant is provided, and the coolant is used as a heat dissipation environment for the power semiconductor.

[0117] In this embodiment, a stable coolant temperature and flow rate are set, such as 25°C and a flow rate of 10L / min, so that the power module is placed in the dedicated heat dissipation water channel of the heat dissipation module. The power semiconductor is a MOS tube. When testing, the MOS tube on the water inlet side is tested in sequence: the positive pole of the constant current source is connected to the input end of the current detection module, the output end of the current detection module is connected to the power drain terminal of the MOS tube to be tested, and the power source terminal of the MOS tube is connected back to the negative pole of the constant current source. At the same time, the positive and negative input ends of the voltage detection module are respectively connected to the Kelvin drain and Kelvin source of the MOS tube, and the driving module is connected to the gate-Kelvin source of the MOS tube. In addition, a high-precision infrared thermal imager is set up directly above the MOS tube, and the focus is selected to the MOS tube chip wafer to be tested. After that, the driving voltage is controlled to be continuously output, so that the MOS tube works in the deep ohmic region, and then the constant current source output current is set to allow the current to flow through the drain-source of the MOS tube. At this time, the heating power of the current MOS tube is calculated according to the measured values ​​after the electrical measurement monitoring module and the current detection module are stabilized. At the same time, the highest temperature of the MOS tube wafer area is monitored by the high-precision infrared thermal imager, and the highest junction temperature of the current chip wafer area after stabilization is recorded. Finally, the steady-state thermal resistance is calculated based on the coolant temperature, wafer junction temperature, and heating power.

[0118] In this embodiment, the transient test is repeated twice. The first test is a process in which the current source is turned off and turned on at a constant current, accompanied by the junction temperature rising from the coolant temperature to the thermal equilibrium stable temperature; the second test is a process in which the current source is turned on and off at a constant current, accompanied by the junction temperature falling from the thermal equilibrium stable temperature to the coolant temperature. The curve of the chip junction temperature changing with time is recorded by an infrared thermal imager, and the functional relationship between thermal resistance and thermal capacitance is obtained by using a software fitting tool, so as to obtain the transient thermal impedance using the thermal impedance calculation formula.

[0119] In this embodiment, in order to improve the junction temperature estimation accuracy, the parallel MOS tube chips can also be divided into a single wafer. For example, for MOS tubes with several chips connected in parallel, the thermal resistance is divided into wafer-level, which can better obtain more accurate thermal resistance and thermal impedance data based on the current sharing characteristics.

[0120] In an embodiment of the present invention, a terminal device is also provided, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above-mentioned power semiconductor thermal resistance testing method when executing the computer program.

[0121] In an embodiment of the present invention, a computer-readable storage medium is further provided. The computer-readable storage medium includes a stored computer program. When the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the above-mentioned power semiconductor thermal resistance testing method.

[0122] Exemplarily, the computer program can be divided into one or more modules, one or more modules are stored in a memory and executed by a processor to complete the present invention. One or more modules can be a series of computer program instruction segments that can complete specific functions, and the instruction segments are used to describe the execution process of the computer program in the power semiconductor thermal resistance test device.

[0123] The power semiconductor thermal resistance test equipment can be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The power semiconductor thermal resistance test equipment may include, but is not limited to, a processor, a memory, and a display. Those skilled in the art will understand that the above components are merely examples of power semiconductor thermal resistance test equipment and do not constitute a limitation on power semiconductor thermal resistance test equipment. It may include more or fewer components than the components, or a combination of certain components, or different components. For example, the power semiconductor thermal resistance test equipment may also include input and output devices, network access devices, buses, etc.

[0124] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the power semiconductor thermal resistance test equipment, and uses various interfaces and lines to connect various parts of the entire power semiconductor thermal resistance test equipment.

[0125] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the power semiconductor thermal resistance test equipment by running or executing the computer programs and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, a text conversion function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, text message data, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Med ia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0126] Wherein, if the module based on the thermal resistance test of power semiconductor is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. Computer-readable media can include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0127] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for testing thermal resistance of a power semiconductor, characterized in that: include: Acquire first temperature data of the power semiconductor based on a preset first current variation rule and a preset heat dissipation environment, and acquire a first thermal resistance curve of the power semiconductor based on the first temperature data; The first current change rule is that the preset test current changes from an off state to an on state; Acquire second temperature data of the power semiconductor based on a preset second current change rule and the heat dissipation environment, and acquire a second thermal resistance curve of the power semiconductor based on the second temperature data; the second current change rule is that a preset test current changes from an on state to an off state; A thermal resistance test result of the power semiconductor is obtained based on the first thermal resistance curve and the second thermal resistance curve.

2. A power semiconductor thermal resistance testing method as claimed in claim 1, characterized in that: The step of acquiring first temperature data of the power semiconductor based on a preset first current variation rule and a preset heat dissipation environment, and acquiring a first thermal resistance curve of the power semiconductor based on the first temperature data, includes: Controlling the first test current of the power semiconductor to switch states based on the first current change rule, and obtaining the first heat consumption, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the state switching of the first test current based on the heat dissipation environment and a preset first synchronization clock signal; First temperature data is acquired based on the first heat dissipation, the first heat dissipation temperature, and the first wafer junction temperature, and a first thermal resistance curve of the power semiconductor is generated by fitting based on the first temperature data.

3. A power semiconductor thermal resistance testing method as claimed in claim 2, characterized in that: The step of acquiring second temperature data of the power semiconductor based on a preset second current variation rule and the heat dissipation environment, and acquiring a second thermal resistance curve of the power semiconductor based on the second temperature data, includes: Controlling the second test current of the power semiconductor to switch state based on the second current change rule, and obtaining the second heat dissipation, second heat dissipation temperature and second wafer junction temperature of the power semiconductor during the first test current state switching process based on the heat dissipation environment and a preset second synchronization clock signal; Second temperature data is acquired based on the second heat dissipation, the second heat dissipation temperature and the second wafer junction temperature, and a second thermal resistance curve of the power semiconductor is generated by fitting based on the second temperature data.

4. A power semiconductor thermal resistance testing method as claimed in claim 3, characterized in that: The obtaining a thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve includes: Acquire a first dynamic thermal impedance of the power semiconductor based on the first thermal resistance curve, and acquire a first equilibrium thermal resistance of the power semiconductor based on the first dynamic thermal impedance; Acquire a second dynamic thermal impedance of the power semiconductor based on the second thermal resistance curve, and acquire a second equilibrium thermal resistance of the power semiconductor based on the second dynamic thermal impedance; A thermal resistance test result of the power semiconductor is obtained based on the first balanced thermal resistance, the second balanced thermal resistance, the first dynamic thermal impedance, and the second dynamic thermal impedance.

5. A power semiconductor thermal resistance testing method as claimed in claim 4, characterized in that: Before obtaining the thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve, the method further includes: A steady-state thermal resistance of the power semiconductor is acquired based on the first temperature data and the second temperature data.

6. A power semiconductor thermal resistance testing device, characterized in that: include: A first test module, a second test module and a test result generating module; The first test module is used to obtain first temperature data of the power semiconductor based on a preset first current change rule and a preset heat dissipation environment, and to obtain a first thermal resistance curve of the power semiconductor based on the first temperature data; The first current change rule is that the preset test current changes from an off state to an on state; The second test module is used to obtain second temperature data of the power semiconductor based on a preset second current change rule and the heat dissipation environment, and to obtain a second thermal resistance curve of the power semiconductor based on the second temperature data; the second current change rule is that the preset test current changes from an on state to an off state; The test generation is used to obtain a thermal resistance test result of the power semiconductor based on the first thermal resistance curve and the second thermal resistance curve.

7. A power semiconductor thermal resistance testing device as claimed in claim 6, characterized in that: The first test module is used to: Controlling the first test current of the power semiconductor to switch states based on the first current change rule, and obtaining the first heat consumption, the first heat dissipation temperature and the first wafer junction temperature of the power semiconductor during the state switching of the first test current based on the heat dissipation environment and a preset first synchronization clock signal; First temperature data is acquired based on the first heat dissipation, the first heat dissipation temperature, and the first wafer junction temperature, and a first thermal resistance curve of the power semiconductor is generated by fitting based on the first temperature data.

8. A power semiconductor thermal resistance testing device as claimed in claim 7, characterized in that: The second test module is used to: Controlling the second test current of the power semiconductor to switch state based on the second current change rule, and obtaining the second heat dissipation, second heat dissipation temperature and second wafer junction temperature of the power semiconductor during the first test current state switching process based on the heat dissipation environment and a preset second synchronization clock signal; Second temperature data is acquired based on the second heat dissipation, the second heat dissipation temperature and the second wafer junction temperature, and a second thermal resistance curve of the power semiconductor is generated by fitting based on the second temperature data.

9. A power semiconductor thermal resistance testing device as claimed in claim 8, characterized in that: The test is generated to: Acquire a first dynamic thermal impedance of the power semiconductor based on the first thermal resistance curve, and acquire a first equilibrium thermal resistance of the power semiconductor based on the first dynamic thermal impedance; Acquire a second dynamic thermal impedance of the power semiconductor based on the second thermal resistance curve, and acquire a second equilibrium thermal resistance of the power semiconductor based on the second dynamic thermal impedance; A thermal resistance test result of the power semiconductor is obtained based on the first balanced thermal resistance, the second balanced thermal resistance, the first dynamic thermal impedance, and the second dynamic thermal impedance.

10. A power semiconductor thermal resistance testing device as claimed in claim 9, characterized in that: The test generator is also used to: A steady-state thermal resistance of the power semiconductor is acquired based on the first temperature data and the second temperature data.

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