Chip detection method, device, storage medium and system

Abstract

The present invention provides a chip detection method, device, storage medium and system. By designing an AND gate alarm circuit, while an analog-to-digital converter polls and collects voltage data, the AND gate alarm circuit monitors the voltage fluctuation of each power supply channel. If a power supply channel generates voltage fluctuation, the AND gate alarm circuit is triggered to output a preset level to a controller, triggering an external interrupt of the controller, and then triggering the controller to control the switching of a multi-way selection switch, so that the analog-to-digital converter measures the voltage value of the target power supply channel connected to the AND gate alarm circuit that outputs the preset level alone, and controls the power supply unit to power off when it is determined that the voltage value is abnormal. There is no need to wait for the analog-to-digital converter to measure the voltage value of the abnormal power supply channel in a preset order before the abnormality can be discovered. The abnormality detection efficiency can be improved, the abnormal power supply channel can be quickly located, and the power supply unit can be controlled to power off, thereby improving the safety of chip testing and avoiding losses caused by untimely power off.

Description

Technical Field

[0001] The present disclosure relates to automated testing technology, and in particular to a chip testing method, device, storage medium and system. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to test the various parameters of the device under test (DUT). After the finished product test is completed, the chips with normal parameters will be subjected to aging tests to eliminate aged and failed devices, thereby controlling the factory quality of semiconductor devices.

[0003] In the current chip testing system, the voltage detection unit mainly uses the analog to digital converter (ADC) chip or the peripheral ADC of the microcontroller unit (MCU) to perform voltage detection on the power channel of the chip to be tested and measure the voltage value of the power channel. In order to improve the detection efficiency, the power module is usually connected to a large number of chips to be tested to supply power for them, and the ADC switches channels through a multiplexer switch to poll and detect the voltage of the power channel corresponding to each chip to be tested.

[0004] However, in the process of polling and detecting each power supply channel in the above voltage detection method, if there is a power supply or chip abnormality, it may not be detected in time, resulting in damage to the chip to be tested. Summary of the invention

[0005] In response to the above technical problems, the embodiments of the present disclosure provide a chip detection method, device, storage medium and system, which can improve the efficiency of abnormality detection and improve the security of chip testing.

[0006] One aspect of the present disclosure provides a chip detection method.

[0007] A controller used in a chip detection system, the chip detection system comprising the controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter, the analog-to-digital converter being connected to a power supply channel via a multi-way selection switch and being used for polling and measuring the voltage of the power supply channel, the power supply channel being a circuit for connecting the power supply unit and a chip to be tested, the input end of the AND gate alarm circuit being connected to each of the power supply channels and the output end being connected to the controller, and being used for triggering an interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps; the method comprising:

[0008] In response to receiving the interrupt signal, determining a target power channel based on a connection relationship between the AND gate alarm circuit and the power channel;

[0009] Controlling the multi-way selection switch to switch so that the analog-to-digital converter is connected to the target power supply channel;

[0010] Acquire a target voltage measurement value of the target power supply channel acquired by the analog-to-digital converter;

[0011] In response to the existence of a target voltage measurement value that does not belong to a preset voltage value interval, the at least one power supply unit is controlled to be powered off and an alarm message is generated.

[0012] Optionally, the chip detection system includes n levels of AND gate alarm circuits, in each level of AND gate alarm circuits, the input end of each AND gate is connected to the output end of the corresponding AND gate in the previous level AND gate alarm circuit, and the output end of each AND gate is connected to the input end of the corresponding AND gate in the next level AND gate alarm circuit, wherein the input end of each AND gate of the first level AND gate alarm circuit is connected to the corresponding power supply channel respectively, and the output end of each AND gate of the nth level AND gate alarm circuit is connected to the corresponding port of the controller respectively, and n is an integer greater than 1;

[0013] The step of determining the target power channel in response to receiving the interrupt signal based on the connection relationship between the AND gate alarm circuit and the power channel comprises:

[0014] In response to receiving the interrupt signal, the target power channel is determined based on the connection relationship between each level of the AND gate alarm circuit and the power channel.

[0015] Optionally, different AND gates in the n-th level AND gate alarm circuit are respectively connected to different interrupt ports in the interrupt system;

[0016] The determining the target power channel based on the connection relationship between the AND gate alarm circuits at various levels and the power channel comprises:

[0017] Determine the interrupt port that generates the interrupt signal as the target interrupt port;

[0018] Determine a target AND gate alarm circuit based on the connection relationship of the AND gate alarm circuits at each level, wherein the target AND gate alarm circuit is the first level AND gate alarm circuit connected to the target interrupt port through the AND gate alarm circuits at other levels;

[0019] Based on the connection relationship between the first-level AND gate alarm circuit and the power channel, the power channel connected to the target AND gate alarm circuit is determined as the target power channel.

[0020] Optionally, after acquiring the target voltage measurement value of the target power channel acquired by the analog-to-digital converter, the method further includes:

[0021] Control the multi-way selection switch to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to other power supply channels in sequence and performs voltage value measurement;

[0022] Acquire and cache the voltage measurement values ​​of each of the other power supply channels;

[0023] In response to the existence of a voltage measurement value that does not belong to the preset voltage value interval, the at least one power supply unit is controlled to be powered off and the alarm information is generated.

[0024] Optionally, in response to receiving the interrupt signal, before determining a target alarm channel connected to the target AND gate alarm circuit based on a connection relationship between the AND gate alarm circuit and the power supply channel, the method further includes:

[0025] Control the multi-way selection switch to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to each power supply channel in turn and measures the voltage value;

[0026] Acquire and cache the voltage measurement value of each power supply channel;

[0027] In response to the existence of a voltage measurement value that does not belong to the preset voltage value interval, the at least one power supply unit is controlled to be powered off and the alarm information is generated.

[0028] Optionally, after controlling the at least one power supply unit to be powered off and generating alarm information in response to the existence of a target voltage measurement value that does not belong to a preset voltage value interval, the method includes:

[0029] In response to receiving a voltage detection query instruction sent by a host computer, sending the alarm information to the host computer through a preset communication protocol;

[0030] Among them, the alarm information includes the chip under test corresponding to the abnormal power channel, the power supply unit corresponding to the abnormal power channel and the target voltage measurement value corresponding to the abnormal power channel. The abnormal power channel is a target power channel whose target voltage measurement value does not belong to the preset voltage value range.

[0031] Another aspect of the embodiments of the present disclosure provides a chip detection device, which is applied to a controller in a chip detection system, wherein the chip detection system includes the controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter, wherein the analog-to-digital converter is connected to a power supply channel via a multi-way selection switch, and is used to poll and measure the voltage of the power supply channel, wherein the power supply channel is a circuit for connecting the power supply unit and a chip to be tested, wherein the input end of the AND gate alarm circuit is connected to each of the power supply channels and the output end is connected to the controller, and is used to trigger an interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps; the device includes:

[0032] a determination module, configured to determine a target power channel in response to receiving the interrupt signal and based on a connection relationship between the AND gate alarm circuit and the power channel;

[0033] A first control module, used for controlling the multi-way selection switch to switch so that the analog-to-digital converter is connected to the target power supply channel;

[0034] A first acquisition module, used for acquiring a target voltage measurement value of the target power supply channel acquired by the analog-to-digital converter;

[0035] The second control module is used to control the at least one power supply unit to power off and generate alarm information in response to the existence of a target voltage measurement value that does not belong to a preset voltage value interval.

[0036] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in the above aspects is implemented.

[0037] Another aspect of the embodiments of the present disclosure provides a chip detection system, including a controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter;

[0038] The analog-to-digital converter is connected to the power supply channel through a multi-way selection switch, and is used for polling and measuring the voltage of the power supply channel, wherein the power supply channel is a circuit for connecting the power supply unit and the chip to be tested;

[0039] The input end of the AND gate alarm circuit is connected to each of the power supply channels and the output end is connected to the controller, and is used to trigger the interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps;

[0040] The controller is used to execute the method described in the above aspects.

[0041] Optionally, the system includes n levels of AND gate alarm circuits, in each level of AND gate alarm circuits, the input end of each AND gate is connected to the output end of the corresponding AND gate in the previous level AND gate alarm circuit, and the output end of each AND gate is connected to the input end of the corresponding AND gate in the next level AND gate alarm circuit, wherein the input end of each AND gate of the first level AND gate alarm circuit is connected to the corresponding power supply channel, respectively, and the output end of each AND gate of the nth level AND gate alarm circuit is connected to the corresponding port of the controller, respectively, and n is an integer greater than 1.

[0042] Based on the embodiments of the present disclosure, an AND gate alarm circuit is designed. While the analog-to-digital converter polls and collects voltage data, the AND gate alarm circuit monitors the voltage fluctuation of each power supply channel. If the power supply channel generates voltage fluctuation, the AND gate alarm circuit is triggered to output a preset level to the controller, triggering the external interrupt of the controller, and then triggering the controller to control the switching of the multi-way selection switch, so that the analog-to-digital converter measures the voltage value of the target power supply channel connected to the AND gate alarm circuit that outputs the preset level separately, and controls the power supply unit to power off when it is determined that the voltage value is abnormal. There is no need to wait for the analog-to-digital converter to measure the voltage value of the abnormal power supply channel in a preset order before the abnormality can be discovered. The abnormality detection efficiency can be improved, the abnormal power supply channel can be quickly located, and the power supply unit can be controlled to power off, thereby improving the safety of chip testing and avoiding losses caused by untimely power-off.

[0043] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0045] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0046] Figure 1 This is a flow chart of an embodiment of the chip detection method disclosed in the present invention;

[0047] Figure 2 is a structural block diagram of an embodiment of the chip detection system disclosed in the present invention;

[0048] Figure 3 A schematic diagram of a multi-way selection switch provided in an embodiment of the present disclosure;

[0049] Figure 4 A schematic diagram of a two-stage AND gate alarm circuit provided in an embodiment of the present disclosure;

[0050] Figure 5 A flowchart of another embodiment of the chip detection method disclosed in the present invention;

[0051] Figure 6 is a structural block diagram of an embodiment of a chip detection device disclosed in the present invention;

[0052] Figure 7 is a structural block diagram of another embodiment of the chip detection device disclosed in the present invention;

[0053] Figure 8 This is a structural block diagram of another embodiment of the chip detection device disclosed in the present invention. DETAILED DESCRIPTION

[0054] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0055] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0056] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0057] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0058] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0059] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0060] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0061] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0062] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0063] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0064] Figure 1 The image processing method of the embodiment of the present disclosure can be applied to a controller in a chip detection system, such as Figure 2 As shown, the chip detection system includes a controller 201, at least one power supply unit 202, at least one AND gate alarm circuit 203 and an analog-to-digital converter 204. The analog-to-digital converter 204 is connected to the power supply channel through a multi-way selection switch 205, and is used to poll the power supply channel for voltage measurement. The power supply channel is a circuit for connecting the power supply unit 202 and the chip to be tested. The input end of the AND gate alarm circuit 203 is connected to each power supply channel and the output end is connected to the controller 201, and is used to trigger the interrupt system of the controller 201 to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps. Optionally, the analog-to-digital converter 204 can be an external converter or a converter inside the controller 201, which is not limited in the embodiment of the present disclosure.

[0065] The chip detection method comprises the following steps:

[0066] Step 101, in response to receiving an interrupt signal, determining a target power channel based on a connection relationship between an AND gate alarm circuit and a power channel.

[0067] In a possible implementation, when the voltage of each power channel is normal, the AND gate alarm circuit outputs a normal level (e.g., a high level), and when there is a voltage fluctuation in at least one power channel, the AND gate alarm circuit outputs a preset level (e.g., a low level), thereby triggering the interrupt system of the controller to generate an interrupt signal. When the interrupt signal is received, it is determined that there may be an abnormal power channel in the current power channel. When there are multiple AND gates in the AND gate alarm circuit, different AND gates are connected to different power channels. The controller can determine the part of the power channels connected to the AND gates that output the preset level as the target power channels based on the connection relationship between the AND gate alarm circuit and the power channels, and then determine the abnormal power channels from the target power channels.

[0068] Optionally, the AND gate alarm circuit may use a 2-and-1 AND gate, a 4-and-1 AND gate, or other types of AND gates. For example, when there are 16 power supply channels, the AND gate alarm circuit may use 4 4-and-1 AND gates to connect the 16 power supply channels, with the input end of each AND gate being connected to 4 power supply channels respectively, and the output end being connected to the port corresponding to the interrupt system of the controller.

[0069] Optionally, the controller may be a microcontroller unit (MCU), a system on chip (SOC), a microprocessor (MPU) or the like. The embodiments of the present disclosure are described using MCU as an example.

[0070] Step 102, controlling the multi-way selection switch to switch so that the analog-to-digital converter is connected to the target power supply channel.

[0071] Indicative, Figure 3 A schematic diagram of a 16-to-1 multi-way selector switch is shown. As shown in the figure, the 16 input terminals S1 to S16 of the multi-way selector switch are respectively connected to 16 power supply channels, and the output terminal D (16-1) is connected to an analog-to-digital converter. The controller can connect the output terminal D (16-1) to any input terminal of S1 to S16 by controlling the level of the four pins A0, A1, A2, and A3 in the multi-way selector switch. For example, by lowering the levels of A0 to A3, the analog-to-digital converter can be connected to the power supply channel corresponding to S1.

[0072] Under normal circumstances, the controller in the system controls the switch state of the multiplexer in a preset order, so that the analog to digital converter (ADC) collects the voltage value of each power channel in turn according to the preset order. When an interrupt signal is received, after determining the target power channel, the controller controls the multiplexer to switch, so that the analog to digital converter collects the voltage value of each target power channel in turn. For example Figure 3 The multi-way selection switch shown in the figure normally switches the levels of the four pins A0, A1, A2, and A3 in sequence, so that the ADC is connected to the 16 power supply channels S1 to S16 in sequence and measures the pressure. If the controller receives an interrupt signal and determines that the target power supply channel is the power supply channel corresponding to S5 to S8, the controller controls the output terminal D (16-1) of the multi-way selection switch to be connected to the input terminals S5, S6, S7, and S8 in sequence, so that the ADC measures the 4 target power supply channels corresponding to S5, S6, S7, and S8 in sequence.

[0073] Step 103: Acquire a target voltage measurement value of a target power supply channel acquired by an analog-to-digital converter.

[0074] Step 104 : in response to the existence of a target voltage measurement value that does not belong to a preset voltage value interval, control at least one power supply unit to be powered off and generate alarm information.

[0075] If the target voltage measurement values ​​of each target power supply channel are all within the preset voltage value range, it can be determined that this voltage fluctuation is a normal short-term fluctuation. If a target voltage measurement value that does not fall within the preset voltage value range is detected, it means that there is an abnormal power supply channel (which may be caused by an abnormal power supply unit, or by an abnormal chip or other device under test). The power supply unit corresponding to the power supply channel whose target voltage measurement value does not fall within the preset voltage value range can be controlled to be powered off separately, or all power supply units and other devices can be controlled to be powered off in a preset order.

[0076] Optionally, the alarm information may include a channel identifier of the abnormal power supply channel, a target voltage measurement value, and a chip identifier of a corresponding chip to be tested.

[0077] Illustratively, based on the example in step 102, if the target voltage measurement values ​​of the target power channels corresponding to S5, S7 and S8 are measured to belong to the preset voltage value range, and the target voltage measurement value of the target power channel corresponding to S6 does not belong to the preset voltage value range, the power supply unit corresponding to the target power channel is controlled to be powered off.

[0078] Based on the embodiments of the present disclosure, an AND gate alarm circuit is designed. While the analog-to-digital converter polls and collects voltage data, the AND gate alarm circuit monitors the voltage fluctuation of each power supply channel. If the power supply channel generates voltage fluctuation, the AND gate alarm circuit is triggered to output a preset level to the controller, triggering the external interrupt of the controller, and then triggering the controller to control the switching of the multi-way selection switch, so that the analog-to-digital converter measures the voltage value of the target power supply channel connected to the AND gate alarm circuit that outputs the preset level separately, and controls the power supply unit to power off when it is determined that the voltage value is abnormal. There is no need to wait for the analog-to-digital converter to measure the voltage value of the abnormal power supply channel in a preset order before the abnormality can be discovered. The abnormality detection efficiency can be improved, the abnormal power supply channel can be quickly located, and the power supply unit can be controlled to power off, thereby improving the safety of chip testing and avoiding losses caused by untimely power-off.

[0079] In a possible implementation, the chip detection system includes n levels of AND gate alarm circuits, in each level of AND gate alarm circuits, the input end of each AND gate is connected to the output end of the corresponding AND gate in the previous level AND gate alarm circuit, and the output end of each AND gate is connected to the input end of the corresponding AND gate in the next level AND gate alarm circuit, wherein the input end of each AND gate of the first level AND gate alarm circuit is respectively connected to the corresponding power supply channel, and the output end of each AND gate of the nth level AND gate alarm circuit is respectively connected to the corresponding port of the controller, and n is an integer greater than 1.

[0080] The above step 101 may specifically include the following steps:

[0081] In response to receiving the interrupt signal, a target power supply channel is determined based on the connection relationship between each level of the AND gate alarm circuit and the power supply channel.

[0082] Indicative, Figure 4 The schematic diagram of a two-stage AND gate alarm circuit is shown. The left side is the first-stage AND gate alarm circuit, and each input terminal thereof is connected to the corresponding power supply channel. For example, in the first-stage AND gate alarm circuit A, the input terminal 2A is connected to the power supply channel MON_SLAVE_12V, and the input terminal 2B is connected to the power supply channel MON_DVDD_3V3. The figure uses a 4-and-1 AND gate. Among the 4 power supply channels connected to the 4 input terminals, if any one of them has voltage fluctuation, the corresponding output terminal will output a preset level. For example, the input terminals 2A, 2B, 2C and 2D correspond to the output terminal MON_INT2. If any one of the input terminals has voltage fluctuation, the output terminal MON_INT2 outputs a preset level to the second-stage AND gate alarm circuit. The four output terminals MON_INT1, MON_INT2, MON_INT3, and MON_INT4 of the first-stage AND gate alarm circuit are connected to the input terminal 1A of the second-stage AND gate alarm circuit C. Similarly, the input terminal 1B of the second-stage AND gate alarm circuit C is connected to the output terminals of the other four first-stage AND gate alarm circuits. When any of the four input terminals of the second-stage AND gate alarm circuit receives the preset level output by the first-stage AND gate alarm circuit, the corresponding output terminal will output the preset level, thereby triggering the corresponding controller port to generate an interrupt signal. For example, the input terminals 1A, 1B, 1C, and 1D of the second-stage AND gate alarm circuit C correspond to the output terminal 1Y. When any of the MON_INT1, MON_INT2, MON_INT3, and MON_INT4 in the first-stage AND gate alarm circuit outputs the preset level, the output terminal 1Y outputs the preset level, thereby triggering the controller port MON_MCU_INT1 to generate an interrupt signal. In response to receiving the interrupt signal, the controller may determine the target power channel based on a connection relationship between the second-level AND gate alarm circuit and the first-level AND gate alarm circuit, and a connection relationship between the first-level AND gate alarm circuit and the power channel.

[0083] Specifically, Figure 5 As shown, the above step of "determining the target power channel based on the connection relationship between the AND gate alarm circuits and the power channels at each level" may include the following steps:

[0084] Step 501: determine the interrupt port that generates the interrupt signal as the target interrupt port.

[0085] Step 502, determining a target AND gate alarm circuit based on the connection relationship between each level of AND gate alarm circuits.

[0086] The target AND gate alarm circuit is a first-level AND gate alarm circuit connected to the target interrupt port through other-level AND gate alarm circuits.

[0087] In a possible implementation, a plurality of interrupt ports are provided on the controller and connected to the output end of the n-th level AND gate alarm circuit, and one interrupt port corresponds to one n-th level AND gate alarm circuit. When an interrupt signal is received, the interrupt port receiving the interrupt signal is determined as the target interrupt port, thereby determining the n-th level AND gate alarm circuit outputting a preset level, and then forward inquiring based on the connection relationship of each level AND gate alarm circuit to determine the target AND gate alarm circuit.

[0088] For example, for Figure 4 In the two-level AND gate alarm circuit shown, if the interrupt port MON_MCU_INT1 of the controller generates an interrupt signal, the port is determined to be the target interrupt port, and the second-level AND gate alarm circuit corresponding to the port is the upper half of the AND gate chip C. The connected first-level AND gate alarm circuit includes four AND gate alarm circuits with output ends MON_INT1, MON_INT2, MON_INT3, and MON_INT4. These four AND gate alarm circuits are target AND gate alarm circuits.

[0089] Step 503: Based on the connection relationship between the first-level AND gate alarm circuit and the power channel, determine the power channel connected to the target AND gate alarm circuit as the target power channel.

[0090] Optionally, the power channel connected to the target AND gate alarm circuit is directly determined as the target power channel. For example, based on the example of step 502 above, the target power channel can be determined as MON_SLAVE_12V, MON_DVDD_3V3, MON_KU_P3V3, MON_P3V3_CK, MON_P3V3_IO, MON_VCC3V3_SYS, MON_VCC3V3_PMO, MON_VCC_3V3, MON_P5V4, MON_P_6V, MON_P2V3_CK, MON_P9V5_IO.

[0091] Based on the embodiments of the present disclosure, by performing a hierarchical design on the AND gate alarm circuit, when the number of power supply channels is large, the number of AND gate alarm circuits can be reduced, thereby reducing the complexity and manufacturing cost of the chip detection circuit.

[0092] In a possible implementation, after the controller controls the analog-to-digital converter to measure the target voltage of the target power channel, the voltage values ​​of other power channels may be measured in sequence to determine whether there are other abnormal power channels. After the above step 103, the following steps may be included:

[0093] The multi-way selection switch is controlled to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to other power supply channels in turn and measures the voltage value; the voltage measurement value of each other power supply channel is obtained and cached; in response to the existence of a voltage measurement value that does not belong to the preset voltage value interval, at least one power supply unit is controlled to be powered off and an alarm message is generated.

[0094] After determining the target power channel and obtaining the target voltage measurement value, the controller controls the multi-way selection switch to switch according to the preset detection sequence, so that the analog-to-digital converter is connected to other power channels in turn and measures the voltage value. Optionally, the preset detection sequence can be consistent with the measurement sequence of the analog-to-digital converter under normal circumstances, or the power channels adjacent to the target power channel can be measured in the order of giving priority to measuring the power channels. For example, there are 10 power channels in the chip detection circuit, namely 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10. Under normal circumstances, the analog-to-digital converter measures the voltage value in the order from 1 to 10. When the analog-to-digital converter measures the power channel No. 3 in sequence, the controller receives an interrupt signal and determines that the target power channels are 7 and 8. Then the controller controls the multi-way selection switch to switch to power channels 7 and 8 respectively and controls the analog-to-digital converter to measure the target voltage measurement value, and then controls the multi-way selection switch to switch in the order of 6, 9, 1, 2, 3, 4, 5, 10 (or the order of 1, 2, 3, 4, 5, 6, 9, 10) so that the analog-to-digital converter measures the voltage value for other power channels in turn. If there is a voltage measurement value that does not belong to the preset voltage value interval, control at least one power supply unit to power off and generate an alarm message.

[0095] Based on the embodiments of the present disclosure, after obtaining the target voltage measurement value of the target power channel, the voltage values ​​of other power channels are collected in a preset order to check whether there are abnormalities in other power channels. For example, the voltage values ​​of power channels near the target power channel can be measured preferentially, and the possibility that power supply abnormalities may cause voltage abnormalities in multiple adjacent power channels can be taken into consideration, thereby improving the efficiency of abnormality troubleshooting.

[0096] In a possible implementation, before receiving the interrupt signal, the controller is responsible for controlling the analog-to-digital converter to poll and measure the voltage value of each power supply channel according to a preset detection sequence. Before the above step 101, the method provided by the embodiment of the present disclosure may also include the following steps:

[0097] The multi-way selection switch is controlled to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to each power supply channel in turn and measures the voltage value; the voltage measurement value of each power supply channel is obtained and cached; in response to the existence of a voltage measurement value that does not belong to the preset voltage value interval, at least one power supply unit is controlled to be powered off and an alarm message is generated.

[0098] Schematically, there are 10 power supply channels in the chip detection circuit, namely 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10. Under normal circumstances, the analog-to-digital converter polls and measures the voltage value in the order from 1 to 10. The controller is responsible for caching the voltage measurement value of each power supply channel and comparing it with the preset voltage value range. If there is a voltage measurement value that does not belong to the preset voltage value range, even if no interrupt signal is received, at least one power supply unit is controlled to power off and generate an alarm message. Therefore, abnormal detection can be performed simultaneously by software and hardware.

[0099] In a possible implementation, after the above step 104, the method provided by the embodiment of the present disclosure may further include the following steps:

[0100] In response to receiving a voltage detection query instruction sent by a host computer, an alarm message is sent to the host computer through a preset communication protocol.

[0101] Among them, the alarm information includes the chip under test corresponding to the abnormal power channel, the power supply unit corresponding to the abnormal power channel, and the target voltage measurement value corresponding to the abnormal power channel. The abnormal power channel is a target power channel whose target voltage measurement value does not belong to the preset voltage value range.

[0102] Optionally, after the controller generates the alarm information, it waits for the host computer to query. The controller and the host computer can communicate through a preset communication protocol, such as an RS485 communication protocol, in which the host computer is the host and the controller is the slave. The host computer can actively poll various types of information from the controller. When receiving a voltage detection query instruction, the controller sends an alarm message to the host computer.

[0103] Figure 6 The structural block diagram of a chip detection device provided by an exemplary embodiment of the present disclosure is shown. The chip detection device is applied to a controller in a chip detection system, and the chip detection system includes a controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter, wherein the analog-to-digital converter is connected to a power supply channel through a multi-way selection switch, and is used to poll the power supply channel for voltage measurement, the power supply channel is a circuit for connecting the power supply unit and the chip to be tested, and the input end of the AND gate alarm circuit is connected to each power supply channel and the output end is connected to the controller, and is used to trigger the interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps.

[0104] The chip detection device comprises:

[0105] A determination module 601, configured to determine a target power channel based on a connection relationship between an AND gate alarm circuit and a power channel in response to receiving an interrupt signal;

[0106] A first control module 602 is used to control the multi-way selection switch to switch so that the analog-to-digital converter is connected to the target power channel determined by the determination module 601;

[0107] A first acquisition module 603 is used to acquire a target voltage measurement value of a target power supply channel acquired by an analog-to-digital converter;

[0108] The second control module 604 is configured to control at least one power supply unit to power off and generate an alarm message in response to the existence of a target voltage measurement value that does not belong to a preset voltage value interval.

[0109] Optionally, in a possible implementation, the chip detection system includes n-level AND gate alarm circuits, in each level of AND gate alarm circuits, the input end of each AND gate is connected to the output end of the corresponding AND gate in the previous level AND gate alarm circuit, and the output end of each AND gate is connected to the input end of the corresponding AND gate in the next level AND gate alarm circuit, wherein the input end of each AND gate of the first level AND gate alarm circuit is respectively connected to the corresponding power supply channel, and the output end of each AND gate of the nth level AND gate alarm circuit is respectively connected to the corresponding port of the controller, and n is an integer greater than 1;

[0110] The above determination module 601 may also be used for:

[0111] In response to receiving the interrupt signal, a target power supply channel is determined based on the connection relationship between each level of the AND gate alarm circuit and the power supply channel.

[0112] Optionally, in a possible implementation manner, different AND gates in the n-th level AND gate alarm circuit are respectively connected to different interrupt ports in the interrupt system;

[0113] The above determination module 601 may also be used for:

[0114] Determine the interrupt port that generates the interrupt signal as the target interrupt port;

[0115] Based on the connection relationship of the AND gate alarm circuits at various levels, a target AND gate alarm circuit is determined, where the target AND gate alarm circuit is a first-level AND gate alarm circuit connected to the target interrupt port through the AND gate alarm circuits at other levels;

[0116] Based on the connection relationship between the first-level AND gate alarm circuit and the power channel, the power channel connected to the target AND gate alarm circuit is determined as the target power channel.

[0117] Optional, such as Figure 7 As shown, in a possible implementation manner, the chip detection device may further include:

[0118] The first switching module 701 is used to control the multi-way selection switch to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to other power supply channels in sequence and performs voltage value measurement;

[0119] A second acquisition module 702, used to acquire and cache voltage measurement values ​​of other power supply channels;

[0120] The third control module 703 is used to control at least one power supply unit to power off and generate alarm information in response to the existence of a voltage measurement value that does not belong to the preset voltage value interval.

[0121] Optional, such as Figure 8 As shown, in a possible implementation manner, the chip detection device may further include:

[0122] The second switching module 801 is used to control the multi-way selection switch to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to each power supply channel in turn and measures the voltage value;

[0123] A third acquisition module 802 is used to acquire and cache the voltage measurement value of each power supply channel;

[0124] The fourth control module 803 is used to control at least one power supply unit to power off and generate the alarm information in response to the existence of a voltage measurement value that does not belong to the preset voltage value interval.

[0125] Optionally, in a possible implementation manner, the chip detection device may further include:

[0126] A sending module, configured to send an alarm message to the upper computer through a preset communication protocol in response to receiving a voltage detection query instruction sent by the upper computer;

[0127] Among them, the alarm information includes the chip under test corresponding to the abnormal power channel, the power supply unit corresponding to the abnormal power channel, and the target voltage measurement value corresponding to the abnormal power channel. The abnormal power channel is a target power channel whose target voltage measurement value does not belong to the preset voltage value range.

[0128] The present disclosure also provides a chip detection system, which includes a controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter:

[0129] The analog-to-digital converter is connected to the power supply channel through a multi-way selection switch and is used to poll the power supply channel for voltage measurement. The power supply channel is a circuit for connecting a power supply unit and a chip to be tested.

[0130] The input end of the AND gate alarm circuit is connected to each power supply channel and the output end is connected to the controller, and is used to trigger the interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps.

[0131] The controller is used to execute the methods provided by the above-mentioned various method embodiments.

[0132] Optionally, the chip detection system includes n levels of the AND gate alarm circuit, in each level of the AND gate alarm circuit, the input end of each AND gate is connected to the output end of the corresponding AND gate in the previous level AND gate alarm circuit, and the output end of each AND gate is connected to the input end of the corresponding AND gate in the next level AND gate alarm circuit, wherein the input end of each AND gate of the first level AND gate alarm circuit is connected to the corresponding power supply channel, respectively, and the output end of each AND gate of the nth level AND gate alarm circuit is connected to the corresponding port of the controller, respectively, and n is an integer greater than 1.

[0133] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same, similar or corresponding parts between the embodiments can be referred to each other. Since the method, device, and system embodiments are basically corresponding, the relevant parts can be referred to the description of the corresponding parts. The method, device, and system of the embodiments of the present disclosure also correspond to each other in terms of specific implementation methods and beneficial technical effects. The relevant contents can be referred to each other and will not be repeated.

[0134] In addition to the above-mentioned methods and systems, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the image processing method according to various embodiments of the present disclosure described in the above part of this specification.

[0135] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0136] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enable the processor to execute the steps of the image processing method according to various embodiments of the present disclosure described in the above part of this specification.

[0137] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0138] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0139] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0140] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0141] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0142] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0143] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0144] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0145] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip detection method, characterized in that: A controller used in a chip detection system, the chip detection system comprising the controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter, the analog-to-digital converter being connected to a power supply channel via a multi-way selection switch and being used for polling and measuring the voltage of the power supply channel, the power supply channel being a circuit for connecting the power supply unit and a chip to be tested, the input end of the AND gate alarm circuit being connected to each of the power supply channels and the output end being connected to the controller, and being used for triggering an interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps; the method comprising: In response to receiving the interrupt signal, determining a target power channel based on a connection relationship between the AND gate alarm circuit and the power channel; Controlling the multi-way selection switch to switch so that the analog-to-digital converter is connected to the target power supply channel; Acquire a target voltage measurement value of the target power supply channel acquired by the analog-to-digital converter; In response to the existence of a target voltage measurement value that does not belong to a preset voltage value interval, the at least one power supply unit is controlled to be powered off and an alarm message is generated.

2. The method according to claim 1, characterized in that The chip detection system comprises n levels of AND gate alarm circuits, in each level of AND gate alarm circuits, the input end of each AND gate is connected to the output end of the corresponding AND gate in the previous level AND gate alarm circuit, and the output end of each AND gate is connected to the input end of the corresponding AND gate in the next level AND gate alarm circuit, wherein the input end of each AND gate of the first level AND gate alarm circuit is connected to the corresponding power supply channel respectively, and the output end of each AND gate of the nth level AND gate alarm circuit is connected to the corresponding port of the controller respectively, and n is an integer greater than 1; The step of determining the target power channel in response to receiving the interrupt signal based on the connection relationship between the AND gate alarm circuit and the power channel comprises: In response to receiving the interrupt signal, the target power channel is determined based on the connection relationship between each level of the AND gate alarm circuit and the power channel.

3. The method according to claim 2, characterized in that Different AND gates in the n-th level AND gate alarm circuit are respectively connected to different interrupt ports in the interrupt system; The determining the target power channel based on the connection relationship between the AND gate alarm circuits at various levels and the power channel comprises: Determine the interrupt port that generates the interrupt signal as the target interrupt port; Determine a target AND gate alarm circuit based on the connection relationship of the AND gate alarm circuits at each level, wherein the target AND gate alarm circuit is the first level AND gate alarm circuit connected to the target interrupt port through the AND gate alarm circuits at other levels; Based on the connection relationship between the first-level AND gate alarm circuit and the power channel, the power channel connected to the target AND gate alarm circuit is determined as the target power channel.

4. The method according to any one of claims 1 to 3, characterized in that: After acquiring the target voltage measurement value of the target power supply channel acquired by the analog-to-digital converter, the method further includes: Control the multi-way selection switch to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to other power supply channels in sequence and performs voltage value measurement; Acquire and cache the voltage measurement values ​​of each of the other power supply channels; In response to the existence of a voltage measurement value that does not belong to the preset voltage value interval, the at least one power supply unit is controlled to be powered off and the alarm information is generated.

5. The method according to any one of claims 1 to 3, characterized in that: In response to receiving the interrupt signal, before determining a target alarm channel connected to the target AND gate alarm circuit based on a connection relationship between the AND gate alarm circuit and the power supply channel, the method further includes: Control the multi-way selection switch to switch according to a preset detection sequence, so that the analog-to-digital converter is connected to each power supply channel in turn and measures the voltage value; Acquire and cache the voltage measurement value of each power supply channel; In response to the existence of a voltage measurement value that does not belong to the preset voltage value interval, the at least one power supply unit is controlled to be powered off and the alarm information is generated.

6. The method according to any one of claims 1 to 3, characterized in that: After the at least one power supply unit is controlled to be powered off and alarm information is generated in response to the existence of a target voltage measurement value that does not belong to the preset voltage value interval, the method includes: In response to receiving a voltage detection query instruction sent by a host computer, sending the alarm information to the host computer through a preset communication protocol; Among them, the alarm information includes the chip under test corresponding to the abnormal power channel, the power supply unit corresponding to the abnormal power channel and the target voltage measurement value corresponding to the abnormal power channel. The abnormal power channel is a target power channel whose target voltage measurement value does not belong to the preset voltage value range.

7. A chip detection device, characterized in that: A controller used in a chip detection system, the chip detection system comprising the controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter, the analog-to-digital converter being connected to a power supply channel via a multi-way selection switch and being used for polling and measuring the voltage of the power supply channel, the power supply channel being a circuit for connecting the power supply unit and a chip to be tested, the input end of the AND gate alarm circuit being connected to each of the power supply channels and the output end being connected to the controller, and being used for triggering an interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps; the device comprising: a determination module, configured to determine a target power channel in response to receiving the interrupt signal and based on a connection relationship between the AND gate alarm circuit and the power channel; A first control module, used for controlling the multi-way selection switch to switch so that the analog-to-digital converter is connected to the target power supply channel; A first acquisition module, used for acquiring a target voltage measurement value of the target power supply channel acquired by the analog-to-digital converter; The second control module is used to control the at least one power supply unit to power off and generate alarm information in response to the existence of a target voltage measurement value that does not belong to a preset voltage value interval.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method described in any one of claims 1 to 6 is implemented.

9. A chip detection system, characterized in that: It includes a controller, at least one power supply unit, at least one AND gate alarm circuit and an analog-to-digital converter; The analog-to-digital converter is connected to the power supply channel through a multi-way selection switch, and is used for polling and measuring the voltage of the power supply channel, wherein the power supply channel is a circuit for connecting the power supply unit and the chip to be tested; The input end of the AND gate alarm circuit is connected to each of the power supply channels and the output end is connected to the controller, and is used to trigger the interrupt system of the controller to generate an interrupt signal by outputting a preset level when the voltage of the power supply channel jumps; The controller is used to execute the method described in any one of claims 1 to 6.

10. The system according to claim 9, characterized in that The system includes n levels of AND gate alarm circuits. In each level of AND gate alarm circuits, the input end of each AND gate is connected to the output end of the corresponding AND gate in the previous level AND gate alarm circuit, and the output end of each AND gate is connected to the input end of the corresponding AND gate in the next level AND gate alarm circuit, wherein the input end of each AND gate of the first level AND gate alarm circuit is connected to the corresponding power supply channel respectively, and the output end of each AND gate of the nth level AND gate alarm circuit is connected to the corresponding port of the controller respectively, and n is an integer greater than 1.

Images