An adaptive gain control device and implementation method for a coherent processing branch

Abstract

The present invention relates to the field of coherent signal processing, and in particular to an adaptive gain control device and implementation method of a coherent processing branch. The present invention utilizes the characteristics of the floating point data format in FPGA, combines the coherently processed signal with a simple signal processing structure and a small-scale lookup table, performs logarithmic compression of a large dynamic signal, thereby obtaining a stable gain control signal, and inputs it into the controlled intermediate frequency amplifier, thereby realizing the automatic control function of the digital receiver gain. The present invention has the characteristics of low resource consumption, high time efficiency, and flexible configuration parameters.

Description

Technical Field

[0001] The invention relates to the field of coherent signal processing, and in particular to an adaptive gain control device of a coherent processing branch and an implementation method thereof. Background Art

[0002] In target indication radar, in order to ensure the linear processing dynamic range of the coherent processing branch of the digital receiving system, the amplification gain of the digital receiving system must be adjusted quickly and automatically. Usually, the large dynamic linear signal after coherent processing is logarithmically compressed, and then the amplification gain of the receiving device is adaptively controlled according to the size of the compressed signal, so as to maintain an appropriate gain range in the radar digital receiving system.

[0003] In order to solve the problem of large dynamic range of coherent branch signals, there are two commonly used logarithmic compression methods: one is based on table lookup, which has simple hardware logic and high time efficiency, but is limited by hardware storage resources. Especially in modern radar signal processing systems, signal sampling accuracy is getting higher and higher, and the dynamic range is getting larger and larger. Even if the data segmentation mapping table lookup method is used to compress the table lookup data, this method will still be abandoned due to excessive consumption of hardware ROM resources. The other is a real-time processing device based on a certain iterative algorithm. Through technological development, although the existing device uses a simplified CORDIC algorithm or other shift accumulators to implement numerical recursion to reduce the number of operation iterations, in order to ensure the accuracy of logarithmic calculation, the iteration level still needs at least 4 levels. Each iteration requires calculation of multiple clock cycles, and the relatively large amount of calculation and high complexity. For high-speed signal processing systems based on FPGA, this type of operation implementation method has a lot of delay, and if it is to be stably implemented in a high-speed application environment, it must sacrifice the timing beat, which reduces the time efficiency of the device. At the same time, the method is not flexible enough, and it is not possible to achieve logarithmic processing of different bases and different precisions through simple changes.

[0004] Therefore, there is a need for an adaptive gain control device and method that has a simple structure, consumes less resources, has high time efficiency, has flexible configuration parameters, and can meet the requirements of large dynamic coherent branch signals. Summary of the invention

[0005] In view of the deficiencies of the prior art, the present invention provides an adaptive gain control device and implementation method for a coherent processing branch. This method addresses the problem of large dynamic range of the coherent processing branch signal, utilizes the characteristics of the floating point data format in the FPGA, combines the coherently processed signal with a simple signal processing structure and a small-scale lookup table, performs logarithmic compression of the large dynamic signal, thereby obtaining a stable gain control signal, and inputs it into the controlled intermediate frequency amplifier, thereby realizing the automatic control function of the digital receiver gain. The present invention has the characteristics of low resource consumption, high timeliness, and flexible configuration parameters.

[0006] The technical solution of the present invention is: a method for realizing adaptive gain of a coherent processing branch, characterized in that:

[0007] Step 1: Convert the data format of the coherent branch signal power data to convert the signed 18-bit fixed-point number representing the signal power after coherent processing into a 32-bit floating-point number;

[0008] Step 2: Get the floating point exponent, decode the 32-bit floating point number obtained in step 1, and obtain the 8-bit exponent e by shifting and rounding;

[0009] Step 3: Get the mantissa of the floating point number, decode the 32-bit floating point number obtained in step 1, obtain the 23-bit mantissa m by shifting and rounding, and intercept the high N bits as the effective table lookup address MAddr[N-1..0];

[0010] Step 4: Exponential operation. Subtract the exponent offset from the exponent e obtained in step 2 to get ex. The exponent offset of a 32-bit floating point number is 127.

[0011] Step 5: Data scaling adjustment: the exponent ex obtained in step 4 is adjusted by a scaling factor of K times.

[0012] The scaling factor k involved in step 5 is determined by three factors: the base n of the logarithm to be taken, the logarithmic table data accuracy TDM, and the input signal logarithmic dynamic range LDM, that is, k = log n 2×TDM / LDM;

[0013] Step 6: Look up the mantissa in the table. Use the mantissa obtained in step 3 as the logarithmic lookup table address MAddr[N-1..0] to perform a logarithmic table lookup operation to obtain the mantissa logarithm mk.

[0014] Step 7: Data synthesis: add the exponential logarithm ek obtained in step 5 and the mantissa logarithm mk obtained in step 6 to obtain the desired logarithmic signal log n x, x represents the value of the coherent signal input by the receiver;

[0015] Step 8: Gain control signal encoding, the logarithmic signal obtained in step 7 log n x is smoothed and segment-coded to generate a gain control signal relevant to a digital receiver.

[0016] The device and method of the present invention have the following beneficial effects: In the adaptive gain control device of the coherent processing branch, the traditional method of realizing large dynamic signal logarithmic compression based on FPGA is mostly realized by segmented lookup table, which consumes more FPGA storage resources. The simplified iterative algorithm using approximate series expansion is mostly used in computer or DSP system, and its calculation structure is complex and difficult to realize in FPGA and inefficient. The present invention converts the signal into a floating point number for logarithmic calculation, wherein the realization difficulty is to take the logarithm of the mantissa, and adopts the combination of approximate calculation and lookup table to realize, and converts the complex real-time operation into offline fixed parameter calculation. At the beginning of the design, the parameter calculation can be completed by matlab and stored in a lookup table with a smaller capacity, so that the device can ensure the calculation accuracy while the hardware implementation structure is simple, the resource consumption is small, and the execution timeliness is high, and only 5 clock beats are needed to complete the signal logarithmic processing. At the same time, the parameter configuration modification is more flexible, and the logarithmic processing of floating point signals with any base, any single, double or quadruple precision can be realized, which meets the demand for large dynamic signal logarithmic compression in the coherent processing branch in the FPGA hardware platform, thereby realizing a stable and continuous automatic gain control function. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The device block diagram is shown in FIG.

[0018] Figure 2 This is the block diagram of the logarithmic compression principle.

[0019] Figure 3 Generate a block diagram for the logarithmic table.

[0020] Figure 4 Schematic diagram for smoothing. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0022] like Figures 1 to 4As shown, the radar receiving signal of the present invention is converted into a digital signal through high-speed AD sampling, and the signal bit width is usually 14 bits (even if the existing highest precision AD sampling is used, the signal bit width will not exceed 16 bits). However, after the coherent accumulation processing, the signal dynamic range will be greatly expanded, that is, the digital signal bit width will usually be expanded to 18 bits or higher with multi-order coherent accumulation. However, the power amplifier control signal bit width that realizes the gain adjustment function in the receiving system only supports 16 bits. At the same time, in order to retain the sensitivity of small signal changes, the signal cannot be simply compressed linearly. Instead, the 18-bit signal after coherent processing needs to be logarithmically compressed and converted into a 16-bit signal to control the receiver gain, so as to ensure that the large signal of the receiver is not saturated and the small signal is continuously and stably output. An adaptive gain control device of a coherent processing branch of the present invention realizes the compression and optimization processing of the 18-bit bit width large dynamic signal after coherent processing, and adjusts it to a 16-bit adaptive control signal to control the gain of the receiving system. The traditional 18-bit address width lookup table between values ​​0 and 262143 is converted into a 10-bit address width lookup table between values ​​1 and 2, which improves the accuracy of logarithmic value acquisition and reduces the hardware logic space occupied by the lookup table. In addition, the hardware implementation structure is simple and time-efficient, and only 5 clock beats are required to complete the function. Figure 1 As shown, an adaptive gain control device of a coherent processing branch of the present invention includes a fixed-point to floating-point module, a shift register, a subtractor, a multiplier, a logarithmic lookup table, and a gain control signal encoding in an FPGA chip.

[0023] The fixed-point to floating-point module converts the signed 18-bit fixed-point number representing the coherent branch signal power into a 32-bit floating-point number.

[0024] The 32-bit floating point number is output to the shift register, which decodes the 32-bit floating point number, shifts and intercepts bits 30 to 23 to obtain an 8-bit exponent e[7..0], and intercepts bits 22 to 13 to obtain a 10-bit mantissa m[9..0]. The shift register outputs the 8-bit exponent e[7..0] to the subtractor.

[0025] The subtractor subtracts the offset 127 from the exponent e[7..0] output by the shift register to obtain ex[7..0]. The subtractor outputs the result ex[7..0] to the multiplier. The multiplier multiplies the output ex[7..0] of the subtractor by the scaling factor k to obtain the exponential logarithm ek[15..0]. The multiplier outputs the logarithm ek[15..0] to the adder.

[0026] On the other hand, the shift register outputs the 10-bit mantissa m[9..0] to the logarithmic lookup table. The logarithmic lookup table uses the mantissa m[9..0] output by the shift register as the address to look up the mantissa logarithm mk[15..0]. The logarithmic lookup table outputs the mantissa logarithm mk[15..0] to the adder. The adder sums the exponential logarithm ek[15..0] and the mantissa logarithm mk[15..0] to obtain the desired logarithmic signal log n x. The adder converts the logarithmic signal log n x is output to the gain control signal encoding. The gain control signal encoding smoothes the logarithmic signal output by the adder and generates a gain control signal related to the receiver by segment encoding. The smoothing process uses Dn = 1 / 8*log n x+7 / 8D(n-1) is used to implement the principle. Figure 4 .

[0027] The data format characteristics of floating-point numbers in the FPGA chip of the present invention are used as the basis for realizing signal logarithmic compression processing. The data format of the double-precision 32-bit floating-point number x[31..0] in the FPGA is as follows: x

[31] is the sign bit, represented by s; x[30..23] is the exponent bit, represented by e; x[22..0] is the mantissa bit, represented by m; then, the actual value corresponding to x is x=(-1) s ×2 (e-127) ×(1+m).

[0028] Since the power data processed in the signal processing system are modulo, they are all positive integers, so the logarithm value of x with base 2 is log2x=(e-127)+log2(1+m), and the corresponding logarithm value of x with base n is log n x=log n 2×log2x.

[0029] The principle block diagram of the method adopted by the present invention is shown in the attached Figure 2 , a method for realizing adaptive gain of a coherent processing branch, the specific implementation steps are as follows:

[0030] Step 1: Convert the data format of the coherent branch signal power data. Convert the signed 18-bit fixed-point number representing the signal power after coherent processing into a 32-bit floating-point number. The coherent signal value output by the receiver to the FPGA chip is represented by x.

[0031] Step 2: Get the floating point exponent, decode the 32-bit floating point number obtained in step 1, and obtain the 8-bit exponent e by shifting and rounding.

[0032] Step 3: Get the mantissa of the floating point number, decode the 32-bit floating point number obtained in step 1, obtain the 23-bit mantissa m by shifting and rounding, and intercept the high N bits as the effective table lookup address MAddr[N-1..0].

[0033] Step 4: Exponential operation. Subtract the exponent offset from the exponent e obtained in step 2 to obtain ex. The exponent offset of a 32-bit floating point number is 127, that is, ex=e-127.

[0034] Step 5: Data scaling adjustment. In order to obtain the logarithm with base n, the exponent ex obtained in step 4 must be scaled by K times. At the same time, considering the FPGA design accuracy and the dynamic range of the input signal, in practical applications, it is necessary to properly optimize the scaling factor K to obtain the exponential logarithm ek.

[0035] The scaling factor k involved in step 5 is determined by three factors: the base n of the logarithm to be taken, the logarithmic table data accuracy TDM, and the input signal logarithmic dynamic range LDM, that is, k = log n 2×TDM / LDM. Once the system design requirements are determined, the scaling factor becomes a fixed parameter and can be obtained by offline calculation and optimization using MATLAB during system design to ensure parameter accuracy.

[0036] Step 6: Look up the mantissa in the table. Use the mantissa obtained in step 3 as the logarithmic lookup table address MAddr[N-1..0] to perform a logarithmic table lookup operation, thereby realizing the function of taking the logarithm of the mantissa and scaling the mantissa in one step to obtain the mantissa logarithm mk.

[0037] The logarithmic table involved in step 6 is obtained by generating a logarithmic table with a base of 2 and an address width of N bits with values ​​between 1 and 2, scaling it by K times the coefficient obtained in step 8, and finally rounding it off. See the attached schematic diagram Figure 3 The logarithmic table is obtained by offline calculation optimization using MATLAB during system design, which can ensure the accuracy of the logarithmic table. The scaling factor k is determined by three factors: the base n of the logarithm required, the data accuracy TDM of the logarithmic table, and the logarithmic dynamic range LDM of the input signal, that is, the scaling factor k = log n 2×TDM / LDM.

[0038] Step 7: Data synthesis: add the exponential logarithm ek obtained in step 5 and the mantissa logarithm mk obtained in step 6 to obtain the desired logarithmic signal log n x, x represents the coherent signal value input by the receiver.

[0039] Step 8: Gain control signal encoding, the logarithmic signal obtained in step 7 log nx is smoothed and segmented to generate a gain control signal related to the digital receiver. The smoothing process uses Dn = 1 / 8*log n x+7 / 8D(n-1) is implemented, the gain control signal Dn is output, D(n-1) represents the output of the gain control signal of the previous cycle, the principle is shown in the attached Figure 4 , during the initial calculation, D(n-1) is zero.

[0040] This implementation example utilizes the characteristics of the floating-point data format in FPGA, combines the coherently processed signal with a simple signal processing structure and a small-scale lookup table, and performs logarithmic compression of the large dynamic signal, thereby obtaining a stable gain control signal, which is input into the intermediate frequency amplifier to control the gain of the digital receiver. The example implements logarithmic compression processing with a base of 10 based on the double-precision 32-bit floating-point number x[31..0] feature in FPGA, that is, generating a log for the sampled signal X. 10 x. The capacity of the logarithmic table is 10*16 bits, and the data accuracy of the logarithmic table is 16 bits, that is, TDM=2 16 The dynamic range of the input signal is 17 bits, that is, LDM = log 10 (2 17 ). The specific implementation process is as follows:

[0041] Convert the signed 18-bit fixed-point number mod[17..0] representing the signal power to a 32-bit floating-point number d[31..0]. This is done directly using the floating-point conversion module in the FPGA.

[0042] Decode the 32-bit floating point number, and use the shift register to get d[30..23] to get the 8-bit exponent e[7..0]. By shifting and rounding, take d[22..0] to get the 23-bit mantissa m[22..0], and intercept the upper 10 bits as the effective table lookup address MAddr[9..0].

[0043] The exponent e[7..0] is subtracted from the exponent offset by a subtractor to obtain ex[7..0]. The exponent offset of a 32-bit floating point number is 127, that is, ex[7..0]=e[7..0]-127.

[0044] In order to obtain the logarithm with base 10, the exponent ex[7..0] must be adjusted by a fixed multiple K. At the same time, considering the FPGA design accuracy and the dynamic range of the input signal, in practical applications, it is necessary to properly optimize the scaling factor K to obtain the exponential logarithm ek[15..0], that is, ek[15..0] = k*ex[7..0]. Among them, the scaling factor k is determined by three factors, namely, the base of the logarithm required n = 10, the logarithm table data accuracy TDM = 2 16、Logarithmic dynamic range of input signal LDM=log 10 (2 17 ), that is, k = log n 2×TDM / LDM. Once the system design requirements are determined, the scaling factor becomes a fixed parameter and can be obtained by offline calculation and optimization using MATLAB during system design, which can ensure parameter accuracy and precision and simplify the hardware structure.

[0045] At the same time, it is also necessary to look up the logarithm of the mantissa. Use the mantissa address MAddr[9..0] to look up the logarithm table, and implement the function of taking the logarithm of the mantissa and scaling it in one step to obtain the mantissa logarithm mk[15..0]. The logarithm table is generated by an offline MATLAB program and solidified in the hardware device after design. Generate a logarithm table with a very small capacity between 1 and 2 in MATLAB, and then multiply it by the same multiple as the exponent, that is, k=log n 2×TDM / LDM times scaling, but the K times scaling function is obtained by using MATLAB offline calculation optimization when establishing the logarithmic table, without the need for hardware real-time calculation. During the calculation process, the data always takes 16 bits of precision, but the system requires that the final logarithmic value only takes 10 bits of precision to meet the system dynamic range requirements. Therefore, the data after k times scaling can be obtained by adding an offset of 2 6 Implement rounding calculation after truncation. This operation is the same as the logarithmic value and k-fold scaling functions mentioned above, and is completed when MATLAB builds the logarithmic table. In this way, the complex calculation process is converted to offline calculation, which not only ensures the accuracy of the logarithmic data, but also simplifies the hardware implementation structure and improves the timeliness of the hardware operation processing. The specific MATLAB program for generating the logarithmic table is as follows:

[0046]

[0047] Finally, the exponential logarithm ek[16..0] and the mantissa logarithm mk[16..0] are added by the adder to obtain the logarithmic signal log required in the example. 10 x. Smooth the logarithmic signal by 1 / 8, that is, Dn = 1 / 8*log nx+7 / 8D(n-1), the gain control signal Dn is output, D(n-1) represents the output of the gain control signal of the previous cycle, and the gain control signal related to the receiver is generated by segment coding, and output to the intermediate frequency amplification control end of the receiver, that is, the automatic gain control function is realized. An adaptive gain control device of a coherent processing branch of the present invention realizes the compression optimization processing of the 18-bit wide dynamic signal of the receiving system after coherent processing, and adjusts it to a 16-bit adaptive control signal to control the gain of the receiving system. Among them, the traditional lookup table with an address width of 18 bits between values ​​0 and 262143 is converted into a lookup table with an address width of 10 bits between values ​​1 and 2, which improves the accuracy of logarithmic value taking and reduces the hardware logic space occupied by the lookup table. In addition, the hardware implementation structure is simple and time-efficient, and only 5 clock beats are required to complete the function.

Claims

1. A method for realizing adaptive gain of a coherent processing branch, characterized in that: Step 1: Convert the data format of the coherent branch signal power data to convert the signed 18-bit fixed-point number representing the signal power after coherent processing into a 32-bit floating-point number; Step 2: Get the floating point exponent, decode the 32-bit floating point number obtained in step 1, and obtain the 8-bit exponent e by shifting and rounding; Step 3: Get the mantissa of the floating point number, decode the 32-bit floating point number obtained in step 1, obtain the 23-bit mantissa m by shifting and rounding, and intercept the high N bits as the effective table lookup address MAddr[N-1..0]; Step 4: Exponential operation. Subtract the exponent offset from the exponent e obtained in step 2 to get ex. The exponent offset of a 32-bit floating point number is 127. Step 5: Data scaling adjustment: the exponent ex obtained in step 4 is adjusted by a scaling factor of K times. The scaling factor k involved in step 5 is determined by three factors: the base n of the logarithm to be taken, the logarithmic table data accuracy TDM, and the input signal logarithmic dynamic range LDM, that is, k = log n 2×TDM / LDM; Step 6: Look up the mantissa in the table. Use the mantissa obtained in step 3 as the logarithmic lookup table address MAddr[N-1..0] to perform a logarithmic table lookup operation to obtain the mantissa logarithm mk. Step 7: Data synthesis: add the exponential logarithm ek obtained in step 5 and the mantissa logarithm mk obtained in step 6 to obtain the desired logarithmic signal log n x, x represents the value of the coherent signal input by the receiver; Step 8: Gain control signal encoding, the logarithmic signal obtained in step 7 log n x is smoothed and segment-coded to generate a gain control signal relevant to a digital receiver.

2. The method for realizing adaptive gain of a coherent processing branch according to claim 1, characterized in that: The smoothing process in step 8 uses Dn=1 / 8*log n The gain control signal Dn is outputted in the form of x+7 / 8D(n-1), D(n-1) represents the output of the gain control signal in the previous cycle, and x represents the coherent signal value inputted by the receiver.

3. An adaptive gain control device for a coherent processing branch, wherein the FPGA chip includes a fixed-point to floating-point module, a shift register, a subtractor, a multiplier, an adder, a logarithmic lookup table, and a gain control signal encoding, characterized in that: The fixed-point to floating-point module converts the signed 18-bit fixed-point number representing the power of the coherent branch signal into a 32-bit floating-point number; the 32-bit floating-point number is output to the shift register, the shift register decodes the 32-bit floating-point number, shifts and intercepts 30 to 23 bits to obtain an 8-bit exponent e[7..0], intercepts 22 to 13 bits to obtain a 10-bit mantissa m[9..0], and the shift register outputs the 8-bit exponent e[7..0] to the subtractor; the subtractor subtracts the offset 127 from the exponent e[7..0] output by the shift register to obtain ex[7..0]; the subtractor outputs the result of ex[7..0] to the multiplier; the multiplier The output of the subtractor ex[7..0] is multiplied by the scaling factor k to obtain the exponential logarithm ek[15..0]; the multiplier outputs the logarithm ek[15..0] to the adder; the shift register outputs the 10-bit mantissa m[9..0] to the logarithmic lookup table; the logarithmic lookup table uses the mantissa m[9..0] output by the shift register as the address to look up the mantissa logarithm mk[15..0]; the logarithmic lookup table outputs the mantissa logarithmk[15..0] to the adder; the adder sums the exponential logarithm ek[15..0] and the mantissa logarithm mk[15..0] to obtain the desired logarithmic signal log n x; the adder converts the logarithmic signal log n x is output to the gain control signal encoding; the gain control signal encoding smoothes the logarithmic signal output by the adder and generates a gain control signal related to the receiver by segment encoding, and x represents the coherent signal value input by the receiver.

4. The adaptive gain control device of a coherent processing branch according to claim 1, characterized in that: The smoothing process in the gain control signal encoding adopts Dn=1 / 8*log n The gain control signal Dn is outputted in the manner of x+7 / 8D(n-1), and D(n-1) represents the output of the gain control signal in the previous cycle.

5. The adaptive gain control device of a coherent processing branch according to claim 1, characterized in that: Scaling factor k = log n 2×TDM / LDM; n is the base of the logarithm; TMD is the logarithmic table data accuracy, and LDM is the logarithmic dynamic range of the input signal.

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