FPGA-based radar pulse signal sampling and storing method and device

Abstract

The invention discloses a radar pulse signal sampling and storing method and device based on an FPGA in the technical field of signal processing. The method comprises the steps that S1, radar pulse signals are acquired and sampled, and radar pulse data to be stored are acquired after processing; s2, a half-power point is obtained from the radar pulse data, data storage is started when the signal amplitude is larger than or equal to the half-power point for the first time, and the half-power point is obtained by subtracting a set value from the amplitude of a pulse signal corresponding to a first standard maximum value point of the rising edge of the radar pulse data. Compared with a conventional method, the sampling storage method can effectively avoid the influence of the pulse signal amplitude on the position of the rising edge of the detection signal, so that the initial position of data storage is relatively stable, the position of an interference target which is delayed and forwarded later is also relatively stable, and a relatively good interference effect is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a radar pulse signal sampling and storage method and device based on FPGA. Background Art

[0002] When using FPGA to sample, store and delay interference of radar pulse signals, FPGA needs to store the sampled data of radar pulse signals first, and generate interference signals at a certain distance by delaying forwarding. If the radar pulse width is large, the signal needs to be extracted before storage. If the extraction multiple is high, the data sampling rate will be low, and the different storage starting positions will affect the position of the interference signal, because the radar determines the target distance by the arrival time of the rising edge of the echo pulse. When to start storing data becomes a key point affecting the interference effect.

[0003] Normally, the sampled data is FFTed in FPGA to determine whether the FFT peak value exceeds the threshold. If the FFT peak value is higher than the threshold, it indicates that a pulse signal has arrived. At this time, the detection signal is set to 1. If it is lower than the threshold, the detection signal is set to 0. When the detection signal is 1, the sampled pulse data is stored. However, the above method is only applicable to the case where the sampling rate of the data to be stored is high. For data with a low sampling rate, it is not appropriate to determine whether the signal needs to be stored by whether the FFT peak value exceeds the detection threshold. Because the FFT IP core in FPGA performs sliding window FFT, the number of data in its sliding window is the same as its FFT point number, that is, the data that has participated in this FFT will not participate in the next FFT operation. Since the arrival of the pulse signal is random, the number of pulse data participating in the FFT each time is also random, which makes the time when the FFT peak is generated and the amplitude of the peak very random, and then makes the starting position of the data storage random. Of course, multiple FFT IP cores can also be used to reduce the number of sliding window data, but the use of multiple FFT IP cores will also increase the code complexity and resource usage.

[0004] In view of the above situation, for data with a low sampling rate, the conventional approach is to directly determine whether the signal amplitude exceeds the detection threshold. The detection threshold is set manually and is usually a value higher than the noise floor amplitude. This approach makes the starting position of data storage affected by the amplitude of the pulse signal. When the pulse signal amplitude is low, the starting position of data storage is closer to the trailing edge of the pulse signal; when the pulse signal amplitude is high, the starting position of data storage is closer to the leading edge of the pulse signal. Summary of the invention

[0005] The present application provides a radar pulse signal sampling and storage method based on FPGA, which solves the problem of inaccurate storage starting position of pulse data with a low sampling rate in the prior art, and achieves a relatively stable starting position of data storage, thereby making the position of the interference target that is delayed and forwarded later also relatively stable, thereby improving the interference effect.

[0006] The embodiment of the present application provides a radar pulse signal sampling and storage method based on FPGA, comprising the following steps: S1: Acquire radar pulse signals and perform sampling, and obtain radar pulse data with a low sampling rate to be stored after processing; S2: Obtain a half-power point from the radar pulse data, and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data.

[0007] The beneficial effect of the above embodiment is that compared with conventional practices, this sampling and storage method can effectively avoid the influence of the pulse signal amplitude on the position of the rising edge of the detection signal, which makes the starting position of the data storage more stable, and thus makes the position of the interference target that is delayed and forwarded later also more stable, and has a better interference effect.

[0008] Based on the above embodiments, the present application can be further improved as follows: In one embodiment of the present application, the step S1 is specifically as follows: S1.1: Acquire the radar pulse signal and perform sampling to obtain a sampling signal; S1.2: performing orthogonal down-conversion and first-level filtering on the sampled signal; S1.3: performing secondary down-conversion processing on the sampled signal after the primary filtering; S1.4: The sampling signal after the secondary down-conversion process is subjected to multiple decimation and secondary filtering to obtain the radar pulse data with a low sampling rate to be stored, thereby reducing the amount of data required to be stored while lowering the sampling rate.

[0009] In one embodiment of the present application, in step S1.3, the secondary down-conversion processing method is as follows: The sampled signal after primary filtering is copied into two copies, one of which is temporarily stored in RAM, and the other is processed by FFT, and the FFT peak is compared with the set threshold, and the frequency of the sampled signal is calculated according to the position of the peak that exceeds the threshold, and the frequency is used as the local oscillator to perform secondary down-conversion on the cached sampled signal, thereby moving the sampled radar pulse signal to the vicinity of zero frequency.

[0010] In one of the embodiments of the present application, in the step S2, data storage is stopped when the signal amplitude is less than the half power point for the first time.

[0011] In one of the embodiments of the present application, in step S2, the stored data is triggered by a detection signal. When the signal amplitude in the radar pulse data is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and data storage begins when the detection signal is first 1. When the signal amplitude in the radar pulse data is less than the amplitude of the half-power point, the detection signal is set to 0, and data storage stops when the detection signal is first 0.

[0012] In one embodiment of the present application, in step S2, the first standard maximum point is obtained as follows: Obtain the maximum point in the rising edge stage of the radar pulse data, and obtain the amplitude average of multiple data points following the maximum point, and compare the amplitude average with the amplitude corresponding to the maximum point; if the difference is less than the set value, the maximum point is used as the first standard maximum point, otherwise the next maximum point after the maximum point is obtained and verified again until the first standard maximum point is obtained. Process the burrs that may exist in the rising edge stage of the pulse signal to ensure that the detection threshold generated by the pulse signal amplitude is correct.

[0013] In one of the embodiments of the present application, in the step S2, a noise floor threshold is further set, and the maximum point is greater than the noise floor threshold.

[0014] In one of the embodiments of the present application, in the step S2, the set value is set to 6db.

[0015] The embodiment of the present application also provides a radar pulse signal sampling and storage device based on FPGA, comprising: A processing module is used to acquire radar pulse signals and perform sampling, and obtain radar pulse data to be stored after processing; A storage module is used to obtain a half-power point from the radar pulse data, and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point of the rising edge of the radar pulse data.

[0016] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: 1. This sampling storage method changes the conventional manually set detection threshold into a detection threshold automatically generated according to the signal amplitude, thereby preventing the starting position of data storage from being affected by changes in the signal amplitude.

[0017] 2. This sampling and storage method provides a further improvement plan for the glitches that may exist in the rising edge stage of the pulse signal, using a more accurate method to determine the amplitude of the radar pulse signal to ensure that the detection threshold generated by the pulse signal amplitude is correct.

[0018] 3. This sampling and storage method processes the acquired radar pulse signal in multiple steps, which reduces the sampling rate and the amount of data required to be stored, making it easier to store subsequent data. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0020] Figure 1 This is a flowchart of a radar pulse signal sampling and storage method based on FPGA in an embodiment of the present application; Figure 2 A flowchart of the steps of obtaining radar pulse data to be stored in an embodiment of the present application; Figure 3 The signal diagram of radar pulse data in the embodiment of the present application is shown in FIG. Figure 1 ; Figure 4 The signal diagram of radar pulse data in the embodiment of the present application is shown in FIG. Figure 2 ; Figure 5 A structural block diagram of a radar pulse signal sampling and storage device based on FPGA provided in an embodiment of the present invention; Figure 6 The present invention is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention is further explained below in conjunction with specific implementation methods. It should be understood that these implementation methods are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0022] In the description of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in the present invention and the features of different embodiments or examples without contradiction.

[0023] Example: like Figure 1 As shown, a radar pulse signal sampling and storage method based on FPGA includes the following steps: S1: Acquire radar pulse signals and perform sampling, and obtain radar pulse data with a low sampling rate to be stored after processing; specifically: S1.1: Acquire a radar pulse signal and perform sampling to obtain a sampled radar pulse signal; S1.2: Perform orthogonal down-conversion and first-level filtering on the sampled radar pulse signal; S1.3: Perform secondary down-conversion processing on the radar pulse signal after the primary filtering, and adjust the radar pulse signal to a frequency close to zero; Among them, the secondary down-conversion processing method is as follows: The radar pulse signal after the first-stage filtering is copied into two copies, one of which is temporarily stored in RAM, and the other is processed by FFT. The FFT peak is compared with the threshold, and the frequency of the radar pulse signal is calculated according to the position of the peak that exceeds the threshold. This frequency is used as the local oscillator to perform secondary down-conversion on the cached radar pulse signal, thereby moving the radar pulse signal to near zero frequency. S1.4: Perform multiple decimation and secondary filtering on the radar pulse signal close to zero frequency to obtain radar pulse data with a low sampling rate to be stored.

[0024] S2: Get the half-power point from the radar pulse data. Start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, and stop storing data when the signal amplitude is less than the half-power point. The half-power point is obtained by subtracting the set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data.

[0025] Usually, the setting value is set to 6db. That is, the amplitude of the pulse signal corresponding to the first standard maximum value point is subtracted by 6db to obtain the half power point. In practice, the half power point can also be obtained by subtracting 3db from the power of the pulse signal corresponding to the first standard maximum value point.

[0026] Among them, the stored data is triggered by the detection signal. When the signal amplitude in the radar pulse data is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and the pulse data is stored from the time the detection signal is 1. When the signal amplitude is less than the amplitude of the half-power point, the detection signal is set to 0, and the pulse data storage is stopped from the time the detection signal is 0.

[0027] Among them, the first standard maximum point is obtained as follows: Get the maximum point in the rising edge stage of the radar pulse data, and get the amplitude average of multiple data points following the maximum point, compare the amplitude average with the amplitude corresponding to the maximum point, if the difference is less than the set value, take the maximum point as the first standard maximum point, otherwise get the next maximum point after the maximum point and verify again until the first standard maximum point is obtained.

[0028] In the actual application of FPGA, a noise floor threshold must be set. The maximum point is greater than the noise floor threshold. When the amplitude of the signal data is greater than the threshold, it means that a radar pulse signal has arrived, triggering and looking for the first standard maximum value greater than the noise floor threshold.

[0029] The following is a specific example of a radar pulse signal sampling and storage method based on FPGA.

[0030] like Figure 2 As shown, step S1 is exemplified as follows: S1.1: Assume that the microwave module converts the radar pulse signal to an intermediate frequency of 2MHz to 30MHz, and the FPGA samples the intermediate frequency radar pulse signal at a sampling rate of 2.4G to obtain 16 channels of AD sampling data with a sampling rate of 150M. However, since the radar pulse signal width is relatively large and the sampling rate is relatively high, in order to store the radar pulse signal data, it is necessary to extract these 16 channels of AD sampling data, thereby reducing the sampling rate and the amount of data required to be stored.

[0031] S1.2: The 16 channels of data are extracted and filtered to obtain single-channel AD data with a sampling rate of 75M. The single-channel AD data with a sampling rate of 75M is first orthogonally down-converted to a bandwidth range of -14M to 14M, and then the obtained complex signal is doubled to obtain a single-channel AD data with a sampling rate of 37.5M, and then a first-level filtering process is performed on it.

[0032] S1.3: Then, the first-stage filtered data is copied into two copies, one is temporarily stored in RAM, and the other is subjected to 2048-point FFT, and it is determined whether the FFT peak exceeds the threshold, and the frequency of the radar pulse signal is calculated according to the position of the peak that exceeds the threshold. After that, the measured frequency of the radar pulse signal is used as the local oscillator to perform a second down-conversion on the cached data, and the radar pulse signal is moved to the vicinity of zero frequency.

[0033] S1.4: Next, the radar pulse signal near the zero frequency is extracted and filtered by 128 times, so that the sampling rate of the data becomes 292.96875KHz, so that the radar pulse data with a low sampling rate to be stored is obtained, which is also convenient for the data storage in the subsequent step S2.

[0034] In this example, it can be seen that in step S1, since the sampling rate of the extracted data is 292.96875KHz, that is, one data is collected every about 3.41us, if the relationship between the starting position of the data storage and the position of the pulse start is uncertain, the rising edge of the interference signal will fluctuate greatly. For example, when storing a pulse signal, it may be stored before the pulse signal arrives and 5 data are stored, or it may start to store after the pulse arrives 5 data, anyway, it fluctuates between the two, then the rising edge of the actual pulse will be compared with the rising edge position of the expected pulse, there will be a fluctuation of ±17.05us, which has a great impact on the target position. If the speed of light is calculated as 300m / us, the rising edge of the actual pulse will differ from the rising edge of the expected pulse by 1us, and the target position will differ by 150m (the radar signal is round-trip, so the calculated distance should be divided by 2).

[0035] Therefore, before storing radar data, it is necessary to determine the starting position of the data storage to ensure that the positional relationship between the starting position of the data storage and the beginning of the pulse is fixed. Therefore, in step S2, this method uses the half-power point as the starting position and end position of the pulse signal, and shows how to find the half-power point of the pulse signal.

[0036] An example of step S2 is as follows: In most cases, radar pulse data looks like this: Figure 3 As shown, it is not a standard rectangular pulse signal, because the pulse needs a period of time to rise and fall. To find the half-power point of the pulse, it is necessary to first determine the power or amplitude of the pulse signal, because the power of the pulse signal minus 3db or the pulse signal amplitude minus 6db is the size of its half-power point. Figure 3 It can be seen that the amplitude value of the pulse rising edge stage is constantly increasing, so we only need to find the first maximum value in the rising edge stage, which is the first standard maximum value. This maximum value is the amplitude of the pulse signal, and it is the half-power point after subtracting 6db. When the signal amplitude is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and the pulse data is stored from the time the detection signal is 1.

[0037] In actual process, the rising and falling edges of radar pulse signals may not be as Figure 3 As shown, it is not as smooth as Figure 4 As shown in the figure, there are many burrs, so the first N maximum values ​​in the rising edge stage are not standard maximum values, and are not the amplitude of the pulse signal. When the accuracy requirement is high, a more accurate method is needed to determine the amplitude of the pulse signal. Figure 4It can be seen that the overall trend of the rising edge stage is getting bigger, so the data on the right side of each maximum point in the rising edge stage are summed, and the result of the sum is averaged and compared with the amplitude of the maximum point. If the difference between the amplitude values ​​of the two is within 3db, the maximum point is used as the first standard maximum, and the corresponding amplitude is used as the radar pulse amplitude, otherwise the next maximum point is verified. After finding the maximum point that meets the conditions as the first standard maximum, subtract 6db from the amplitude of the first standard maximum to get the amplitude of the half-power point. When the signal amplitude is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and the pulse data is stored from the time the detection signal is 1.

[0038] The present invention provides an improved method for determining the storage starting position of pulse data with a low sampling rate. Compared with the conventional method, this method changes the manually set detection threshold into a threshold automatically generated according to the actual pulse signal amplitude, avoiding the starting position of data storage from being affected by the change of signal amplitude. The starting position of data storage is made more stable, and the position of the interference target that is delayed and forwarded later is also relatively stable, which has a better interference effect.

[0039] The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages: 1. This sampling storage method changes the conventional manually set detection threshold into a detection threshold automatically generated according to the signal amplitude, thereby preventing the starting position of data storage from being affected by changes in the signal amplitude.

[0040] 2. This sampling and storage method provides a further improvement plan for the glitches that may exist in the rising edge stage of the pulse signal, that is, a more accurate method is used to determine the amplitude of the radar pulse signal to ensure that the detection threshold generated by the pulse signal amplitude is correct.

[0041] 3. This sampling and storage method processes the acquired radar pulse signal in multiple steps, which reduces the sampling rate and the amount of data required to be stored, making it easier to store subsequent data.

[0042] Figure 5 This is a structural block diagram of a radar pulse signal sampling and storage device based on FPGA provided by an embodiment of the present invention. Based on the above radar pulse signal sampling and storage method, the device includes: A processing module is used to acquire radar pulse signals and perform sampling, and obtain radar pulse data to be stored after processing; A storage module is used to obtain the half-power point from the radar pulse data, and starts storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point of the rising edge of the radar pulse data.

[0043] Figure 5 The functions of each module in the embodiment correspond to the contents in the corresponding method embodiment and will not be repeated here.

[0044] Figure 3 The schematic diagram of the structure of the electronic device 60 provided in the embodiment of the present invention is shown, and the electronic device 60 includes at least one processor 601 (such as a CPU), at least one input and output interface 604, a memory 602, and at least one communication bus 603, which is used to realize the connection and communication between these components. At least one processor 601 is used to execute the computer instructions stored in the memory 602, so that the at least one processor 601 can execute any embodiment of the aforementioned radar pulse signal sampling and storage method. The memory 602 is a non-transitory memory, which may include a volatile memory, such as a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection with at least one other device or unit is realized through at least one input and output interface 604 (which may be a wired or wireless communication interface).

[0045] In some implementations, the memory 602 stores a program 6021, and the processor 601 executes the program 6021 to execute the content of any of the aforementioned table partitioning method embodiments.

[0046] The electronic device may exist in a variety of forms, including but not limited to: (1) Mobile communication equipment: This type of equipment is characterized by having mobile communication functions and its main purpose is to provide voice and data communications. This type of terminal includes: smart phones, multimedia phones, functional phones, and low-end phones.

[0047] (2) Ultra-mobile personal computer devices: These devices fall into the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access features. These terminals include: PDA, MID, and UMPC devices.

[0048] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players, handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0049] (4) Specific servers: devices that provide computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to the general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, manageability, etc.

[0050] (5) Other electronic devices with data interaction functions.

[0051] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0052] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0053] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A radar pulse signal sampling and storage method based on FPGA, characterized in that: The following steps are involved: S1: Acquire radar pulse signals and perform sampling, and obtain radar pulse data to be stored after processing; S2: Obtain a half-power point from the radar pulse data, and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data.

2. The radar pulse signal sampling and storage method according to claim 1, characterized in that: The step S1 is specifically as follows: S1.1: Acquire the radar pulse signal and perform sampling to obtain a sampling signal; S1.2: performing orthogonal down-conversion and first-level filtering on the sampled signal; S1.3: performing secondary down-conversion processing on the sampled signal after the primary filtering; S1.4: performing multiple decimation and secondary filtering on the sampled signal after the secondary down-conversion processing to obtain the radar pulse data to be stored.

3. The radar pulse signal sampling and storage method according to claim 2, characterized in that: In step S1.3, the secondary down-conversion processing method is as follows: The sampling signal after the first-stage filtering is copied into two copies, one of which is temporarily stored in RAM, and the other is subjected to FFT processing. The FFT peak is compared with the set threshold, and the frequency of the sampling signal is calculated based on the position of the peak that exceeds the threshold. This frequency is used as the local oscillator to perform secondary down-conversion on the cached sampling signal.

4. The radar pulse signal sampling and storage method according to claim 1, characterized in that: In the step S2, when the signal amplitude is smaller than the half power point for the first time, data storage is stopped.

5. The radar pulse signal sampling and storage method according to claim 4, characterized in that: In step S2, the stored data is triggered by a detection signal. When the signal amplitude in the radar pulse data is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and data storage begins when the detection signal is first set to 1. When the signal amplitude in the radar pulse data is less than the amplitude of the half-power point, the detection signal is set to 0, and data storage stops when the detection signal is first set to 0.

6. The radar pulse signal sampling and storage method according to claim 1, characterized in that: In step S2, the first standard maximum point is obtained as follows: The maximum point in the rising edge phase of the radar pulse data is obtained, and the amplitude average of multiple data points subsequent to the maximum point is obtained, and the amplitude average is compared with the amplitude corresponding to the maximum point; if the difference is less than a set value, the maximum point is used as the first standard maximum point, otherwise the next maximum point after the maximum point is obtained and verified again until the first standard maximum point is obtained.

7. The radar pulse signal sampling and storage method according to claim 6, characterized in that: In the step S2, a noise floor threshold is also set, and the maximum value point is greater than the noise floor threshold.

8. The radar pulse signal sampling and storage method according to claim 1, characterized in that: In the step S2, the set value is set to 6db.

9. A radar pulse signal sampling and storage device based on FPGA, characterized in that: The radar pulse signal sampling and storage method according to any one of claims 1 to 8 further comprises: A processing module, used to acquire the radar pulse signal and perform sampling, and obtain the radar pulse data to be stored after processing; A storage module is used to obtain the half-power point from the radar pulse data, and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude corresponding to the first standard maximum point of the rising edge of the radar pulse data.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the radar pulse signal sampling and storage method according to any one of claims 1 to 8 are implemented.

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