Storage device and method for operating the storage device

Abstract

The present disclosure relates to a storage device and a method for operating the storage device. The storage device may be provided with a plurality of partitions, each of the plurality of partitions including one or more storage blocks among a plurality of storage blocks. When a sudden power failure is detected during a write operation to a target partition among the plurality of partitions, the storage device may write virtual data to the target partition during a recovery operation of the sudden power failure. When data having a size matching the size of the virtual data is written to the target partition after the virtual data is written, the storage device may write the data to a target storage block outside the target partition.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0131357 filed on October 4, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a storage device that performs a sudden power failure recovery operation on a target partition, and a method of operating the storage device. Background Art

[0004] The storage device is a device for storing data in accordance with a request from an external device such as a computer, a mobile terminal (eg, a smartphone or a tablet), or the like.

[0005] The storage device may include a memory for storing data and a controller for controlling the memory. The memory may be a volatile memory or a non-volatile memory. The controller may receive a command from an external device (e.g., a host) and execute or control an operation of reading, writing, or erasing data in the memory according to the received command.

[0006] According to a request of an external device, the storage device may set a plurality of partitions. The memory may include a plurality of storage blocks, and each of the plurality of storage blocks may be included in one of the plurality of partitions. Summary of the invention

[0007] Various embodiments of the disclosed technology are directed to providing a storage device capable of preventing performance degradation of a partition due to sudden power failure, and a method of operating the storage device.

[0008] On the one hand, a storage device may include: i) a memory including multiple storage blocks, each of the multiple storage blocks including multiple pages; and ii) a controller configured to set multiple partitions according to a request of a host, each of the multiple partitions including one or more storage blocks among the multiple storage blocks, when a sudden power outage is detected during a write operation to a target partition among the multiple partitions, write virtual data to the target partition during a recovery operation of the sudden power outage, and after the virtual data is written to the target partition, write data with a size matching the size of the virtual data to a target storage block among the multiple storage blocks that is located outside the target partition in response to a write request from the host to the target partition.

[0009] On the other hand, a method for operating a storage device may include: i) setting multiple partitions according to a request of a host, each of the multiple partitions including one or more storage blocks among a plurality of storage blocks included in the storage device; ii) detecting a sudden power failure during a write operation to a target partition among the multiple partitions; iii) writing virtual data to the target partition during a recovery operation of the sudden power failure; iv) after writing the virtual data to the target partition, receiving a write request for the target partition from the host; and v) in response to the write request, writing data whose size matches that of the virtual data to a target storage block among the multiple storage blocks that is located outside the target partition.

[0010] According to an embodiment of the disclosed technology, the performance of a partition can be prevented from being degraded due to a sudden power failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 It is schematically shown Figure 1 Block diagram of the memory.

[0013] Figure 3 is a diagram showing a schematic structure of a storage device according to an embodiment of the present disclosure.

[0014] Figure 4 is a diagram illustrating an operation of detecting a sudden power failure according to an embodiment of the present disclosure.

[0015] Figure 5 is a diagram illustrating an operation of writing dummy data during a recovery operation of a sudden power failure according to an embodiment of the present disclosure.

[0016] Figure 6 is a diagram illustrating an operation of writing first data according to an embodiment of the present disclosure.

[0017] Figure 7 is a diagram illustrating an operation of generating mapping information according to an embodiment of the present disclosure.

[0018] Figure 8 is a diagram illustrating an operation of writing second data according to an embodiment of the present disclosure.

[0019] Fig. 9 is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the specification, references to "an embodiment," "another embodiment," etc. are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily limited to the same embodiment. When the term "embodiment" is used herein, it does not necessarily refer to all embodiments.

[0021] Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. However, the present invention may be embodied in different forms and variations and should not be construed as being limited to the embodiments set forth herein. On the contrary, the described embodiments are provided to make the present disclosure comprehensive and complete and to fully convey the present invention to those skilled in the art to which the present invention belongs. Throughout the entire disclosure, similar reference numerals represent similar components throughout the various figures and embodiments of the present invention.

[0022] The methods, processes and / or operations described herein may be performed by codes or instructions run by a computer, processor, controller or other signal processing device. The computer, processor, controller or other signal processing device may be a device described herein or may be an element other than the elements described herein. Because the algorithms underlying the methods (or the operations of the computers, processors, controllers or other signal processing devices) are described in detail, the codes or instructions for implementing the operations of the method embodiments may convert the computer, processor, controller or other signal processing device into a dedicated processor for performing the methods herein.

[0023] When implemented at least partially in software, controllers, processors, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device.

[0024] Figure 1 is a schematic configuration diagram of a storage device 100 according to an embodiment of the present disclosure.

[0025] Reference Figure 1 , the storage device 100 may include a memory 110 that stores data and a controller 120 that controls the memory 110 .

[0026] The memory 110 includes a plurality of memory blocks, and operates under the control of the controller 120. The operation of the memory 110 may include a read operation, a program operation (also referred to as a write operation), and an erase operation.

[0027] The memory 110 may include a memory cell array including a plurality of memory cells (also simply referred to as “cells”) storing data.

[0028] For example, the memory 110 may be implemented as various types of memories such as double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, Rambus dynamic random access memory (RDRAM), NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc.

[0029] The memory 110 may be implemented in a three-dimensional array structure. For example, the embodiments of the present disclosure may be applied to a charge trap flash (CTF) memory in which a charge storage layer is configured by a dielectric layer and a flash memory in which a charge storage layer is configured by a conductive floating gate.

[0030] The memory 110 may receive a command and an address from the controller 120 and may access a region selected by the address in the memory cell array. In other words, the memory 110 may perform an operation indicated by the command on the region selected by the address.

[0031] The memory 110 may perform a programming operation, a reading operation, or an erasing operation. For example, when performing a programming operation, the memory 110 may program data to an area selected by an address. When performing a reading operation, the memory 110 may read data from an area selected by an address. In an erasing operation, the memory 110 may erase data stored in an area selected by an address.

[0032] The controller 120 may control a write (or program) operation, a read operation, an erase operation, and a background operation for the memory 110. For example, the background operation may include at least one of a garbage collection (GC) operation, a wear leveling (WL) operation, a read reclaim (RR) operation, a bad block management (BBM) operation, and the like.

[0033] The controller 120 may control the operation of the memory 110 according to a request from a device (eg, a host) located outside the storage device 100. However, the controller 120 may also control the operation of the memory 110 without a request from the host.

[0034] As non-limiting examples, the host may be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configuring a data center, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID (radio frequency identification) device, and a mobile device (e.g., a vehicle, a robot, or a drone) capable of operating under human control or autonomous driving. Alternatively, the host may be a virtual reality (VR) device providing a 2D or 3D virtual reality image or an augmented reality (AR) device providing an augmented reality image. The host may be any of various electronic devices that require a storage device 100 capable of storing data.

[0035] The host may include at least one operating system (OS). The OS may generally manage and control functions and operations of the host, and may control interoperability between the host and the storage device 100. The OS may be classified into a general OS and a mobile OS according to the mobility of the host.

[0036] The controller 120 and the host may be separate devices from each other, or the controller 120 and the host may be integrated into one device. Hereinafter, for convenience of explanation, the controller 120 and the host are described as separate devices from each other.

[0037] Reference Figure 1 , the controller 120 may include a memory interface 122 and a control circuit 123 , and may further include a host interface 121 .

[0038] The host interface 121 provides an interface for communicating with the host. For example, the host interface 121 provides an interface using at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol.

[0039] When receiving a command from the host, the control circuit 123 may receive the command through the host interface 121 and may perform an operation of processing the received command.

[0040] The memory interface 122 may be coupled with the memory 110 to provide an interface for communicating with the memory 110. That is, the memory interface 122 may be configured to provide an interface between the memory 110 and the controller 120 under the control of the control circuit 123.

[0041] The control circuit 123 performs general control operations of the controller 120 to control the operation of the memory 110. To this end, for example, the control circuit 123 may include at least one of the processor 124 or the working memory 125, and may optionally include an error detection and correction circuit (ECC circuit) 126.

[0042] The processor 124 may control general operations of the controller 120 and may perform logic calculations. The processor 124 may communicate with the host through the host interface 121 and may communicate with the memory 110 through the memory interface 122.

[0043] The processor 124 may execute logic operations required to perform the functions of the flash translation layer (FTL). The processor 124 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the flash translation layer. The flash translation layer may receive the logical block address and convert the logical block address into a physical block address by using a mapping table.

[0044] The flash translation layer has a variety of address mapping methods according to the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0045] The processor 124 may randomize the data received from the host. For example, the processor 124 may randomize the data received from the host by using a set randomization seed. The randomized data may be provided to the memory 110 and may be programmed into the memory cell array of the memory 110.

[0046] In a read operation, the processor 124 may derandomize the data received from the memory 110. For example, the processor 124 may derandomize the data received from the memory 110 by using a derandomization seed. The derandomized data may be output to the host.

[0047] The processor 124 may run firmware to control the operation of the controller 120. That is, in order to control the general operation of the controller 120 and perform logical calculations, the processor 124 may run (or drive) the firmware loaded into the working memory 125 at startup. Hereinafter, the operation of the storage device 100 according to an embodiment of the present disclosure will be described as implementing the processor 124 running the firmware that defines the corresponding operation.

[0048] The firmware, which is a program to be executed in the storage device 100 to drive the storage device 100, may include various functional layers. For example, the firmware may include binary data defining codes for respectively executing the functional layers.

[0049] For example, the firmware may include at least one of a flash translation layer, a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer performs a conversion function between a logical address requested by the host to the storage device 100 and a physical address of the memory 110, the host interface layer is used to analyze a command requested by the host to the storage device 100 and transmit the command to the flash translation layer, and the flash interface layer transmits the command indicated by the flash translation layer to the memory 110.

[0050] Such firmware may be loaded into the working memory 125 from, for example, the memory 110 or a separate non-volatile memory (e.g., ROM or NOR flash) located outside the memory 110. The processor 124 may first load all or part of the firmware into the working memory 125 when running a startup operation after power-on.

[0051] The processor 124 may execute the logic calculations defined in the firmware loaded into the working memory 125 to control the general operation of the controller 120. The processor 124 may store the results of executing the logic calculations defined in the firmware in the working memory 125. The processor 124 may control the controller 120 according to the results of executing the logic calculations defined in the firmware, so that the controller 120 generates a command or signal. When a portion of the firmware defining the logic calculations to be executed is stored in the memory 110 but is not loaded into the working memory 125, the processor 124 may generate an event (e.g., an interrupt) to load the corresponding portion of the firmware from the memory 110 into the working memory 125.

[0052] The processor 124 may load metadata required for driving firmware from the memory 110. As metadata for managing data of the memory 110, management information on user data stored in the memory 110 may be included.

[0053] The firmware may be updated during the manufacturing process of the storage device 100 or during its operation. The controller 120 may download new firmware from an external source outside the scope of the storage device 100 and update the existing firmware with the new firmware.

[0054] In order to drive the controller 120, the working memory 125 may store necessary firmware, program code, commands, and data. The working memory 125 may be a volatile memory including, for example, at least one of a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous DRAM (SDRAM). On the other hand, in addition to the working memory 125, the controller 120 may also use a separate volatile memory (e.g., SRAM or DRAM) located outside the controller 120.

[0055] The error detection and correction circuit 126 may detect an error bit of the target data by using an error correction code and correct the detected error bit. The target data may be data stored in the working memory 125 or data read from the memory 110.

[0056] The error detection and correction circuit 126 can decode the data by using an error correction code. The error detection and correction circuit 126 can be implemented using various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0057] For example, when the read data consists of a plurality of sectors, the error detection and correction circuit 126 can detect an error bit in each set sector in the read data. A sector can be a data unit smaller than a page, which is used as a read unit of a flash memory. A plurality of sectors constituting the read data can be matched with each other using addresses.

[0058] The error detection and correction circuit 126 may calculate a bit error rate (BER) on a sector-by-sector basis and may determine whether the error is correctable. For example, when the bit error rate is higher than a reference value, the error detection and correction circuit 126 may determine that the corresponding sector is uncorrectable or failed. On the other hand, when the bit error rate is lower than a reference value, the error detection and correction circuit 126 may determine that the corresponding sector is correctable or passed.

[0059] The error detection and correction circuit 126 may sequentially perform error detection and correction operations on all read data. In the event that a sector included in the read data is found to be correctable, the error detection and correction circuit 126 may skip error detection and correction operations on the corresponding sector in the next set of read data. If the error detection and correction operations on all read data are completed in this manner, the error detection and correction circuit 126 may detect an uncorrectable sector in the last set of read data. One or more sectors may be determined to be uncorrectable. The error detection and correction circuit 126 may transmit information (e.g., address information) about the uncorrectable sector to the processor 124.

[0060] The bus 127 may be configured to provide a channel between the components 121, 122, 124, 125, and 126 of the controller 120. The bus 127 may include a control bus for transmitting various control signals, commands, etc., a data bus for transmitting various data, etc.

[0061] Some of the above components 121, 122, 124, 125, and 126 of the controller 120 may be omitted, or some of the above components 121, 122, 124, 125, and 126 of the controller 120 may be integrated into one component. In addition to the above components 121, 122, 124, 125, and 126 of the controller 120, one or more other components may be added.

[0062] In the following, reference will be made to Figure 2 The memory 110 is described in further detail.

[0063] Figure 2 It is schematically shown Figure 1 A block diagram of the memory 110 is shown.

[0064] Reference Figure 2 , the memory 110 may include a memory cell array 210 , an address decoder 220 , a read and write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0065] The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz (where z is a natural number of 2 or more).

[0066] In the plurality of memory blocks BLK1 to BLKz, a plurality of word lines WL and a plurality of bit lines BL may be provided.

[0067] The plurality of memory blocks BLK1 to BLKz may be coupled to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1 to BLKz may be coupled to the read and write circuit 230 through a plurality of bit lines BL.

[0068] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the plurality of memory cells may be nonvolatile memory cells and may be configured of nonvolatile memory cells having a vertical channel structure.

[0069] The memory cell array 210 may be configured by a memory cell array of a two-dimensional structure, or may be configured by a memory cell array of a three-dimensional structure.

[0070] Each of the plurality of memory cells included in the memory cell array 210 may store at least 1 bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-layer cell (SLC) storing 1 bit of data. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-layer cell (MLC) storing 2 bits of data. In yet another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-layer cell (TLC) storing 3 bits of data. In yet another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-layer cell (QLC) storing 4 bits of data. In a further example, the memory cell array 210 may include a plurality of memory cells, each of which stores 5 or more bits of data.

[0071] The number of bits of data stored in each of the plurality of memory cells can be dynamically determined. For example, a single-layer cell storing 1 bit of data can be changed to a triple-layer cell storing 3 bits of data.

[0072] Reference Figure 2 , the address decoder 220 , the read and write circuit 230 , the control logic 240 , and the voltage generating circuit 250 may operate as peripheral circuits for driving the memory cell array 210 .

[0073] The address decoder 220 may be coupled to the memory cell array 210 through a plurality of word lines WL.

[0074] The address decoder 220 may be configured to operate under the control of the control logic 240 .

[0075] The address decoder 220 may receive an address through an input / output buffer in the memory 110. The address decoder 220 may be configured to decode a block address in the received address. The address decoder 220 may select at least one memory block according to the decoded block address.

[0076] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0077] During a read operation, the address decoder 220 may apply a read voltage Vread to a selected word line WL coupled to a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL coupled to the selected memory block.

[0078] During a program verification operation, the address decoder 220 may apply a verification voltage generated in the voltage generation circuit 250 to a selected word line WL coupled to a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL coupled to the selected memory block.

[0079] The address decoder 220 may be configured to decode the column address in the received address. The address decoder 220 may send the decoded column address to the read and write circuit 230.

[0080] The read operation and the program operation of the memory 110 may be performed page by page. The address received when requesting the read operation or the program operation may include at least one of a block address, a row address, and a column address.

[0081] The address decoder 220 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read and write circuit 230.

[0082] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0083] The read and write circuit 230 may include a plurality of page buffers PB. The read and write circuit 230 may be used as a read circuit in a read operation of the memory cell array 210 and may be used as a write circuit in a write operation of the memory cell array 210.

[0084] The above-mentioned read and write circuit 230 may also be referred to as a page buffer circuit or a data register circuit including a plurality of page buffers PB. The read and write circuit 230 may include a data buffer responsible for a data processing function, and may further include a cache buffer responsible for a cache function.

[0085] The plurality of page buffers PB may be coupled to the memory cell array 210 through the plurality of bit lines BL. The plurality of page buffers PB may continuously provide a sensing current to the bit lines BL coupled to the memory cells in a read operation and a program verification operation to sense a threshold voltage (Vth) of the memory cells, and may latch sensing data by sensing a change in the amount of current flowing through the bit lines BL caused by a programming state of the memory cells through a sensing node.

[0086] The read and write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0087] In a read operation, the read and write circuit 230 temporarily stores read data DATA by sensing data of a memory cell and then outputs the data DATA to an input / output buffer of the memory 110. In an embodiment, the read and write circuit 230 may further include a column selection circuit in addition to the page buffer PB or the page register.

[0088] The control logic 240 may be coupled to the address decoder 220, the read and write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory 110.

[0089] The control logic 240 may be configured to control a general operation of the memory 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting a precharge potential level of a sensing node of a plurality of page buffers PB.

[0090] The control logic 240 may control the read and write circuit 230 to perform a read operation of the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass for a read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0091] Each memory block of the above-described memory 110 may be configured with a plurality of pages corresponding to a plurality of word lines WL and a plurality of strings corresponding to a plurality of bit lines BL.

[0092] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged to cross each other. For example, each of the plurality of word lines WL may be arranged along a row direction, and each of the plurality of bit lines BL may be arranged along a column direction. Alternatively, each of the plurality of word lines WL may be arranged along a column direction, and each of the plurality of bit lines BL may be arranged along a row direction.

[0093] The memory cell may be coupled to one of a plurality of word lines WL and one of a plurality of bit lines BL. A transistor may be provided in each memory cell.

[0094] For example, the transistor provided in each memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be directly or via another transistor coupled to a corresponding bit line BL. The source (or drain) of the transistor may be directly or via another transistor coupled to a source line (which may be grounded). The gate of the transistor may include a floating gate surrounded by a dielectric and a control gate to which a gate voltage is applied from a word line WL.

[0095] In each memory block, a first selection line (also called a source selection line or a drain selection line) may be additionally set outside a first outermost word line of the two outermost word lines that is closer to the read and write circuit 230, and a second selection line (also called a drain selection line or a source selection line) may be additionally set outside a second outermost word line of the two outermost word lines.

[0096] At least one dummy word line may be disposed between the first outermost word line and the first selection line. In addition, at least one dummy word line may be disposed between the second outermost word line and the second selection line.

[0097] The read operation and the program operation (or the write operation) of the above-mentioned memory block may be performed page by page, and the erase operation may be performed on a memory block basis.

[0098] Figure 3 FIG. 1 shows a schematic structure of a storage device 100 according to an embodiment of the disclosed technology.

[0099] Reference Figure 3 , the storage device 100 may include a memory 110 and a controller 120 .

[0100] The memory 110 may include a plurality of memory blocks BLK. Each of the plurality of zones ZONE may include one or more memory blocks BLK. Data stored in each zone ZONE may be managed according to a block mapping scheme.

[0101] Each of the plurality of memory blocks BLK may include a plurality of pages PG.

[0102] The multiple zones ZONEs may be managed by a host HOST connected to the storage device 100. The host HOST may request the storage device 100 to create multiple zones ZONEs, write data to multiple zones ZONEs, and delete or reset some of the multiple zones ZONEs.

[0103] When writing data to one of the multiple zones, the host HOST may write the data to the corresponding zones in sequence. In this case, the data already stored in the corresponding zones will not be updated. To this end, the host HOST may manage a write pointer for each of the multiple zones, which indicates the location of the data to be written in each zone.

[0104] Once the host HOST has fully used the storage capacity of the specific partition ZONE, as indicated by the write pointer reaching the end of the specific partition ZONE, all storage blocks mapped to the specific partition ZONE are fully filled with data. In this case, since there is no free space in the specific partition ZONE that is neither stored in data nor wasted, the host HOST can use the specific partition ZONE efficiently.

[0105] The controller 120 may set a plurality of zones ZONE according to a request of the host HOST. Each of the plurality of zones ZONE may include at least one of the plurality of memory blocks BLK included in the memory 110.

[0106] The controller 120 may control a write operation of the memory 110 according to a request of the host HOST, and may write data into one zone ZONE among a plurality of zones ZONE.

[0107] When the storage device 100 writes data into one of the multiple zones ZONE according to a request from the host HOST, a sudden power failure may occur in which the power supply is abnormally suspended. This will be described in detail below.

[0108] Figure 4 is a diagram showing the operation of detecting a sudden power failure according to an embodiment of the disclosed technology. The operation can be referred to above Figure 3 The storage device 100 described here performs.

[0109] Reference Figure 4 The storage device 100 may receive a request from the host HOST instructing it to write data to a target partition TGT_ZONE among multiple partitions ZONE, and may then write the data to the target partition TGT_ZONE in response to the request.

[0110] exist Figure 4 In the example embodiment, when performing an operation of writing data to the target zone TGT_ZONE, the storage device 100 may detect the occurrence of a sudden power off (SPO). This detection may be considered to be the occurrence of SPO when the duration of the supplied power level being lower than the reference level is equal to or longer than the reference time.

[0111] After detecting a sudden power failure, the operation of writing data to the target partition TGT_ZONE is suspended, which causes the integrity of the data stored in the target partition TGT_ZONE to fail.

[0112] When power supply is restored after a sudden power failure occurs, the storage device 100 may perform a recovery operation for the sudden power failure. By performing the recovery operation, the storage device 100 may resolve the failure in the storage device 110 due to the sudden power failure, and may reduce the possibility of future failures in the storage device 110. Figure 5 This is described in detail.

[0113] Figure 5 is a diagram illustrating an operation of writing dummy data as a part of a recovery operation specifically for resolving a sudden power failure according to an embodiment of the disclosed technology.

[0114] Reference Figure 5 When power is restored after a sudden power outage, the controller 120 of the storage device 100 may write virtual data into the target partition TGT_ZONE. The size of the virtual data may be a first size SIZE_1.

[0115] To this end, the controller 120 may search for the last used page when the power is suddenly turned off among the memory blocks included in the target partition TGT_ZONE. The controller 120 may check whether an uncorrectable error correction code (UECC) occurs in a page within a predetermined range starting from the searched page, and may write dummy data to the corresponding page to enhance the reliability of the target partition TGT_ZONE.

[0116] Since the writing of virtual data into the memory 110 is controlled by the controller 120, the portion of the memory block storing the virtual data will not be accessed by the host HOST, so that the host HOST can be prevented from accessing the area that fails due to a sudden power failure.

[0117] In embodiments of the disclosed technology, the virtual data may have various patterns. For example, the virtual data may be a repeating sequence of a specific bit pattern. Alternatively, the virtual data may have random bit values.

[0118] The first size SIZE_1 may be a preset value. For example, the first size SIZE_1 may be a multiple of a page size included in each of the plurality of memory blocks BLK.

[0119] In this way, when dummy data is written to the target partition TGT_ZONE after a sudden power failure occurs, there may be a mismatch between the write pointer of the target partition TGT_ZONE managed by the host HOST and the size of data actually stored in the target partition TGT_ZONE.

[0120] As described above, the controller 120 writes the virtual data autonomously without any request from the host HOST. Therefore, although the virtual data is written, the host HOST will not change the write pointer of the target partition TGT_ZONE. In this case, although the write pointer of the target partition TGT_ZONE remains unchanged, the data size stored in the target partition TGT_ZONE will increase.

[0121] Therefore, when the host HOST writes data of a predetermined size into the target partition TGT_ZONE, a blank space without data storage may appear in the storage block where the data was last written in the target partition TGT_ZONE, that is, unoccupied space, which may cause the performance of the target partition TGT_ZONE to degrade.

[0122] Therefore, solving the mismatch problem caused by writing virtual data becomes very important for the storage device 100. Figure 6 This is described in detail.

[0123] Figure 6 is a diagram illustrating an operation of writing first data DATA_1 according to an embodiment of the disclosed technology.

[0124] After writing the virtual data to the target partition TGT_ZONE, the controller 120 of the storage device 100 may receive a write request for the target partition TGT_ZONE from the host HOST. Figure 6 , the controller 120 may receive a write request from the host HOST instructing it to write the first data DATA_1 into the target zone TGT_ZONE. The first data DATA_1 may include a whole set of data or a portion of data requested to be written by the host HOST.

[0125] At this time, the target partition TGT_ZONE may be in a state where no other data is expected to be written after the insertion of the dummy data mentioned above. That is, the target partition TGT_ZONE may be full of data.

[0126] The host HOST may send a write request instructing to write the first data DATA_1 into the target zone TGT_ZONE to the controller 120 in various ways.

[0127] For example, the host HOST may divide the write request into a plurality of write commands and send the plurality of write commands to the controller 120 .

[0128] Alternatively, the host HOST may send a write request including the first data DATA_1 to the controller 120 .

[0129] In response to the write request, the controller 120 may write the first data DATA_1 to a designated memory block different from the memory blocks included in the target zone TGT_ZONE among the plurality of memory blocks BLK.

[0130] exist Figure 6 In the example, the designated memory block may be the first memory block BLK_1. The controller 120 may write the first data DATA_1 into the first memory block BLK_1. The first memory block BLK_1 may be selected from a memory block BLK that does not belong to the target zone TGT_ZONE among the plurality of memory blocks BLK.

[0131] For example, the first memory block BLK_1 may be a backup memory block that is not included in any zone ZONE among the plurality of zones ZONE.

[0132] The size of the first data DATA_1 may be a first size SIZE_1 which is a size corresponding to dummy data.

[0133] In this way, when the controller 120 writes the first data DATA_1 to the first storage block BLK_1, the controller 120 can efficiently resolve the mismatch between the write pointer of the target zone TGT_ZONE managed by the host HOST and the data size actually written to the target zone TGT_ZONE. This proactive measure can prevent the performance of the target zone TGT_ZONE from being degraded.

[0134] When the first data DATA_1 is written into the first storage block BLK_1 in this way, the storage device 100 should generate mapping information that allows the host HOST to access the first data DATA_1. This is because, although the host HOST attempts to write the first data DATA_1 into the target zone TGT_ZONE, the first storage block BLK_1 into which the first data DATA_1 is actually written is not part of the target zone TGT_ZONE.

[0135] Hereinafter, a specific embodiment of generating mapping information will be described.

[0136] Figure 7 is a diagram illustrating an operation of generating mapping information according to an embodiment of the disclosed technology.

[0137] Reference Figure 7 , the controller 120 of the storage device 100 may generate mapping information indicating a mapping relationship between an index corresponding to the first data DATA_1 in the target zone TGT_ZONE and a location where the first data DATA_1 is actually stored in the first storage block BLK_1 .

[0138] The index corresponding to the first data DATA_1 may indicate a relative position of the first data DATA_1 within the target zone TGT_ZONE.

[0139] The location where the first data DATA_1 is actually stored within the first memory block BLK_1 may indicate a physical location (eg, an address of a page) where the first data DATA_1 is actually stored.

[0140] exist Figure 7 In the target zone TGT_ZONE, the index corresponding to the first data DATA_1 is IDX_1. The actual storage location of the first data DATA_1 in the first storage block BLK_1 is LOC_1.

[0141] Therefore, the controller 120 may generate mapping information indicating that the index IDX_1 corresponding to the first data DATA_1 within the target zone TGT_ZONE and the location LOC_1 where the first data DATA_1 is actually stored within the first memory block BLK_1 are mapped to each other.

[0142] An index IDX_1 corresponding to the first data DATA_1 in the target partition TGT_ZONE and a location LOC_1 where the first data DATA_1 is actually stored in the first memory block BLK_1 may be mapped in units of a first size SIZE_1 , where the first size SIZE_1 indicates the size of the first data DATA_1 .

[0143] The mapping information may further include flag information indicating that the first data DATA_1 is stored in the first memory block BLK_1. Using the flag information, the controller 120 may recognize that the first data DATA_1 is not stored in a memory block within the target zone TGT_ZONE but is stored in the first memory block BLK_1 outside the target zone TGT_ZONE.

[0144] Figure 8 is a diagram illustrating an operation of writing second data DATA_2 according to an embodiment of the disclosed technology.

[0145] Reference Figure 8 , the controller 120 of the storage device 100 may write the additional data into the target partition TGT_ZONE after completing writing the first data DATA_1 into the first storage block BLK_1. For example, the controller 120 may write the second data DATA_2 into the target partition TGT_ZONE.

[0146] For example, the controller 120 may simultaneously receive a request from the host HOST indicating writing of both the first data DATA_1 and the second data DATA_2. Alternatively, the controller 120 may first receive a request from the host HOST indicating writing of the first data DATA_1 and then receive a different request from the host HOST indicating writing of the second data DATA_2.

[0147] The controller 120 may write the second data DATA_2 into a memory block located in the target partition TGT_ZONE among the plurality of memory blocks BLK. Figure 8 In the embodiment, the controller 120 may write the second data DATA_2 into the second storage block BLK_2 within the target zone TGT_ZONE.

[0148] Since the above-mentioned mismatch problem is solved by writing the first data DATA_1 into the first memory block BLK_1 , the controller 120 may write the second data DATA_2 into the target zone TGT_ZONE.

[0149] Fig. 9 is a diagram illustrating a method of operating a storage device according to an embodiment of the disclosed technology. Figures 3 to 7 Give a description.

[0150] Reference Fig. 9 At S910, the storage device 100 may set a plurality of partitions ZONE according to a request of the host HOST. As described above, the memory 110 may include a plurality of storage blocks BLK, and each of the plurality of partitions ZONE may include one or more of the plurality of storage blocks BLK.

[0151] At S920 , the storage device 100 may detect a sudden power failure in which power supply is suddenly cut off during a write operation with respect to a target zone TGT_ZONE among the plurality of zones ZONE.

[0152] At S930 , the storage device 100 may write virtual data to the target partition TGT_ZONE during the recovery operation of the sudden power failure.

[0153] At S940 , after writing the virtual data to the target partition TGT_ZONE, the storage device 100 may receive a write request for the target partition TGT_ZONE from the host HOST.

[0154] At S950 , in response to a write request for the target partition TGT_ZONE, the storage device 100 may write data whose size matches the size of the virtual data to a target storage block located outside the target partition TGT_ZONE among the plurality of storage blocks BLK.

[0155] For example, step S950 may include generating mapping information indicating a mapping relationship between an index corresponding to data in the target partition TGT_ZONE and a specific location where the data is stored in the target storage block.

[0156] The mapping information may additionally include flag information indicating that the data is actually stored in the target storage block.

[0157] The index corresponding to the data in the target partition TGT_ZONE and the specific location where the data is stored in the target storage block can be mapped in units of the size of the data.

[0158] The method may further include writing additional data into the target partition TGT_ZONE after completing writing the data into the target storage block. For example, writing the additional data into a storage block located in the target partition TGT_ZONE among the plurality of storage blocks BLK.

[0159] Although the exemplary embodiments of the present disclosure have been described for exemplary purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only in a descriptive sense, and not for limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted in conjunction with the attached claims, and include all equivalent schemes that fall within the scope of the attached claims.

Claims

1. A storage device, comprising: A memory, comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of pages; as well as Controller: A plurality of partitions are set according to a request of a host, each of the plurality of partitions comprising one or more storage blocks among the plurality of storage blocks, When a sudden power failure is detected during a write operation for a target partition among the plurality of partitions, writing dummy data to the target partition during a recovery operation of the sudden power failure, and After the virtual data is written to the target partition, in response to a write request from the host for the target partition, data having a size matching that of the virtual data is written to a target storage block located outside the target partition among the plurality of storage blocks.

2. The storage device according to claim 1, wherein: The size of the data is a multiple of the page size.

3. The storage device according to claim 1, wherein: When writing the data into the target storage block, the controller generates mapping information indicating a mapping relationship between an index corresponding to the data in the target partition and a location where the data is stored in the target storage block.

4. The storage device according to claim 3, wherein: The mapping information includes flag information indicating that the data is stored in the target storage block.

5. The storage device according to claim 3, wherein: The index corresponding to the data in the target partition and the location where the data is stored in the target storage block are mapped in units of the size of the data.

6. The storage device according to claim 1, wherein: When additional data is written to the target partition after the data is written to the target storage block, the controller writes the additional data to a storage block included in the target partition.

7. A method of operating a storage device, comprising: Setting a plurality of partitions according to a request of a host, each of the plurality of partitions including one or more storage blocks among a plurality of storage blocks included in the storage device; detecting a sudden power failure during a write operation to a target partition among the plurality of partitions; writing virtual data to the target partition during the recovery operation of the sudden power failure; After writing the virtual data to the target partition, receiving a write request for the target partition from the host; as well as In response to the write request, data having a size matching the size of the virtual data is written to a target storage block located outside the target partition among the plurality of storage blocks.

8. The method according to claim 7, wherein: Writing the data into the target storage block includes generating mapping information indicating a mapping relationship between an index corresponding to the data in the target partition and a location where the data is stored in the target storage block.

9. The method according to claim 8, wherein: The mapping information includes flag information indicating that the data is stored in the target storage block.

10. The method according to claim 8, wherein: The index corresponding to the data in the target partition and the location where the data is stored in the target storage block are mapped in units of the size of the data.

11. The method according to claim 7, further comprising: When the additional data is written to the target partition after the data is written to the target storage block, the additional data is written to the storage block included in the target partition.

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