Complex operation parallel acceleration method and system based on ARMNEON

Abstract

The invention provides a complex operation parallel acceleration method and system based on ARMNEON, and relates to the technical field of computers.The method comprises the steps that a computer provided with a Xilinx SDK is obtained, and the Xilinx SDK is an integrated development environment and used for developing an application program based on a Xilinx FPGA; configuring a hardware environment of the computer, the hardware environment comprising an ARM processor equipped with a NEON-supporting instruction set and sufficient memory to support NEON vector operation; selecting a cross-compiler and compiler options to configure a software environment of the computer; a GCC tool chain is used for carrying out abstract packaging on an NEON instruction set, the packaged NEON instruction set is fused into a C / C + + code so as to achieve an efficient parallel computing algorithm, and a target library supporting the NEON instruction set is used for development. Based on the ARMNEON architecture, parallel acceleration is realized in the aspect of complex operation, so that the calculation performance is remarkably improved. By fully utilizing the parallel computing capability of the ARMNEON, a plurality of computing tasks can be processed at the same time, and the computing time is greatly shortened.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a complex number operation parallel acceleration method and system based on ARM_NEON. Background Art

[0002] In today's science and technology field, with the rapid growth of data volume and computational complexity, the traditional serial computing model is no longer applicable. In order to meet this challenge and improve computing efficiency, the introduction of parallel computing is an effective solution. Parallel computing covers the technology of executing multiple computing tasks simultaneously on multiple processing units, by breaking down tasks into smaller subtasks and executing them simultaneously on different processing units to improve the overall computing speed and efficiency.

[0003] Complex number operations are a common data processing task, involving complex multiplication, addition and other operations. With the growing demand for complex complex number operations in fields such as signal processing and image processing, the speed of complex number operations has become the main constraint on the development of related algorithms, and it is urgent to improve the speed of complex number operations. It is urgent to accelerate the processing of complex number operations to meet the growing computing needs. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present application provides a complex number operation parallel acceleration method and system based on ARM_NEON, which solves the problem that the slow speed of complex number operations restricts the development of related algorithms.

[0005] To achieve the above objectives, this application is implemented through the following technical solutions:

[0006] In the first aspect, an embodiment of the present application provides a complex number operation parallel acceleration method based on ARM_NEON, and the complex number operation parallel acceleration method based on ARM_NEON includes: obtaining a computer configured with Xilinx SDK, XilinxSDK is an integrated development environment and is used to develop applications based on Xilinx FPGA; configuring the hardware environment of the computer, the hardware environment includes an ARM processor equipped with a NEON instruction set that supports the NEON instruction set, and sufficient memory to support NEON vector operations; selecting a cross-compiler and compiler options to configure the software environment of the computer; using the GCC tool chain to abstractly encapsulate the NEON instruction set, integrating the encapsulated NEON instruction set into the C / C++ code to implement an efficient parallel computing algorithm, and using a target library that supports the NEON instruction set for development.

[0007] According to a first aspect of an embodiment of the present application, the cross-compiler supports the ARM architecture and the NEON instruction set, and the compiler option is used to enable NEON instruction set support.

[0008] According to a first aspect of the embodiment of the present application, the CPU processor of the computer configured with Xilinx SDK is ARM-Cortex-A9; the target library includes at least one of a NEON-optimized math library, a multimedia processing library, and an image processing library.

[0009] According to the first aspect of the embodiment of the present application, the ARM_NEON-based complex number operation parallel acceleration method also includes: optimizing the NEON inline assembly instructions through a preset debugging strategy.

[0010] According to the first aspect of the embodiment of the present application, the aforementioned optimization of NEON's inline assembly instructions through a preset debugging strategy may specifically include: setting processor-specific compiler instructions to ensure that the project is configured correctly and supports the NEON instruction set; writing complex functions and using the NEON instruction set to optimize and accelerate the complex functions; the NEON instruction set supports complex operations by providing multiple vectorized instructions to process multiple data simultaneously; using the Xilinx SDK debugging tool to verify the correctness of the complex function, and using the performance analysis tool to evaluate the optimization effect of the NEON instruction set; ensuring data alignment and adjusting function order; integrating the complex function optimized by the NEON instruction set into the target application for calling; testing and verifying the target application to determine that the complex function optimized by the NEON instruction set can improve performance and produce correct results.

[0011] According to the first aspect of the embodiment of the present application, the aforementioned ensuring data alignment and adjusting function order may specifically include: in the case where the NEON instruction set is a NEON multiplication instruction, the NEON multiplication instruction generates a waiting time of 2 clock signals CLK through operation, and the operation of the previous step in the irrelevant code is interspersed in the waiting time of the 2 clock signals CLK to maximize the use of all time.

[0012] According to the first aspect of the embodiment of the present application, the aforementioned configuration of the computer's hardware environment may specifically include: establishing a vivado project, completing the PS and PL side configuration, and compiling the configured project export file; in the Ubuntu virtual machine development environment, ensuring that the Linux system kernel includes support for NEON, and that the system files include NEON-supported libraries, and generating image.ub files and BOOT.bin files; deploying the system image containing the hardware configuration and support for NEON functions to the Linux system of the board, completing the board Linux operating system deployment and transplantation; using Linux to configure the board IP, and uploading the BOOT.bin file and image.ub file produced according to the actual project to the corresponding partition of the board to complete the hardware preparation.

[0013] In a second aspect, an embodiment of the present application provides an ARM_NEON-based complex number operation parallel acceleration system, which includes an acquisition module, a hardware configuration module, a software configuration module and an encapsulation and integration module.

[0014] Specifically, the acquisition module is used to acquire a computer configured with Xilinx SDK, which is an integrated development environment and is used to develop applications based on Xilinx FPGA; the hardware configuration module is used to configure the computer's hardware environment, which includes an ARM processor equipped with a NEON instruction set that supports the NEON instruction set, and sufficient memory to support NEON vector operations; the software configuration module is used to select a cross-compiler and compiler options to configure the computer's software environment; the encapsulation and integration module is used to use the GCC tool chain to abstractly encapsulate the NEON instruction set, integrate the encapsulated NEON instruction set into the C / C++ code to implement efficient parallel computing algorithms, and use a target library that supports the NEON instruction set for development.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the ARM_NEON-based complex number operation parallel acceleration method in the aforementioned first aspect is implemented.

[0016] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the ARM_NEON-based complex number operation parallel acceleration method in the aforementioned first aspect is implemented.

[0017] This application provides a complex number operation parallel acceleration method and system based on ARM_NEON. Compared with the prior art, it has the following beneficial effects:

[0018] In order to accelerate complex operations in parallel, this application configures the Xilinx SDK integrated development environment on a computer to develop applications based on Xilinx FPGA; and further configures the computer's hardware and software environments, by setting an ARM processor that supports the NEON instruction set and sufficient memory to support NEON vector operations, determining the cross compiler and compiler options; using the GCC tool chain to abstractly encapsulate the NEON instruction set, and integrating the encapsulated NEON instruction set into the C / C++ code, thereby realizing an efficient parallel computing algorithm; this application is based on the ARM_NEON architecture, and uses the NEON instruction set to optimize complex operations, thereby increasing the speed of complex operations and reducing energy consumption; parallel acceleration is achieved in complex operations, thereby significantly improving computing performance. By making full use of the parallel computing capabilities of ARM_NEON, multiple computing tasks can be processed simultaneously, greatly shortening the computing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 This is a flowchart of a parallel acceleration method for complex number operations based on ARM_NEON provided in an embodiment of the present application;

[0021] Figure 2 It is an exemplary flow chart of another ARM_NEON-based complex number operation parallel acceleration method provided in an embodiment of the present application;

[0022] Figure 3 It is the internal design diagram of the ARM-Cortex-A9 processor provided in the embodiment of the present application;

[0023] Figure 4 It is a data storage block diagram based on ARM-NEON provided in an embodiment of the present application;

[0024] Figure 5 It is a comparison table of complex number operation execution results provided in an embodiment of the present application;

[0025] Figure 6 It is a structural diagram of a complex number operation parallel acceleration system based on ARM_NEON provided in an embodiment of the present application;

[0026] Figure 7It is a structural schematic diagram of another complex number operation parallel acceleration system based on ARM_NEON provided in an embodiment of the present application;

[0027] Figure 8 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0030] The embodiments of the present application provide a complex number operation parallel acceleration method and system based on ARM_NEON, thereby solving the problem that the slow speed of complex number operations restricts the development of related algorithms.

[0031] The technical solution in the embodiment of the present application is to solve the above technical problems, and the overall idea is as follows:

[0032] In today's science and technology field, with the rapid growth of data volume and computational complexity, the traditional serial computing model is no longer applicable. In order to meet this challenge and improve computing efficiency, the introduction of parallel computing is an effective solution. Parallel computing covers the technology of executing multiple computing tasks simultaneously on multiple processing units, by breaking down tasks into smaller subtasks and executing them simultaneously on different processing units to improve the overall computing speed and efficiency.

[0033] Complex number operations are a common data processing task, involving complex multiplication, addition and other operations. With the growing demand for complex complex number operations in fields such as signal processing and image processing, the speed of complex number operations has become the main constraint on the development of related algorithms, and it is urgent to improve the speed of complex number operations. It is urgent to accelerate the processing of complex number operations to meet the growing computing needs.

[0034] In the field of multimedia and artificial intelligence, the demand for processing and analyzing large-scale data is growing, so Single Instruction Multiple Data (SIMD) technology can be used to accelerate various types of calculations. Through parallel computing, these complex operations can be processed efficiently, the algorithm execution speed can be accelerated, and the real-time and responsiveness of the system can be improved.

[0035] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0036] The following first introduces a complex number operation parallel acceleration method based on ARM_NEON provided in an embodiment of the present application.

[0037] The present application embodiment provides a flowchart of a complex number operation parallel acceleration method based on ARM_NEON, such as Figure 1 As shown, the ARM_NEON-based complex number operation parallel acceleration method may include the following steps S110-S140.

[0038] S110. Obtain a computer configured with Xilinx SDK, where Xilinx SDK is an integrated development environment and is used to develop applications based on Xilinx FPGA.

[0039] S120. Configure the hardware environment of the computer, where the hardware environment includes an ARM processor that supports the NEON instruction set and sufficient memory to support NEON vector operations.

[0040] S130. Select a cross compiler and compiler options to configure the software environment of the computer.

[0041] S140. Use the GCC tool chain to abstract and encapsulate the NEON instruction set, integrate the encapsulated NEON instruction set into the C / C++ code to implement efficient parallel computing algorithms, and use the target library that supports the NEON instruction set for development.

[0042] The above is a specific implementation of the complex number operation parallel acceleration method based on ARM_NEON provided in the embodiment of the present application. It should be noted that NEON refers to an advanced single instruction multiple data SIMD extended instruction set applicable to ARM Cortex-A series processors. Using SIMD technology, more data processing can be completed in the same execution cycle, which also improves the data throughput per unit time and improves computing performance.

[0043] ARM Cortex-A series processors are a series of high-performance application processors, mainly for application areas with high-end computing needs, such as smartphones, mobile computing, in-car entertainment, autonomous driving, servers, etc. They support ARMv7 and ARMv8-A architectures and are compatible with earlier ARM processors.

[0044] NEON technology can accelerate multimedia and signal processing algorithms (such as video encoding / decoding, 2D / 3D graphics, games, audio and voice processing, image processing technology, telephone and sound synthesis). NEON can perform operations on some unique registers inside ARM to accelerate operations. NEON has the following specific features: (1) It supports integer and floating-point operations to ensure that it is suitable for a wide range of applications from codecs, high-performance computing to 3D graphics. (2) It is tightly integrated with the Arm processor, providing a unified view of the instruction stream and memory, making programming simpler than external hardware accelerators.

[0045] It can be understood that in order to accelerate the parallel operation of complex numbers, this application configures the Xilinx SDK integrated development environment on the computer to develop applications based on Xilinx FPGA; and further configures the computer's hardware environment and software environment, by setting up an ARM processor that supports the NEON instruction set and sufficient memory to support NEON vector operations, and determining the cross compiler and compiler options; uses the GCC tool chain to abstractly encapsulate the NEON instruction set, and integrates the encapsulated NEON instruction set into the C / C++ code, thereby realizing an efficient parallel computing algorithm.

[0046] This application is based on the ARM_NEON architecture and uses the NEON instruction set to optimize complex operations, thereby increasing the speed of complex operations and reducing energy consumption; it achieves parallel acceleration in complex operations, thereby significantly improving computing performance. By making full use of the parallel computing capabilities of ARM_NEON, multiple computing tasks can be processed simultaneously, greatly shortening the computing time. It can solve complex complex operations in fields such as signal processing and image processing, and improve the overall computing system processing capabilities.

[0047] In one example, the cross compiler supports the ARM architecture and the NEON instruction set, and the compiler option is used to enable the NEON instruction set support.

[0048] In another example, the CPU processor of the computer configured with Xilinx SDK is ARM-Cortex-A9. For the specific hardware design diagram of ARM-Cortex-A9, please refer to Figure 3 ; The target library includes at least one of a NEON-optimized math library, a multimedia processing library, and an image processing library.

[0049] In some embodiments, the aforementioned complex number operation parallel acceleration method based on ARM_NEON may also include: S150, optimizing the inline assembly instructions of NEON through a preset debugging strategy. It is understandable that in the SIMD instruction set of the ARM architecture, NEON is an extension for processing parallel calculations such as vector and image processing. Therefore, this application aims to explore how to use parallel computing technology, especially in combination with NEON technology, to accelerate complex number operations to meet the growing computing needs and improve system performance and efficiency.

[0050] In one example, the aforementioned optimization of the NEON inline assembly instructions by a preset debugging strategy, that is, the aforementioned S150 may specifically include the following steps:

[0051] S210. Set processor-specific compiler directives to ensure that the project is configured correctly and supports the NEON instruction set.

[0052] S220, write a complex function, and use the NEON instruction set to optimize and accelerate the complex function; the NEON instruction set supports complex operations by providing multiple vectorized instructions to process multiple data simultaneously.

[0053] S230. Use the debugging tools of Xilinx SDK to verify the correctness of complex functions, and use performance analysis tools to evaluate the optimization effect of NEON instruction set.

[0054] S240, ensuring data alignment and adjusting function order; integrating the complex number function optimized by the NEON instruction set into the target application for calling.

[0055] S250. Test and verify the target application to determine whether the complex function optimized by the NEON instruction set can improve performance and produce correct results.

[0056] In the embodiments of the present application, it can be understood that the present application optimizes complex functions based on the NEON instruction set. In specific applications, the process is processed by adding NEON support, writing NEON-optimized complex functions, debugging after writing the complex functions, optimizing performance, integrating into the application, as well as testing and verification. The present application utilizes NEON intrinsic functions to increase the speed of complex operations and reduce energy consumption. By introducing parallel operations, the corresponding parallel algorithms are designed and optimized to achieve efficient processing of complex tasks.

[0057] This application makes full use of the parallel computing power of modern computing resources, solves the bottleneck problem of traditional serial computing, and improves the performance and scalability of related technologies. It will bring new breakthroughs and progress to the development of related technologies. The advantage of parallel computing is that it processes multiple tasks at the same time, significantly improving computing efficiency. Compared with the traditional one-by-one processing method, through parallel computing, work can be assigned to multiple processing units to speed up the calculation speed. In addition, parallel computing can also make full use of hardware resources, reduce resource idle time, and improve the overall utilization of the system. This parallel computing method is not only suitable for processing large-scale data and improving data processing efficiency, but also can accelerate the execution of complex computing tasks, such as image processing, machine learning, and simulation.

[0058] In an example, the aforementioned ensuring data alignment and adjusting function order may specifically include: in the case where the NEON instruction set is a NEON multiplication instruction, the NEON multiplication instruction generates a waiting time of 2 clock signals CLK through operation, and the operation of the previous step in the irrelevant code is interspersed in the waiting time of the 2 clock signals CLK to maximize the use of all time.

[0059] In some embodiments, the aforementioned configuration of the hardware environment of the computer, that is, the aforementioned S120, may specifically include the following steps:

[0060] S310. Create a vivado project, complete the PS and PL configurations, and compile the configured project to export the file.

[0061] S320. In the Ubuntu virtual machine development environment, ensure that the Linux system kernel includes support for NEON and that the system files include NEON-supported libraries, and generate the image.ub file and BOOT.bin file.

[0062] S330, deploy the system image including hardware configuration and NEON function support to the Linux system of the board, and complete the deployment and transplantation of the Linux operating system of the board.

[0063] S340, use Linux to configure the board IP, upload the BOOT.bin file and image.ub file made according to the actual project to the corresponding partition of the board to complete the hardware preparation.

[0064] In the embodiments of the present application, it can be understood that vivado is an integrated design environment for FPGA, including a highly integrated design environment and a new generation of tools from system to IC level, all of which are based on a shared scalable data model and a universal debugging environment. The vivado tool combines various programmable technologies together and can expand the design of up to 100 million equivalent ASIC gates.

[0065] In some embodiments, in order to verify the actual effect of a complex number operation parallel acceleration method based on ARM_NEON provided in the embodiment of the present application, the execution efficiency and results of using NEON optimization and not using NEON optimization are compared; all test data of the same type are the same set of data, please refer to Figure 2 , the specific implementation steps are as follows:

[0066] Step 1: Create a vivado project, complete the PS and PL configurations, compile and export the configured project files for use in step 2;

[0067] Step 2: In the Ubuntu virtual machine development environment, ensure that the Linux system kernel includes support for NEON and that the system files include NEON-supported libraries, and generate image.ub and BOOT.bin files;

[0068] Step 3: Deploy the system image containing hardware configuration and NEON support in step 2 to the Linux system of the board to complete the deployment and transplantation of the Linux operating system of the board;

[0069] Step 4: Use Linux to configure the board IP, upload BOOT.bin and image.ub made according to the actual project to the corresponding partition of the board, and complete the hardware preparation;

[0070] Step 5: Open the Xilinx SDK compiler, select Linux as the OS Platform for the new project, and add the corresponding instructions in the compiler command options to enable the NEON instruction set. The specific menus and options may vary from version to version, but in general, similar options can be found in the project settings to set additional options for the compiler;

[0071] Step 6: Add the header file "arm_neon.h" and write the application. Since the present invention adopts 4 multiplication operations, each 4 data are stored once, so 4 data are operated in parallel. The specific data storage is as follows: Figure 4As shown, the complex parallel acceleration operation function is realized;

[0072] Step 7: Use FTP to upload the application (.elf file) compiled in the Xilinx SDK compiler and run it;

[0073] Step 8: Count and compare the running time of the application using complex number operations and the running time of the application using ARM-NEON-based complex number operation parallel acceleration;

[0074] From the above experiments, we can see that the efficiency of complex number operations is greatly improved by using the ARM-NEON parallel computing acceleration unit. The execution efficiency and result charts using NEON optimization and not using NEON optimization are as follows: Figure 5 As shown in the figure. When the amount of data is large, the float type acceleration efficiency is stable above 2.3. By using the complex number operation parallel acceleration method based on ARM-NEON, it is helpful to improve the operation efficiency of large batches of data in various fields such as digital signal processing and digital image processing.

[0075] This ARM_NEON-based parallel acceleration method for complex operations focuses on optimizing complex algorithms in applications such as digital signal processing (DSP). This method achieves efficient calculation of complex values ​​by utilizing the parallel characteristics of ARM_NEON technology, covering operations such as addition, subtraction, multiplication, and division. This parallel acceleration method greatly improves the efficiency and performance of complex operations, especially in resource-constrained environments such as embedded systems and mobile devices. Since there is no specific application scenario, the testing of this method is mainly focused on the algorithm itself rather than the specific application scenario. Therefore, the design and implementation of this method aims to meet the requirements of real-time performance and power consumption, providing an efficient and reliable foundation for possible complex signal processing algorithms in the future.

[0076] In some embodiments, the present application provides a complex number operation parallel acceleration system 400 based on ARM_NEON, such as Figure 6 As shown, the ARM_NEON-based complex number operation parallel acceleration system 400 may include the following modules:

[0077] An acquisition module 410 is used to acquire a computer configured with Xilinx SDK, where Xilinx SDK is an integrated development environment and is used to develop applications based on Xilinx FPGA;

[0078] A hardware configuration module 420 is used to configure the hardware environment of the computer, wherein the hardware environment includes an ARM processor that supports the NEON instruction set and sufficient memory to support NEON vector operations;

[0079] A software configuration module 430, for selecting a cross compiler and compiler options to configure the software environment of the computer;

[0080] The encapsulation and integration module 440 is used to abstractly encapsulate the NEON instruction set using the GCC tool chain, integrate the encapsulated NEON instruction set into the C / C++ code to implement an efficient parallel computing algorithm, and use a target library that supports the NEON instruction set for development.

[0081] According to an embodiment of the present application, any multiple modules among the acquisition module 410, the hardware configuration module 420, the software configuration module 430 and the encapsulation and integration module 440 can be combined into one module for implementation, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module.

[0082] In some embodiments, please refer to Figure 7 The aforementioned ARM_NEON-based complex number operation parallel acceleration system 400 may further include an optimization module 450, which is used to optimize the NEON inline assembly instructions through a preset debugging strategy, and specifically includes:

[0083] An instruction setting unit 451, used to set processor-specific compiler instructions to ensure that the project is configured correctly and supports the NEON instruction set;

[0084] The optimization acceleration unit 452 is used to write a complex function and optimize and accelerate the complex function using the NEON instruction set; the NEON instruction set supports complex operations by providing multiple vectorized instructions to process multiple data at the same time;

[0085] A verification and evaluation unit 453 is used to verify the correctness of the complex function using the debugging tool of the Xilinx SDK, and to evaluate the optimization effect of the NEON instruction set using the performance analysis tool;

[0086] An alignment adjustment unit 454 is used to ensure data alignment and adjust the function order; integrate the complex function optimized by the NEON instruction set into the target application for calling;

[0087] The test verification unit 455 is used to test and verify the target application to determine whether the complex function optimized by the NEON instruction set can improve performance and produce correct results.

[0088] In some embodiments, the alignment adjustment unit 454 can be specifically used for: when the NEON instruction set is a NEON multiplication instruction, the NEON multiplication instruction generates a waiting time of 2 clock signals CLK through operation, and the operation of the previous step in the irrelevant code is interspersed in the waiting time of the 2 clock signals CLK to maximize the use of all time.

[0089] In some embodiments, the aforementioned hardware configuration module 420 may be specifically used for:

[0090] Create a vivado project, complete the PS and PL configurations, and compile the configured project to export the files;

[0091] In the Ubuntu virtual machine development environment, ensure that the Linux system kernel includes support for NEON, and that the system files include NEON-supported libraries, and generate image.ub and BOOT.bin files;

[0092] Deploy the system image containing hardware configuration and NEON support to the board's Linux system to complete the board's Linux operating system deployment and transplantation;

[0093] Use Linux to configure the board IP, upload the BOOT.bin file and image.ub file made according to the actual project to the corresponding partition of the board to complete the hardware preparation.

[0094] Figure 7 Each module in the system shown has the function of implementing each step in the aforementioned ARM_NEON-based complex number operation parallel acceleration method and can achieve its corresponding technical effect. For the sake of concise description, it will not be repeated here.

[0095] In some embodiments, the present application provides an electronic device, the structure diagram of the electronic device is as follows Figure 8 shown.

[0096] The electronic device may include a processor 510 and a memory 520 storing computer program instructions.

[0097] Specifically, the processor 510 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0098] The memory 520 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 520 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 520 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 520 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 520 is a non-volatile solid-state memory.

[0099] The memory 520 may include a read-only memory (ROM), a random access memory (RAM), a disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Therefore, generally, the memory 520 includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer executable instructions, and when the software is executed (e.g., by one or more processors), it can perform the operations described in any one of the complex number operation parallel acceleration methods based on ARM_NEON in the above-mentioned embodiments.

[0100] The processor 510 implements any one of the ARM_NEON-based complex number operation parallel acceleration methods in the above-mentioned embodiments by reading and executing computer program instructions stored in the memory 520 .

[0101] In one example, the electronic device may further include a communication interface 530 and a bus 500. Figure 8 As shown, the processor 510, the memory 520, and the communication interface 530 are connected via a bus 500 and communicate with each other.

[0102] The communication interface 530 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0103] Bus 500 includes hardware, software or both, and the parts of online data flow billing equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 500 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.

[0104] In addition, in combination with the complex number operation parallel acceleration method based on ARM_NEON in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any one of the complex number operation parallel acceleration methods based on ARM_NEON in the above embodiment is implemented.

[0105] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0106] The functional blocks shown in the above block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0107] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0108] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0109] In summary, compared with the prior art, this application has the following beneficial effects:

[0110] 1. This application is based on the ARM_NEON architecture and achieves parallel acceleration in complex number operations, thereby significantly improving computing performance. By making full use of the parallel computing capabilities of ARM_NEON, multiple computing tasks can be processed simultaneously, greatly shortening the computing time.

[0111] 2. This application is oriented to ARM_NEON systems and has wide applicability. Its flexibility is reflected in its applicability to various ARM_NEON processors and can be applied to complex computing tasks in different fields, meeting diverse computing needs.

[0112] 3. This application adopts the SIMD approach, which greatly shortens the running time of complex operations, improves test efficiency, achieves efficient parallel acceleration, and strongly supports the efficient development and testing of related products.

[0113] 4. This application proposes a performance analysis method for complex operations and provides a corresponding test solution, which provides a reliable solution for complex operations in ARM_NEON systems. These methods help users gain a deeper understanding of system performance and guide system optimization and improvement.

[0114] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A complex number operation parallel acceleration method based on ARM_NEON, characterized in that: include: Obtain a computer configured with Xilinx SDK, wherein the Xilinx SDK is an integrated development environment and is used to develop applications based on Xilinx FPGA; Configuring the hardware environment of the computer, the hardware environment includes an ARM processor that supports the NEON instruction set and sufficient memory to support NEON vector operations; Select cross-compiler and compiler options to configure your computer's software environment; The NEON instruction set is abstractly encapsulated using the GCC tool chain, and the encapsulated NEON instruction set is integrated into the C / C++ code to implement an efficient parallel computing algorithm, and a target library supporting the NEON instruction set is used for development.

2. The complex number operation parallel acceleration method based on ARM_NEON as claimed in claim 1, characterized in that: The cross compiler supports the ARM architecture and the NEON instruction set, and the compiler option is used to enable the NEON instruction set support.

3. The complex number operation parallel acceleration method based on ARM_NEON as claimed in claim 1, characterized in that: The CPU processor of the computer configured with Xilinx SDK is ARM-Cortex-A9; the target library includes at least one of a NEON optimized math library, a multimedia processing library and an image processing library.

4. The ARM_NEON-based complex number operation parallel acceleration method according to any one of claims 1 to 3, characterized in that: Also includes: Optimize NEON's inline assembly instructions through preset debugging strategies.

5. The complex number operation parallel acceleration method based on ARM_NEON as claimed in claim 4, characterized in that: The optimization of the NEON inline assembly instructions by a preset debugging strategy includes: Set processor-specific compiler directives to ensure the project is configured correctly and supports the NEON instruction set; Writing a complex function, and optimizing and accelerating the complex function using the NEON instruction set; the NEON instruction set supports complex number operations by processing multiple data simultaneously by providing multiple vectorized instructions; Using the debugging tool of the Xilinx SDK to verify the correctness of the complex function, and using the performance analysis tool to evaluate the optimization effect of the NEON instruction set; Ensure data alignment and adjust function order; integrate the complex number functions optimized by the NEON instruction set into the target application for calling; The target application is tested and verified to determine whether the complex function optimized by the NEON instruction set can improve performance and produce correct results.

6. The complex number operation parallel acceleration method based on ARM_NEON as claimed in claim 5, characterized in that: The steps to ensure data alignment and adjust function order include: In the case where the NEON instruction set is a NEON multiplication instruction, the NEON multiplication instruction generates a waiting time of two clock signals CLK through operation, and the operation of the previous step in irrelevant code is interspersed in the waiting time of the two clock signals CLK to maximize the use of all time.

7. The complex number operation parallel acceleration method based on ARM_NEON as claimed in claim 1, characterized in that: The hardware environment of the computer is configured, including: Create a vivado project, complete the PS and PL configurations, and compile the configured project to export the files; In the Ubuntu virtual machine development environment, ensure that the Linux system kernel includes support for NEON, and that the system files include NEON-supported libraries, and generate image.ub and BOOT.bin files; Deploy the system image containing hardware configuration and NEON support to the board's Linux system to complete the board's Linux operating system deployment and transplantation; Use Linux to configure the board IP, upload the BOOT.bin file and the image.ub file made according to the actual project to the corresponding partition of the board to complete the hardware preparation.

8. A complex number operation parallel acceleration system based on ARM_NEON, characterized in that: include: An acquisition module is used to acquire a computer configured with Xilinx SDK, wherein the Xilinx SDK is an integrated development environment and is used to develop applications based on Xilinx FPGA; A hardware configuration module, used to configure the hardware environment of the computer, wherein the hardware environment includes an ARM processor that supports the NEON instruction set and sufficient memory to support NEON vector operations; A software configuration module for selecting a cross compiler and compiler options to configure a software environment of a computer; The encapsulation and integration module is used to abstractly encapsulate the NEON instruction set using the GCC tool chain, integrate the encapsulated NEON instruction set into the C / C++ code to implement an efficient parallel computing algorithm, and use a target library that supports the NEON instruction set for development.

9. An electronic device, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the ARM_NEON-based complex number operation parallel acceleration method as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores programs or instructions, and when the programs or instructions are executed by the processor, the ARM_NEON-based complex number operation parallel acceleration method as described in any one of claims 1 to 7 is implemented.

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