A dual-chip remote program upgrade system

Abstract

The present invention discloses a dual-chip remote program upgrade system, including: a host computer, a communication module and a controller system; it relates to the field of chip upgrade technology, and solves the technical problem that the existing technology has low reliability during the chip upgrade process; in the present invention, the host computer is used to select a program to be upgraded for upgrading a target DSP chip; a number of data frames decomposed by the host computer are transmitted to a functional DSP chip and an algorithm DSP chip; the algorithm DSP chip and the functional DSP chip both include an upgrade program and an application program. The present invention integrates the total number of data frames to be verified, the parity labels of the total number of data frames to be verified, and the numbered digital string into a verification feature value, calculates the verification feature value through a hash algorithm to obtain a second hash value, and compares the second hash value with the first hash value. The method can effectively identify the loss of data frames during transmission, thereby facilitating the improvement of the reliability of the dual-chip remote program upgrade.

Description

Technical Field

[0001] The invention belongs to the technical field of chip upgrade, and in particular is a dual-chip remote program upgrade system. Background Art

[0002] As refrigeration compressors, steam compressors, blowers and other downstream energy generation, petrochemical products develop in the direction of personalization, lightweight, high efficiency, energy saving, etc., under the global energy consumption reduction and national energy conservation and emission reduction policies, domestic high-speed motors are developing rapidly, and the corresponding controllers are also developing rapidly. With the continuous increase in motor frequency and controller speed, in order to provide enough space for algorithm chips, dual chips are used more and more widely. Therefore, the problem of remote upgrade of dual chips began to emerge.

[0003] The prior art selects the program to be upgraded in the host computer, processes the program to be upgraded, and sends it to the chip through the communication module. The chip parses the program to be upgraded and completes the program upgrade. However, when the dual chips are upgraded through the host computer, data is lost during the transmission process due to environmental interference, which makes the chip prone to functional abnormalities during the remote program upgrade, resulting in low reliability during the remote program upgrade of the chip.

[0004] The present invention provides a dual-chip remote program upgrade system to solve the above technical problems. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a dual-chip remote program upgrade system, which is used to solve the technical problem that when upgrading the dual-chip program in the prior art, the controller housing needs to be opened and the data cable needs to be connected for upgrading, which makes the chip upgrading process more cumbersome and leads to low efficiency in the chip upgrading process.

[0006] To achieve the above object, a first aspect of the present invention provides a dual-chip remote program upgrade system, comprising: a host computer, a communication module and a controller system;

[0007] The host computer is used to select a program to be upgraded for upgrading a target DSP chip; wherein the target DSP chip includes an algorithm DSP chip and a functional DSP chip;

[0008] The communication module is used for data transmission between the host computer and the controller system; a plurality of data frames decomposed by the host computer are transmitted to the functional DSP chip and the algorithm DSP chip;

[0009] The controller system includes an algorithm DSP chip, a functional DSP chip and an FPGA chip; the algorithm DSP chip is used for algorithm processing, and the functional DSP chip is used for acquisition and communication; the algorithm DSP chip and the functional DSP chip both include upgrade programs and application programs; the FPGA chip is used to process the interactive data between the algorithm DSP chip and the functional DSP chip.

[0010] Preferably, the program to be upgraded is a HEX file consisting of hexadecimal numbers.

[0011] Preferably, the selecting of the program to be upgraded for upgrading the target DSP chip includes:

[0012] When the target DSP chip enters the upgrade program, the host computer selects the program to be upgraded required for the target DSP chip to upgrade; the host computer decomposes the program to be upgraded into a number of data frames, generates a data transmission sequence based on the data frames, and sends the data transmission sequence to the corresponding target DSP chip;

[0013] The target DSP chip performs data verification on the data transmission sequence to obtain a verification result; wherein the verification result includes verification pass and verification fail;

[0014] Determine whether the verification result is passed; if yes, parse the data transmission sequence into a number of data frames, and solidify the data frames in the memory of the target DSP chip; if no, terminate the upgrade of the target DSP chip.

[0015] Preferably, the step of generating a data transmission sequence based on a plurality of data frames includes:

[0016] A1: extract several data frames, obtain the total number of data frames and mark it as n, and randomly set a corresponding unique number i for each data frame; where i = 1, 2, 3, ..., n, and n is a positive integer;

[0017] A2: Determine whether the total number of data frames n is an odd number; if yes, set the parity tag value to 1; if no, set the parity tag value to 0;

[0018] A3: Integrate the unique numbers corresponding to several data frames into a number sequence, and generate a number string according to the order of several numbers in the number sequence;

[0019] A4: Integrate the parity tag value, the total number of data frames n and the serial number string into an original feature value, and calculate the original feature value through a hash algorithm to obtain a first hash value;

[0020] A5: Integrate a plurality of data frames, a numbering sequence and a first hash value into a data transmission sequence.

[0021] Preferably, the target DSP chip performs data verification on the data transmission sequence, including:

[0022] B1: Obtain a number of data frames to be verified, a number sequence to be verified and a first hash value from a data transmission sequence;

[0023] B2: Obtain the total number of data frames to be checked and mark it as m, check the parity tag value corresponding to the total number of data frames, and generate a digital string of numbers to be checked according to the order of the numbers in the number sequence to be checked;

[0024] B3: Integrate the total number of data frames to be verified m, the parity tag value of the total number of data frames to be verified, and the digital string of the number to be verified into a verification feature value;

[0025] B4: Calculate the verification characteristic value by using a hash algorithm to obtain a second hash value;

[0026] B5: Determine whether the first hash value is equal to the second hash value; if yes, mark the verification result as passed; if no, mark the verification result as failed.

[0027] The present invention extracts the data frames to be checked, the numbering sequence to be checked and the first hash value in the data transmission sequence, and integrates the total number of data frames to be checked, the parity tags of the total number of data frames to be checked and the numbering digital string into a verification characteristic value, which can greatly improve the comprehensiveness and accuracy of the verification; the verification characteristic value is calculated by a hash algorithm to obtain a second hash value, and the second hash value is compared with the first hash value to efficiently verify the data integrity and transmission accuracy; this method can effectively identify the loss of data frames during the transmission process, ensure the transmission security of data frames, and thus help to improve the reliability and stability of dual-chip remote program upgrades.

[0028] Preferably, the functional DSP chip is upgraded by:

[0029] When the functional DSP chip needs a program upgrade, the target DSP chip is set as the functional DSP chip in the host computer, and the host computer sends a first flag to the functional DSP chip; the functional DSP chip transfers the application program to the upgrade program and waits for the upgrade.

[0030] Preferably, the algorithm DSP chip is upgraded by program, including:

[0031] When the algorithm DSP chip needs a program upgrade, the target DSP chip is set as the algorithm DSP chip in the host computer, and the host computer sends the second flag to the functional DSP chip; the functional DSP chip transmits the second flag to the algorithm DSP chip through the FPGA chip, and the algorithm DSP chip transfers the application program to the upgrade program and waits for upgrade.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention extracts the data frames to be checked, the numbering sequence to be checked and the first hash value in the data transmission sequence, and integrates the total number of data frames to be checked, the parity tags of the total number of data frames to be checked and the numbering digital string into a verification characteristic value, which can greatly improve the comprehensiveness and accuracy of the verification; the verification characteristic value is calculated by a hash algorithm to obtain a second hash value, and the second hash value is compared with the first hash value to efficiently verify the data integrity and transmission accuracy; this method can effectively identify the loss of data frames during the transmission process, ensure the transmission security of data frames, and thus help to improve the reliability and stability of dual-chip remote program upgrades. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of a dual-chip remote program upgrade system of the present invention;

[0036] Figure 2 It is a schematic diagram of the principle of the controller system in the present invention;

[0037] Figure 3 This is a flow chart of data verification performed by the target DSP chip of the present invention on the data transmission sequence.

[0038] In the figure, 101 is a host computer; 102 is a communication module; 103 is an algorithm DSP chip; 104 is an FPGA chip; 105 is a functional DSP chip. DETAILED DESCRIPTION

[0039] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] See also Figure 1-Figure 3 The first embodiment of the present invention provides a dual-chip remote program upgrade system, comprising:

[0041] like Figure 1 As shown, a dual-chip remote program upgrade system includes: a host computer, a communication module and a controller system;

[0042] The host computer (101) is used to select a program to be upgraded for upgrading a target DSP chip; wherein the target DSP chip includes an algorithm DSP chip and a functional DSP chip;

[0043] The communication module (102) is used for data transmission between the host computer and the controller system; a plurality of data frames decomposed by the host computer are transmitted to the functional DSP chip (105) and the algorithm DSP chip (103); the communication protocol used by the communication module (102) includes but is not limited to RS485\RS232\RS422;

[0044] The controller has two DPS chips, namely a functional DSP chip (105) and an algorithm DSP chip (103). The two are interconnected through FPGA (programmable logic chip) (104). In order to make the algorithm DSP chip focus on the algorithm function, the functional DSP chip is mainly used for communication, data recording and other functions, and the algorithm DSP chip mainly completes the control algorithm and other functions. The two work together; the algorithm DSP chip and the functional DSP chip both include upgrade programs and application programs.

[0045] In this embodiment, selecting a program to be upgraded for upgrading the target DSP chip includes:

[0046] When the target DSP chip enters the upgrade program, the host computer selects the program to be upgraded required for the target DSP chip to upgrade; the host computer decomposes the program to be upgraded into a number of data frames, generates a data transmission sequence based on the data frames, and sends the data transmission sequence to the corresponding target DSP chip;

[0047] The target DSP chip performs data verification on the data transmission sequence to obtain a verification result; wherein the verification result includes verification pass and verification fail;

[0048] Determine whether the verification result is passed; if yes, parse the data transmission sequence into a number of data frames, and solidify the data frames in the memory of the target DSP chip; if no, terminate the upgrade of the target DSP chip.

[0049] In this embodiment, a data transmission sequence is generated based on a number of data frames, including:

[0050] A1: extract several data frames, obtain the total number of data frames and mark it as n, and randomly set a corresponding unique number i for each data frame; where i = 1, 2, 3, ..., n, and n is a positive integer;

[0051] A2: Determine whether the total number of data frames n is an odd number; if yes, set the parity tag value to 1; if no, set the parity tag value to 0;

[0052] A3: Integrate the unique numbers corresponding to several data frames into a number sequence, and generate a number string according to the order of several numbers in the number sequence;

[0053] A4: Integrate the parity tag value, the total number of data frames n and the numbered digital string into an original eigenvalue, and calculate the original eigenvalue by a hash algorithm to obtain a first hash value; wherein the composition structure of the original eigenvalue is divided into a first data block, a second data block and a third data block, the first data block stores the parity tag value, the second data block stores the total number of data frames n, and the third data block stores the numbered digital string;

[0054] A5: Integrate a plurality of data frames, a numbering sequence and a first hash value into a data transmission sequence.

[0055] Exemplarily, the total number of data frames n is set to 10. Since the total number of data frames n is an even number, the parity tag value is set to 0. The numbering sequence is set to {6, 2, 3, 1, 10, 4, 9, 5, 7, 8}, and the numbering digital string is 62311049578.

[0056] The parity tag value, the total number of data frames n and the serial number string are integrated into the original eigenvalue 01062311049578;

[0057] The original feature value 01062311049578 is calculated by the hash algorithm, and the first hash value is 61f0c0fbe87930d50e82b239cca8c6d06808a00bf6d4f7620b3d20aa875235b5;

[0058] A plurality of data frames, a numbering sequence and a first hash value are integrated into a data transmission sequence.

[0059] In this embodiment, the target DSP chip performs data verification on the data transmission sequence, including:

[0060] B1: Obtain a number of data frames to be verified, a number sequence to be verified and a first hash value from a data transmission sequence;

[0061] B2: Obtain the total number of data frames to be checked and mark it as m, check the parity tag value corresponding to the total number of data frames, and generate a digital string of numbers to be checked according to the order of the numbers in the number sequence to be checked;

[0062] B3: Integrate the total number of data frames to be verified m, the parity tag value of the total number of data frames to be verified, and the digital string of the number to be verified into a verification feature value;

[0063] B4: Calculate the verification characteristic value by using a hash algorithm to obtain a second hash value;

[0064] B5: Determine whether the first hash value is equal to the second hash value; if yes, mark the verification result as passed; if no, mark the verification result as failed.

[0065] Exemplarily, the number sequence to be checked is set to {6, 2, 3, 1, 10, 4, 5, 7, 8}, the total number of data frames to be checked is m=9, and the parity tag value of the total number of data frames to be checked is 1;

[0066] The total number of data frames to be checked m, the parity tag value of the total number of data frames to be checked, and the number string to be checked are integrated into a check feature value of 196231104578;

[0067] The verification characteristic value is calculated by a hash algorithm, and the second hash value is 1f2000e0bb881243bdecd8381ceba0127bb5282b4b014f4cca4397cd4b4d7639;

[0068] Since the first Hash value is not equal to the second Hash value, the verification result is marked as verification failure.

[0069] The data verification method proposed in the present invention significantly enhances the comprehensiveness and accuracy of data verification by accurately extracting the data frames to be verified, the numbering sequence to be verified and the first hash value from the data transmission sequence, and innovatively combining the total number of data frames, their parity tag values ​​and the order of the numbering sequence to generate a unique verification characteristic value. This method not only simplifies the verification process and improves the verification efficiency, but also performs a secondary calculation on the integrated verification characteristic value through a hash algorithm to generate a second hash value, and compares it with the original first hash value, thereby realizing efficient verification of data integrity and transmission accuracy. This process can not only effectively identify and mark the possible tampering or loss of data during transmission, but also ensure the reliability and security of several data frames during transmission, which is conducive to improving the reliability and stability of the dual chip during remote program upgrades.

[0070] In this embodiment, the program of the functional DSP chip is upgraded, including:

[0071] When the functional DSP chip needs a program upgrade, the target DSP chip is set as the functional DSP chip in the host computer, and the host computer sends a first flag to the functional DSP chip; the functional DSP chip transfers the application program to the upgrade program and waits for the upgrade.

[0072] In this embodiment, the algorithm DSP chip is upgraded, including:

[0073] When the algorithm DSP chip needs a program upgrade, the target DSP chip is set as the algorithm DSP chip in the host computer, and the host computer sends the second flag to the functional DSP chip; the functional DSP chip transmits the second flag to the algorithm DSP chip through the FPGA chip, and the algorithm DSP chip transfers the application program to the upgrade program and waits for upgrade.

[0074] In this embodiment, when the functional DSP chip (105) receives the first flag bit, the functional DSP chip (105) enters the upgrade program; the host computer (101) adds the program to be upgraded required for the functional DSP chip (105) to upgrade, and decomposes the program to be upgraded into a plurality of data frames, and transmits the plurality of data frames to the functional DSP chip (105) through the communication module; the functional DSP chip performs data verification on the plurality of data frames; when the data verification passes, the data frames are sequentially solidified in the memory space of the functional DSP chip (105) until all the data frames are transmitted; when the data verification fails, the upgrade of the functional DSP chip (105) is terminated.

[0075] In this embodiment, when the functional DSP chip (105) receives the second flag bit, the second flag bit is transmitted to the algorithm DSP chip through the FPGA chip (104), and the algorithm DSP chip (103) enters the upgrade program; the host computer (101) adds the program to be upgraded required for upgrading the algorithm DSP chip (103), and decomposes the program to be upgraded into a plurality of data frames, and transmits the plurality of data frames to the algorithm DSP chip (103) through the communication module; the algorithm DSP chip performs data verification on the plurality of data frames; when the data verification passes, the data frames are sequentially solidified in the memory space of the algorithm DSP chip (103) until all the data frames are transmitted; when the data verification fails, the upgrade of the algorithm DSP chip (103) is terminated.

[0076] like Figure 2 As shown, in the controller system of this embodiment, the algorithm DSP chip and the functional DSP chip are connected to the communication module, the algorithm DSP chip and the functional DSP chip communicate data through the FPGA chip, and the algorithm DSP chip, the functional DSP chip and the FPGA chip are connected through a data bus.

[0077] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A dual-chip remote program upgrade system, comprising: Host computer, communication module and controller system; characterized in that, The host computer is used to select a program to be upgraded for upgrading a target DSP chip; wherein the target DSP chip includes an algorithm DSP chip and a functional DSP chip; The communication module is used for data transmission between the host computer and the controller system; a plurality of data frames decomposed by the host computer are transmitted to the functional DSP chip and the algorithm DSP chip; The controller system includes an algorithm DSP chip, a functional DSP chip and an FPGA chip; the algorithm DSP chip is used for algorithm processing, and the functional DSP chip is used for acquisition and communication; the algorithm DSP chip and the functional DSP chip both include upgrade programs and application programs; the FPGA chip is used to process the interactive data between the algorithm DSP chip and the functional DSP chip.

2. A dual-chip remote program upgrade system according to claim 1, characterized in that: The program to be upgraded is a HEX file composed of hexadecimal numbers.

3. A dual-chip remote program upgrade system according to claim 1, characterized in that: The step of selecting a program to be upgraded for upgrading the target DSP chip includes: When the target DSP chip enters the upgrade program, the host computer selects the program to be upgraded required for the target DSP chip to upgrade; the host computer decomposes the program to be upgraded into a number of data frames, generates a data transmission sequence based on the data frames, and sends the data transmission sequence to the corresponding target DSP chip; The target DSP chip performs data verification on the data transmission sequence to obtain a verification result; wherein the verification result includes verification pass and verification fail; Determine whether the verification result is passed; if yes, parse the data transmission sequence into a number of data frames, and solidify the data frames in the memory of the target DSP chip; if no, terminate the upgrade of the target DSP chip.

4. A dual-chip remote program upgrade system according to claim 3, characterized in that: The generating of a data transmission sequence based on a plurality of data frames comprises: A1: extract several data frames, obtain the total number of data frames and mark it as n, and randomly set a corresponding unique number i for each data frame; where i = 1, 2, 3, ..., n, and n is a positive integer; A2: Determine whether the total number of data frames n is an odd number; if yes, set the parity tag value to 1; if no, set the parity tag value to 0; A3: Integrate the unique numbers corresponding to several data frames into a number sequence, and generate a number string according to the order of several numbers in the number sequence; A4: Integrate the parity tag value, the total number of data frames n and the serial number string into an original feature value, and calculate the original feature value through a hash algorithm to obtain a first hash value; A5: Integrate a plurality of data frames, a numbering sequence and a first hash value into a data transmission sequence.

5. A dual-chip remote program upgrade system according to claim 3, characterized in that: The target DSP chip performs data verification on the data transmission sequence, including: B1: Obtain a number of data frames to be verified, a number sequence to be verified and a first hash value from a data transmission sequence; B2: Obtain the total number of data frames to be checked and mark it as m, check the parity tag value corresponding to the total number of data frames, and generate a digital string of numbers to be checked according to the order of the numbers in the number sequence to be checked; B3: Integrate the total number of data frames to be verified m, the parity tag value of the total number of data frames to be verified, and the digital string of the number to be verified into a verification feature value; B4: Calculate the verification characteristic value by using a hash algorithm to obtain a second hash value; B5: Determine whether the first hash value is equal to the second hash value; if yes, mark the verification result as passed; if no, mark the verification result as failed.

6. A dual-chip remote program upgrade system according to claim 1, characterized in that: Upgrade the functional DSP chip program, including: When the functional DSP chip needs a program upgrade, the target DSP chip is set as the functional DSP chip in the host computer, and the host computer sends a first flag to the functional DSP chip; the functional DSP chip transfers the application program to the upgrade program and waits for the upgrade.

7. A dual-chip remote program upgrade system according to claim 1, characterized in that: Upgrade the algorithm DSP chip program, including: When the algorithm DSP chip needs a program upgrade, the target DSP chip is set as the algorithm DSP chip in the host computer, and the host computer sends the second flag to the functional DSP chip; the functional DSP chip transmits the second flag to the algorithm DSP chip through the FPGA chip, and the algorithm DSP chip transfers the application program to the upgrade program and waits for upgrade.

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