Performing a decoding operation to simulate bits in an identified

Abstract

The application relates to performing a decoding operation to emulate a bit in an identified set of bits of a switching data block. A bit set of the data block associated with the unsuccessful first decoding operation may be identified. A second decoding operation to emulate switching of at least one bit in the group of bits may be performed. It may be determined that at least one bit of the group of bits switched during execution of the second decoding operation corresponds to an error. The error from the at least one bit in the group of bits may be corrected by changing a value of the at least one bit.

Description

[0001] Divisional application

[0002] This application is a divisional application of the invention patent application with the application date of February 20, 2019, application number 201980018989.X, and invention name “Performing decoding operations to simulate switching bits in an identified bit group of a data block”. Technical Field

[0003] The present disclosure relates generally to storage systems and, more particularly, to performing a decode operation to simulate switching bits on identified groups of bits of a block of data. Background Art

[0004] A storage system may include one or more memory components that store data. For example, a solid state drive (SSD) may include a memory device, such as a non-volatile memory device. The SSD may further include an SSD controller that can manage each of the memory devices and allocate data to be stored at the memory devices. A host system may utilize the SSD and request data from the SSD. The SSD controller may be used to retrieve data from the corresponding memory device and transfer the retrieved data back to the host system. Summary of the invention

[0005] According to one aspect of the present disclosure, a system is provided. The system includes: a memory device; and a processing device operably coupled to the memory device to: identify a bit group of a data block associated with an unsuccessful first decoding operation; perform a second decoding operation to simulate switching at least one bit in the bit group; determine whether the at least one bit in the bit group switched during the execution of the second decoding operation corresponds to an error; and in response to determining that the at least one bit in the bit group switched during the execution of the second decoding operation corresponds to the error, correct the error from the at least one bit in the bit group by changing the value of the at least one bit.

[0006] According to another aspect of the present disclosure, a method is provided. The method includes: identifying a bit group of a data block associated with an unsuccessful first decoding operation; performing a second decoding operation to simulate switching at least one bit in the bit group; determining, by a processing device, whether the at least one bit in the bit group switched during the execution of the second decoding operation corresponds to an error; and in response to determining that the at least one bit in the bit group switched during the execution of the second decoding operation corresponds to the error, correcting the error from the at least one bit in the bit group by changing the value of the at least one bit.

[0007] According to another aspect of the present disclosure, a system is provided. The system includes: a memory device; and a processing device operably coupled to the memory device to: identify a bit group of a data block associated with a failed decoding operation; calculate a difference value for at least one bit in the bit group; determine whether the difference value calculated for the at least one bit in the bit group corresponds to a correction capability of the failed decoding operation; and correct the at least one bit in the bit group by switching the value of the at least one bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present invention.

[0009] Figure 1 An example computing environment including a storage system according to some embodiments of the present invention is described.

[0010] Figure 2A An example of a data block of a storage system according to some embodiments of the present invention is illustrated.

[0011] Figure 2B An example of identifying groups of bits for a data block associated with an unsuccessful correction of errors according to some embodiments of the present invention is illustrated.

[0012] Figure 3 is a flow chart of an example method to perform a second decoding operation on an identified group of bits associated with an unsuccessful first decoding operation at an intersection of a row and a column of a block of data according to some embodiments of the invention.

[0013] Figure 4 is a flow chart of an example method to perform a second decoding operation that simulates toggling at least one bit in an identified group of bits, according to some embodiments of the invention.

[0014] Figure 5 is a flow chart of an example method to perform a decoding operation to determine whether a difference value of at least one bit in a bit group corresponds to a correction capability of a failed decoding operation according to some embodiments of the present invention.

[0015] Fig. 6A An example of identifying a first bit in a bit group of a data block for a second decoding operation according to some embodiments of the present invention is illustrated.

[0016] Figure 6B An example of identifying a second bit in a bit group of a data block for a second decoding operation according to some embodiments of the present invention is illustrated.

[0017] Figure 6C An example of correcting a second bit in a bit group of a data block through a second decoding operation according to some embodiments of the present invention is described.

[0018] Figure 7 is a block diagram of an example computer system in which embodiments of the invention may operate. DETAILED DESCRIPTION

[0019] Aspects of the present invention relate to performing a decode operation to simulate switching bits on an identified bit group of a block of data. In general, a host system may utilize a storage system that includes one or more memory devices. The host system may provide data to be stored at the storage system and may subsequently retrieve the data stored at the storage system. Data may be stored and retrieved from the memory devices within the storage system.

[0020] An example of a storage system is a solid state drive (SSD) that includes a non-volatile memory and a controller to manage the non-volatile memory. The controller may encode data into a format for storage at the storage system, and may subsequently decode the encoded data when retrieving the corresponding data from the storage system. This encoding and decoding operation may correspond to an error correction code (ECC) process for correcting errors when retrieving corresponding data that has been stored at the storage system. For example, the number of bits of the decoded data stored at the storage system and received by the controller may have been inadvertently changed (e.g., flipped due to noise, interference, distortion, or bit synchronization errors). Specifically, a bit that was originally stored at a value of '0' may have become a value of '1', or vice versa. The encoding and decoding operations of the ECC process can be used to identify whether a particular bit has been switched, and the value of the bit can then be changed when the corresponding data is returned.

[0021] As an example, a block-by-block product Bose-Chaudhuri-Hocquenghem (BWP-BCH) code may be used to encode data. In a BWP-BCH code, data blocks may be arranged into a two-dimensional array of rows and columns. Each row and column in the two-dimensional array may be encoded with an error correction code such as a binary BCH code. The intersection between a row and a column may be an entry of the array. Each entry of the array may include a set of data bits. The controller may then decode the encoded data into the original sequence of characters encoded on the storage system (hereinafter also referred to as a "codeword"). The codeword corresponding to the corrupted encoded data with errors stored on the storage system may be transmitted from the storage system to the controller during a decoding operation.

[0022] BWP codes can be decoded using an iterative process. For example, each row of the two-dimensional array can be decoded to produce a corresponding codeword. Then, each column of the two-dimensional array can be decoded to produce a corresponding codeword. The decoding of BWP-BCH can be performed using hard decoding, where the controller receives a binary channel output for each bit in the codeword.

[0023] The error correction code encoded in each row and column of the two-dimensional array can correct a number of errors in the corresponding row or column of the error correction code that is less than or equal to the correction capability of the error correction code. However, if the number of errors in the corresponding row or column is greater than the correction capability of the error correction code, the error correction code may not be able to correct the errors in the corresponding row or column, resulting in an unsuccessful error correction (hereinafter also referred to as an "unsuccessful decoding operation"). For example, if the error correction code has the ability to correct 4 errors and the rows and / or columns of the data block contain 4 errors, the error correction code can correct the 4 errors of the rows and / or columns. However, if the error correction code has the ability to correct 4 errors and the rows and / or columns of the array contain 5 errors, the error correction code may not be able to correct the errors of the rows and / or columns, resulting in an unsuccessful decoding operation. The correction capability of the error correction code is proportional to the data size of the error correction code. For example, an error correction code with the ability to correct 3 errors may have a smaller data size than an error correction code with the ability to correct 4 errors.

[0024] Aspects of the present invention solve the above and other disadvantages by performing subsequent decoding operations to simulate the bits of the identified bit groups of the switching data block. For example, a controller of a storage system may perform a first decoding operation on the identified data block. The first decoding operation may correct errors in rows and columns with a number of errors less than or equal to the correction capability of the first decoding operation. If any of the rows or columns of the data block contains more errors than the correction capability of the first decoding operation, decoding those rows or columns may result in unsuccessful correction of errors. Then, the controller may identify any bit groups of the data block that result in unsuccessful correction of errors. Unsuccessful error correction of any of the bit groups of the data block may trigger the initiation of a second decoding operation. The second decoding operation may have a correction capability that is at least one integer greater than the first decoding operation. For example, if the first decoding operation has a correction capability of 4, the second decoding operation may have a correction capability of 5. In some implementations, subsequent decoding operations may generate a list of possible codewords based on the error correction of the bit groups.

[0025] The second decoding operation can have a correction capability greater than the first decoding operation by simulating switching at least one bit in the bit group and determining whether the switched bit is an error. For example, if the bit group of the data block contains 10 bits, the second decoding operation can simulate switching at least one of the 10 bits to determine whether the switched bit is an error. In some embodiments, the second decoding operation can be iteratively performed on each bit in the bit group to identify errors in the bit group. For example, the second decoding operation can simulate switching the first bit in the bit group to determine whether the first bit is an error, then continue to simulate switching the second bit, then simulate switching the third bit, and so on. The second decoding operation can then correct the bits identified as errors by switching the values ​​of those specific bits from 0 to 1 or vice versa.

[0026] Thus, utilizing a second decoding operation may allow a greater number of errors to be corrected during decoding of a storage system by initiating the second decoding operation when a first decoding operation is associated with an unsuccessful error correction. The second decoding operation may also improve decoding accuracy, resulting in a higher probability of a successful decoding operation and reducing power usage and time dedicated to the decoding operation. In addition, the second decoding operation may allow a greater number of errors to be decoded without increasing the data size of the error correction code for each row and column of a data block encoded in the storage system, because the second decoding operation may utilize the same error correction code as the first decoding operation. Thus, the performance of the controller may be improved by allowing a greater number of errors to be corrected during data decoding without increasing the data size of the error correction code. Although the present invention describes correcting errors in an operation of decoding data stored on a storage system, aspects of the present invention may be applicable to any error correction example of a signal.

[0027] Figure 1 An example computing environment 100 is illustrated that includes a storage system 110. In general, the computing environment 100 can include a host system 120 that uses the storage system 110. The host system 120 can write data to the storage system 110 and read data from the storage system 110, for example.

[0028] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including a memory and a processing device. The host system 120 may include or be coupled to the storage system 110 so that the host system 120 can read data from the storage system 110 or write data to the storage system 110. For example, the host system 120 may be coupled to the storage system 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the storage system 110. When the storage system 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory devices 112A to 112N.

[0029] like Figure 1, the storage system 110 may include a controller 111 and memory devices 112A to 112N. In some embodiments, the memory devices 112A to 112N may be based on non-volatile memory. For example, the memory devices 112A to 112N may be "NAND" type flash memory. Each of the memory devices 112A to 112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC) or four-level cells (QLC)). In some embodiments, a particular memory device may include both SLC memory cells and MLC memory cells. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory devices (e.g., NAND type flash memory) are described, the memory devices 112A to 112N may be based on any other type of non-volatile memory or volatile memory. For example, memory devices 112A-112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetomechanical random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point non-volatile memory cell arrays. Memory devices 112A-112N may include any combination of different types of non-volatile memory or volatile memory. Furthermore, the memory cells of memory devices 112A-112N may be grouped into memory pages or data blocks, which may refer to a unit of a memory device for storing data.

[0030] The controller 111 may communicate with the memory devices 112A to 112N to perform operations, such as reading data, writing data, or erasing data at the memory devices 112A to 112N, and other such operations. In addition, the controller 111 may include hardware, such as one or more integrated circuits and / or discrete components, processing devices, buffer memory, software such as firmware or other instructions, or a combination thereof. In general, the controller 111 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 111 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory devices 112A to 112N. The controller 111 may further include a host interface circuit system that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory devices 112A- 112N, and also convert responses associated with the memory devices 112A- 112N into information for the host system 120 .

[0031] refer to Figure 1 , the controller 111 may include a decoder component 113 that can be used to decode data stored on the memory devices 112A to 112N using different types of decoding operations. For example, the decoder component 113 may perform a first decoding operation on the identified data block. The decoder component 113 may correct a first number of errors corresponding to the correction capability of the first decoding operation during the first decoding operation. For example, if the data block contains 4 errors and the correction capability of the first decoding operation is 4, then the decoder component 113 may correct 4 errors during the first decoding operation. The decoder component 113 may also identify a bit group in the data block that includes a second number of errors greater than the correction capability of the first decoding operation. For example, if the first decoding operation has the ability to correct 4 errors and the bit group of the data block contains 5 errors, then the decoder component 113 may identify the bit group as having a number of errors greater than the correction capability of the first decoding operation. Then, the decoder component 113 may perform a second decoding operation on the bit group. Additional details about the operation of the decoder component 113 are described below. Although aspects of the present invention describe that the second decoding operation is performed after the first decoding operation, in an implementation, any number of decoding operations may be performed. For example, a first decoding operation with a correction capability of 4 may be performed, followed by a second decoding operation with a correction capability of 5, followed by a third decoding operation with a correction capability of 6.

[0032] The storage system 110 may include additional circuitry or components not illustrated. For example, the storage system 110 may include a cache or buffer such as a DRAM and address circuitry such as a row decoder and a column decoder that may receive addresses from the controller 111 and decode the addresses to access the memory devices 112A to 112N.

[0033] Figure 2A An example of a data block 200 of a storage system is illustrated. In some embodiments, the data block 200 may be composed of Figure 1 The decoder component 113 decodes.

[0034] Data block 200 may represent user data stored on a storage system. Data block 200 may include user data (k) of a certain size that has been encoded and stored on the storage system. For example, the user data may have a data size of 6400 bits. Data block 200 may also include an error correction code (mt) also of a certain size, where m corresponds to the lower limit of the binary logarithm of n (e.g., the smallest integer greater than the binary logarithm of n). For example, the error correction code may have a data size of 600 bits. The error correction code may have a correction capability (t) indicating the number of errors that the error correction code can correct during the first decoding operation. As previously discussed, the data size of the error correction code may correspond to the correction capability of the error correction code. For example, an error correction code with a correction capability of t=4 may have a larger data size than an error correction code with a correction capability of t=3. Data block 200 may have a total block size (n), which is the sum of both the user data (k) and the error correction code (mt). For example, if the user data has a size of 6400 bits and the error correction code has a size of 600 bits, the data block 200 may have a total block size of 7000 bits.

[0035] Figure 2B An example of identifying a bit group of data block 250 associated with an unsuccessful correction of an error is illustrated. In some embodiments, the bit group may be represented by Figure 1 The decoder component 113 identifies.

[0036] Data block 250 may include user data (k) of data block 200. However, user data (k) may be encoded as an array of rows and columns (e.g. Figure 2B ), rather than being encoded as a single string of data bits (such as Figure 2A For example, if the user data has a data size of 6400 bits, the 6400 bits may be encoded into a data block 250 having 8 rows and 8 columns, each of which is 80 bits, as shown in FIG. Figure 2BAlthough data block 250 may be illustrated as having an equal number of rows and columns, in other implementations, data block 250 may contain various geometric sizes formed by different numbers of rows and columns.

[0037] Each row and column of data block 250 may be encoded with a corresponding error correction code (mt), as previously discussed. In addition, each row and column may be divided into Figure 2B . Using the previous example, a row consisting of 800 bits may be divided into 8 groups of bits, where each bit group includes 10 bits. The error correction code may have a correction capability (t) corresponding to the number of errors that the error correction code may be able to correct in a corresponding row or column of the error correction code during a decoding operation. For example, if the error correction code for a row has a correction capability of t=4, then the error correction code can correct up to 4 errors in that row.

[0038] During a decoding operation, the processing device may store a status bit 260 corresponding to whether that particular row or column has at least one bit group associated with an unsuccessful correction of an error. For example, if a row or column of data block 250 does not have any bit groups that result in an unsuccessful correction of an error, then the processing device may set the status bit 260 corresponding to that particular row or column to a read value of 1. Conversely, if a row or column of data block 250 has at least one bit group that results in an unsuccessful correction of an error, then the processing device may set the status bit 260 corresponding to that particular row or column to a read value of 0.

[0039] During a decoding operation, the processing device may iteratively decode the rows and columns of the data block 250. For example, the processing device may first decode all rows of the array, then decode all columns of the array, or vice versa. During a decoding operation, some bit groups may include a number of errors. In the present illustration, the data block 250 includes 3 bit groups that include a number of errors. One bit group includes 2 errors, one bit group includes 3 errors, and another bit group includes 5 errors. In the present illustration, the error correction code may have a correction capability of t=4. As each row of the data block 250 is decoded, the processing device may store a status bit as 1, which indicates that none of the bit groups in that row is associated with an unsuccessful decoding operation. During a decoding operation, the processing device may begin decoding the fifth row from the top of the array that includes a bit group that includes 2 errors, a bit group that includes 3 errors, and a bit group that includes 5 errors, resulting in a total number of errors for the row equal to 10. Because the total number of errors for the row is greater than the correction capability of the error correction code (e.g., t=4), the row may result in an unsuccessful correction of errors. Thus, the processing device may store the status bits for the row as 0, indicating that at least one of the groups of bits in the row resulted in an unsuccessful correction of an error.

[0040] After decoding of the rows of the array, the processing device may decode each of the columns of the array of data block 250. During the decoding operation, the processing device may decode the third column from the left side of the array that contains a bit group containing 2 errors. Because the total number of errors (e.g., 2) is less than the correction capability of the error correction code of the column (e.g., 4), the decoding operation may successfully correct 2 errors in the bit group. After successfully correcting the 2 errors in the bit group, the processing device may store the status bit of the column as 1, indicating that no bit group in the column will result in unsuccessful correction of errors. Similarly, when the processing device decodes the fourth column from the left side of the array, it may correct 3 errors in the bit group and store the status bit of the fourth column as a value of 1. However, the sixth column from the left side of the array contains 5 errors. Because the total number of errors (e.g., 5 bits) is greater than the correction capability of the error correction code of the column (e.g., 4), the bit group containing 5 errors may result in unsuccessful correction of errors. Therefore, the processing device may store the status bit of the sixth column as 0 to indicate unsuccessful correction of errors.

[0041] Figure 3 1 is a flow chart of an example method 300 for performing a second decoding operation on an identified bit group associated with an unsuccessful first decoding operation at an intersection of a row and a column of a data block according to an embodiment of the present invention. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The decoder component 113 executes.

[0042] Method 300 may begin with a processing device identifying a block of data represented by rows and columns (block 310). For example, the processing device may identify a two-dimensional array of data encoded on a storage system, such as in Figure 2BArray discussed. Then, the processing device may receive a status bit of the first decoding operation corresponding to each row and each column of the two-dimensional array of the data block (block 320). The status bit may correspond to whether the row and / or column is associated with an unsuccessful first decoding operation. For example, if the row is associated with an unsuccessful first decoding operation, the status bit may have a value of 0. However, if the row is associated with a successful first decoding operation, the status bit may have a value of 1. In some implementations, the row and / or column may be associated with an unsuccessful first decoding operation when the number of errors in a particular row and / or column is greater than the correction capability of the error correction code of that particular row and / or column. Then, the processing device may determine that at least one row and at least one column of the two-dimensional array are associated with an unsuccessful first decoding operation based on the status bit (block 330). For example, if the corresponding status bit of the row has a value of 0, the processing device may identify that the row is associated with an unsuccessful first decoding operation. Similarly, if the corresponding status bit of the column has a value of 0, the processing device may identify that the column is associated with an unsuccessful first decoding operation. In some implementations, each state bit may correspond to a syndrome value used in aspects of the present invention, where the state bit may indicate whether the syndrome is 0. For example, if a row has a state bit with a value of 1, then the syndrome value for that row may have a value of 0.

[0043] The processing device may then identify a group of bits in the data block at an intersection of a row and a column associated with an unsuccessful first decoding operation (block 340). Figure 2B , the processing device may identify a bit group containing 5 errors located at the intersection of a row having a state bit value of 0 and a column having a state bit value of 0. In some implementations, more than one bit group of the data block associated with the unsuccessful first decoding operation may be identified. In one implementation, the identified bit group may correspond to one row and multiple columns of the data block. In another implementation, the identified bit group may correspond to one column and multiple rows of the data block. Once the bit group has been identified, the processing device may perform a second decoding operation on the identified bit group (block 350). The second decoding operation may simulate toggling at least one bit in the bit group, as will be discussed in more detail below.

[0044] Figure 4 4 is a flow chart of an example method 400 for performing a second decoding operation of simulating switching of at least one bit in an identified bit group according to one embodiment of the present invention. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The decoder component 113 executes.

[0045] Method 400 may begin with a processing device identifying a group of bits in a data block that is associated with an unsuccessful first decoding operation (block 410). The group of bits may include a specific number of errors that caused the unsuccessful first decoding operation. For example, the identified group of bits may contain 5 errors and the error correction code may have a correction capability of 4. Next, the processing device may perform a second decoding operation to simulate switching at least one bit in the group of bits (block 420). In some implementations, the second decoding operation may iteratively simulate switching of bits from the group of bits. For example, if the group of bits contains 10 bits, then the second decoding operation may first simulate switching the value of the first bit and determining whether the first bit is an error. Next, the second decoding operation may switch the value of the second bit, followed by the value of the third bit, and so on. In some implementations, the second decoding operation may iteratively simulate switching the values ​​of individual bits until each error in the group of bits is identified. For example, if the group of bits contains 10 individual bits and 5 of the bits correspond to errors, then once 5 errors have been identified by the second decoding operation, the second decoding operation may not simulate any remaining bits. The second decoding operation may be able to correct a number of errors that is at least an integer greater than the first decoding operation. For example, if the first decoding operation has an error correction code with a correction capability of t=4, then the second decoding operation may be able to correct 5 errors (e.g., t+1). In one embodiment, the second decoding operation may be used after multiple decoding operations to increase the correction capability. For example, the second decoding operation may be used after decoding operation A with a correction capability of t=4 and decoding operation B with a correction capability of (t+1)=5. This may result in the second decoding operation having a correction capability of (t+2)=6. The second decoding operation may simulate switching bits (e.g., changing the value of a bit from '0' to '1', or vice versa) and determine that the switched bit is an error based on the output of the first decoding operation. The output of the first decoding operation may be determined using the following operations:

[0046] Input: S = [S0, S1, S2, ..., S 2t-1 ]

[0047] Initialization: Λ (0) (x) = 1, β (-1) (x) = x,

[0048] For r = 0, 2, ..., 2t-2, determine:

[0049]

[0050] Λ (r+2) (x) = Λ (r) (x)-Δ (r+2 ).β (r-1) (x)

[0051] If Δ(r+2) ≠0 and So:

[0052] *Set up beta (r-1) (x)←(Δ (r+2) ) -1 .x 2 Λ (r) (x)

[0053] *set up

[0054] otherwise

[0055] *Set up beta (r+1) (x)←x 2 β (r-1) (x)

[0056] *set up

[0057] Output: Λ(x), β(x), L Λ , L β

[0058] Where S corresponds to the syndrome, Λ corresponds to the error location polynomial, β corresponds to the correction polynomial, and L Λ and L β corresponds to the degree of the corresponding polynomial, and r corresponds to the number of iterations.

[0059] Using the output of the first decoding operation, the processing device may then simulate the value of at least one bit in the toggled bit group to determine whether the toggled bit corresponds to an error (block 430) using the following operation:

[0060] Input: Λ(x), β(x), L Λ , L β

[0061] Evaluate:

[0062] For i=0, 1, 2, ..., nt-2, execute:

[0063] initialization

[0064] For i=0, 1, 2, ..., nt-2, determine:

[0065]

[0066] If Δ j ≠∞, then set

[0067] if Then flip The index position in

[0068] where δ i corresponds to the set of positions with difference i, q corresponds to the field size, i corresponds to the bit position, and α corresponds to the primitive field element. i corresponds to the difference value of the specific bit on which the simulated switching operation is performed. i The processing device may identify that the particular bit corresponds to an error if the absolute value of is equal to an integer greater than the correction capability of the first decoding operation (e.g., t+1). For example, if the correction capability of the first decoding operation is 4 (e.g., t=4) and the particular bit has a value Δ equal to 5 (e.g., t+1). i , the processing device may identify that the particular bit corresponds to an error. After the particular bit has been identified as an error, the processing device may correct the error by changing the value of the particular bit (block 440). For example, if the particular bit corresponding to the error has a value of 0, the processing device may change the value to 1 when the data block containing the bit group is transferred back to the host system.

[0069] Figure 5 1 is a flow chart of an example method 500 for performing a decoding operation to determine whether a difference value of at least one bit in a bit group corresponds to a correction capability of a failed decoding operation according to some embodiments of the present invention. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The decoder component 113 executes.

[0070] Method 500 may begin with a processing device identifying a bit group of a data block associated with a failed decoding operation (block 510). In one embodiment, the data block may be represented by a two-dimensional array of rows and columns. In some embodiments, the processing device may determine that a particular row and a particular column are associated with a failed decoding operation and identify a bit group at the intersection of the particular row and the particular column. For example, referring back to Figure 2B, the processing device may identify a bit group containing 5 errors. In an embodiment, the bit group associated with the failed decoding operation may correspond to an identified bit group having a number of errors greater than the correction capability of the failed decoding operation. For example, if the correction capability of the failed decoding operation is 4 and the number of errors of the bit group is 5 (corresponding to 5 bits), then the bit group may be associated with the failed decoding operation. In another embodiment, the bit group may be identified based on the state bits of the rows and columns of the two-dimensional array, as previously discussed. Next, the processing device may calculate a difference value for at least one bit in the bit group (block 520). In one embodiment, the calculation of the difference value may be performed within a loop. In some embodiments, the processing device may iteratively determine the corresponding difference value for each bit in the bit group. Subsequently, the processing device may determine whether the difference value calculated for at least one bit in the bit group corresponds to the correction capability of the failed decoding operation (block 530). For example, if the correction capability of the failed decoding operation is 4 (e.g., t) and the difference value of a particular bit is 5 (e.g., t+1), then the difference value of the particular bit may correspond to the correction capability of the failed decoding operation. In some implementations, in response to determining that the difference value of the particular bit corresponds to a correction capability of the failed decoding operation, the processing device may correct the particular bit by switching the value of the particular bit from 0 to 1 (or vice versa). In some implementations, after correcting the particular bit in the group of bits, the processing device identifies a codeword associated with the corrected group of bits of the data block.

[0071] Fig. 6A 6 illustrates an example of the first bit in bit group 600 identifying a data block for a second decoding operation according to one embodiment of the present invention. In some embodiments, bit group 600 may be Figure 1 The decoder component 113 decodes.

[0072] Bit group 600 may include individual bits each having a corresponding binary value (e.g., 0 or 1). In this illustration, bit group 600 may include 10 individual bits. A second decoding operation may be performed on bit group 600, such as Figure 5 The second decoding operation may start with the first bit in the bit group 600. Then, the second decoding operation may determine whether the first bit corresponds to an error by simulating the switching of the first bit in the bit group 600. In this description, the second decoding operation may determine that the first bit in the bit group 600 does not correspond to an error.

[0073] Figure 6B 6 illustrates an example of a second bit in bit group 600 identifying a data block for a second decoding operation according to an embodiment of the present invention. In some embodiments, bit group 600 may be Figure 1 The decoder component 113 decodes.

[0074] As previously discussed, the second decoding operation may be an iterative operation. Thus, then, the second decoding operation may select the second bit in bit group 600. Then, the second decoding operation may determine whether the second bit corresponds to an error by simulating the switching of the second bit in bit group 600. In this illustration, the decoding operation may determine that the second bit in bit group 600 corresponds to an error.

[0075] Figure 6C 6. An example of correcting the second bit in the bit group 600 of the data block by the second decoding operation according to an embodiment of the present invention is illustrated. In some embodiments, the bit group 600 may be composed of Figure 1 The decoder component 113 decodes.

[0076] As previously discussed, the second decoding operation may identify that the second bit in the bit group 600 corresponds to an error. In response to identifying that the second bit corresponds to an error, the second decoding operation may change the value of the second bit from 1 to 0.

[0077] Figure 7 An example machine illustrating a computer system 700 may execute within the computer system 700 a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein. For example, the computer system 700 may correspond to a host system (e.g., Figure 1 A host system 120 that includes or utilizes a storage system (e.g., Figure 1 storage system 110) or can be used to perform operations of the controller (for example, to execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0078] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 718, which communicate with each other via bus 730. Processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or multiple processors that implement a combination of instruction sets. Processing device 702 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 to communicate over a network 720.

[0079] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software 726 embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside completely or at least partially within the main memory 704 and / or within the processing device 702 during execution by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Storage system 110.

[0080] In one embodiment, instructions 726 include implementing instructions corresponding to a decoder component (e.g., Figure 1 The functional instructions of the decoder component 113 of the present invention are stored in the machine-readable storage medium 724. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" should accordingly be understood to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0081] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, due to common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0082] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms that data into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0083] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present invention described herein.

[0085] The present invention may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0086] In the foregoing specification, embodiments of the invention have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the invention as set forth in the appended claims. The specification and drawings should accordingly be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory device; and a processing device operatively coupled to the memory device to perform operations comprising: a bit group identifying a segment of the memory device associated with a failed decode operation; calculating respective difference values ​​for the bit groups, each respective difference value corresponding to a respective bit in the bit group; determining whether any of the corresponding difference values ​​of the bit groups correspond to a correction capability of the failed decoding operation; and In response to determining that the subset of the corresponding difference values ​​corresponds to the correction capability of the failed decoding operation, correcting the at least one bit in the group of bits corresponding to the subset of the corresponding difference values ​​by changing a value of at least one bit in the group of bits.

2. The system of claim 1, wherein the correction capability corresponds to a number of errors corrected by the failed decoding operation.

3. The system of claim 1, wherein the operations performed by the processing device further comprise: A value of the at least one bit in the group of bits is simulated to be changed, wherein a corresponding difference value of the at least one bit in the group of bits is calculated after the value of the at least one bit in the group of bits is simulated to be changed.

4. The system of claim 1, wherein calculating the corresponding difference values ​​for the bit groups is based on outputs of the failed decoding operations.

5. The system of claim 1, wherein the failed decoding operation corresponds to the bit group including a number of errors greater than the correction capability of the failed decoding operation.

6. The system of claim 1, wherein the segments of the memory device are represented by a plurality of rows and a plurality of columns in an array of the memory device.

7. The system of claim 6, wherein to identify the bit group of the segment of the memory device associated with the failed decode operation, the operations performed by the processing device further comprise: determining that at least one of the plurality of rows is associated with the failed decoding operation; and It is determined that at least one column of the plurality of columns is associated with the failed decoding operation.

8. The system of claim 6, wherein to identify the bit group of the segment of the memory device associated with the failed decode operation, the operations performed by the processing device further comprise: determining that a first state bit of a corresponding row of the plurality of rows is associated with the failed decoding operation; and determining that a second state bit of a corresponding column of the plurality of columns is associated with the failed decode operation, wherein the group of bits identifying the segment of the memory device associated with the failed decode operation is based on determining that the first state bit of the corresponding row and the second state bit of the corresponding column are associated with the failed decode operation.

9. A method comprising: a bit group identifying a segment of a memory device associated with a failed decode operation; calculating respective difference values ​​for the bit groups, each respective difference value corresponding to a respective bit in the bit group; determining whether any of the corresponding difference values ​​of the bit groups correspond to a correction capability of the failed decoding operation; and In response to determining that the subset of the corresponding difference values ​​corresponds to the correction capability of the failed decoding operation, correcting the at least one bit in the group of bits corresponding to the subset of the corresponding difference values ​​by changing a value of at least one bit in the group of bits.

10. The method of claim 9, wherein the correction capability corresponds to a number of errors corrected by the failed decoding operation.

11. The method according to claim 9, further comprising: A value of the at least one bit in the group of bits is simulated to be changed, wherein a corresponding difference value of the at least one bit in the group of bits is calculated after the value of the at least one bit in the group of bits is simulated to be changed.

12. The method of claim 9, wherein calculating the corresponding difference values ​​for the groups of bits is based on outputs of the failed decoding operations.

13. The method of claim 9, wherein the failed decoding operation corresponds to the bit group including a number of errors that is greater than the correction capability of the failed decoding operation.

14. The method of claim 9, wherein the segments of the memory device are represented by a plurality of rows and a plurality of columns in an array of the memory device.

15. The method of claim 14, wherein to identify the bit group of the segment of the memory device associated with the failed decode operation, the operations performed by the processing device further comprise: determining that at least one of the plurality of rows is associated with the failed decoding operation; and It is determined that at least one column of the plurality of columns is associated with the failed decoding operation.

16. The method of claim 14, wherein to identify the bit group of the segment of the memory device associated with the failed decode operation, the operations performed by the processing device further comprise: determining that a first state bit of a corresponding row of the plurality of rows is associated with the failed decoding operation; and determining that a second state bit of a corresponding column of the plurality of columns is associated with the failed decode operation, wherein the group of bits identifying the segment of the memory device associated with the failed decode operation is based on determining that the first state bit of the corresponding row and the second state bit of the corresponding column are associated with the failed decode operation.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: a bit group identifying a segment of the memory device associated with a failed decode operation; calculating respective difference values ​​for the bit groups, each respective difference value corresponding to a respective bit in the bit group; determining whether any of the corresponding difference values ​​of the bit groups correspond to a correction capability of the failed decoding operation; and In response to determining that the subset of the corresponding difference values ​​corresponds to the correction capability of the failed decoding operation, correcting the at least one bit in the group of bits corresponding to the subset of the corresponding difference values ​​by changing a value of at least one bit in the group of bits.

18. The non-transitory computer-readable storage medium of claim 17, wherein the correction capability corresponds to a number of errors corrected by the failed decoding operation.

19. The non-transitory computer-readable storage medium of claim 17, wherein the operations that the instructions cause the processing device to perform further include: A value of the at least one bit in the group of bits is simulated to be changed, wherein a corresponding difference value of the at least one bit in the group of bits is calculated after the value of the at least one bit in the group of bits is simulated to be changed.

20. The non-transitory computer-readable storage medium of claim 17, wherein calculating the respective difference values ​​for the groups of bits is based on an output of the failed decoding operation.

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