Functional safety control system for high-frequency pipeline computing circuits

Abstract

This invention discloses a functional safety control system for high-frequency pipelined computing circuits. With the aim of reducing the cost of implementing functional safety, it proposes a functional safety scheme for transient faults and a functional safety scheme for permanent faults. It uses an algorithm node register parity check network to cover transient faults and an algorithm node signature network to cover permanent faults. By combining the two functional safety schemes, the functional safety goal can be achieved while reducing resource costs.

Description

Technical Field

[0001] The invention relates to a high-frequency pipeline computing circuit, and in particular to a functional safety control system for the high-frequency pipeline computing circuit. Background Art

[0002] The 2D constant false alarm rate (CFAR) circuit is as follows Figure 1 As shown, the circuit characteristics are as follows:

[0003] 1) The circuit is mainly based on multi-bit multiplication and addition operations, and the logic resources are large

[0004] 2) The high-frequency circuit has more pipeline stages, resulting in more registers and a higher transient fault basic failure rate;

[0005] 3) The circuit has a large entropy reduction feature, that is, the amount of original calculation data is large, but the resulting output data is small.

[0006] Difficulties of existing 2D CFAR circuit functional safety solutions:

[0007] 1) Since there are many registers and they are scattered in various levels of pipelines, the register data is updated quickly, and transient faults are difficult to cover;

[0008] 2) Due to the large entropy reduction characteristics of the computing circuit, permanent faults are difficult to cover;

[0009] Therefore, existing functional safety solutions generally adopt overall redundancy or lock-step (for automotive safety level ASILD) or 0.9 logic resource redundancy or lock-step (for automotive safety level ASILB), but this will cause the original circuit resources to increase by 0.9-1.2 times, which is very costly. Summary of the invention

[0010] The technical problem to be solved by the present invention is to provide a functional safety control system for a high-frequency pipeline computing circuit, which can achieve functional safety goals and reduce resource costs.

[0011] In order to solve the above technical problems, the present invention provides a functional safety control system for a high-frequency pipeline computing circuit, which includes an algorithm node signature network and an algorithm node register parity check network;

[0012] The algorithm node signature network is used to detect permanent faults in high-frequency pipeline computing circuits;

[0013] The algorithm node register parity check network is used to detect instantaneous faults in high-frequency pipeline computing circuits.

[0014] Preferably, the high-frequency pipeline computing circuit is a radar target detection and recognition circuit, an image recognition circuit or an artificial intelligence learning and training circuit.

[0015] Preferably, the algorithm node signature network includes a signature hardware algorithm module and a software program module;

[0016] The signature hardware algorithm module includes multiple algorithm node circuits, multiple signature circuits and a final signature circuit;

[0017] Each algorithm node is connected in a circuit tree;

[0018] Each algorithm node circuit is connected to a signature circuit;

[0019] The signature circuits are connected to the respective algorithm node circuits and are connected to the final signature circuits respectively;

[0020] The signature circuit can perform feature value extraction;

[0021] If a permanent fault exists in an algorithm node circuit, the signature circuit corresponding to the algorithm node circuit can extract the characteristic value of the permanent fault of the algorithm node circuit and output the signature result to the final signature circuit;

[0022] The software program module is used to form a set of test patterns and store the final signature results of the set of test patterns;

[0023] The software program module forms a software test pattern which is output to the signature hardware algorithm module, and the software test pattern can cover all algorithm node circuits in the signature hardware algorithm module;

[0024] The software program module is used to compare the signature result summarized by the final signature circuit with the final signature result of a stored set of test patterns, and output the permanent fault detection result of the high-frequency pipeline computing circuit.

[0025] Preferably, the signature circuit is a CRC circuit.

[0026] Preferably, the algorithm node circuit is an algorithm branch circuit of a 2D CFAR part in a millimeter wave radar.

[0027] Better,

[0028] The algorithm node register parity check network includes a register hardware algorithm module and a software program module;

[0029] The register hardware algorithm module includes a plurality of algorithm node circuits, a plurality of parity check circuits and a final parity check circuit;

[0030] Each algorithm node is connected in a circuit tree;

[0031] Each algorithm node circuit is connected to a parity check circuit;

[0032] A parity check circuit correspondingly connected to each algorithm node circuit and respectively connected to the final parity check circuit;

[0033] The algorithm node circuit is provided with an internal register group;

[0034] When the internal register group of an algorithm node circuit is updated, the parity check circuit corresponding to the algorithm node circuit calculates the parity check value of the data of the internal register group of the algorithm node circuit as the current parity check value of the algorithm node circuit; in each subsequent cycle, the parity check value of the data of the internal register group of the algorithm node circuit is calculated and the subsequent parity check value is updated, and the subsequent parity check value is compared with the current parity check value. If the algorithm node circuit has a transient fault causing the subsequent parity check value to flip, the comparison between the subsequent parity check value and the current parity check value will fail, and the parity check circuit corresponding to the algorithm node circuit outputs the transient fault signal of the algorithm node circuit to the final parity check circuit;

[0035] The final parity check circuit obtains the instantaneous fault detection result of the entire register hardware algorithm module according to the algorithm node circuit instantaneous fault signal sent by each parity check circuit;

[0036] The software program module is used to form a set of software test patterns and output them to the root algorithm node circuits in the register hardware algorithm module. The set of software test patterns is required to cover all algorithm node circuits in the register hardware algorithm module.

[0037] The functional safety control system for high-frequency pipeline computing circuits of the present invention aims to reduce the cost of implementing functional safety, and proposes a functional safety solution for transient faults and permanent faults respectively; an algorithm node register parity network is used to cover transient faults, and an algorithm node signature network is used to cover permanent faults. By combining the two functional safety solutions, both the functional safety goal can be achieved and the resource cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 It is the 2D CFAR partial algorithm circuit;

[0040] Figure 2 This is a schematic diagram of an algorithm node signature network of an embodiment of a functional safety control system for a high-frequency pipeline computing circuit of the present invention:

[0041] Figure 3 This is a schematic diagram of register parity check of a single-node algorithm node circuit of an embodiment of a functional safety control system for a high-frequency pipeline computing circuit of the present invention:

[0042] Figure 4 It is a schematic diagram of an algorithm node register parity check network of an embodiment of a functional safety control system for a high-frequency pipeline computing circuit of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] Embodiment 1

[0045] A functional safety control system for a high-frequency pipeline computing circuit, comprising an algorithm node signature network and an algorithm node register parity check network;

[0046] The algorithm node signature network is used to detect permanent faults in high-frequency pipeline computing circuits;

[0047] The algorithm node register parity check network is used to detect transient faults of high-frequency pipeline computing circuits.

[0048] Preferably, the high-frequency pipeline computing circuit is a radar target detection and recognition circuit, an image recognition circuit or an artificial intelligence learning and training circuit.

[0049] The functional safety control system for high-frequency pipeline computing circuits of the present invention aims to reduce the cost of implementing functional safety, and proposes a functional safety solution for transient faults and permanent faults respectively; an algorithm node register parity network is used to cover transient faults, and an algorithm node signature network is used to cover permanent faults. By combining the two functional safety solutions, both the functional safety goal can be achieved and the resource cost can be reduced.

[0050] Embodiment 2

[0051] Based on the functional safety control system for high-frequency pipeline computing circuits of the first embodiment, Figure 2 As shown, the algorithm node signature network includes a signature hardware algorithm module and a software program module;

[0052] The signature hardware algorithm module includes multiple algorithm node circuits, multiple signature circuits and a final signature circuit;

[0053] Each algorithm node is connected in a circuit tree;

[0054] Each algorithm node circuit is connected to a signature circuit;

[0055] The signature circuits are connected to the respective algorithm node circuits and are connected to the final signature circuits respectively;

[0056] The signature circuit can perform feature value extraction;

[0057] If a permanent fault exists in an algorithm node circuit, the signature circuit corresponding to the algorithm node circuit can extract the characteristic value of the permanent fault of the algorithm node circuit and output the signature result to the final signature circuit;

[0058] The software program module is used to form a set of test patterns (vectors) and store a set of final signature results of the test patterns;

[0059] The software program module forms a software test pattern which is output to the root algorithm node circuit of the signature hardware algorithm module, and the software test pattern can cover all algorithm node circuits in the signature hardware algorithm module;

[0060] The software program module is used to compare the signature result summarized by the final signature circuit with the final signature result of a set of stored test patterns, and output the permanent fault detection result of the high-frequency pipeline computing circuit.

[0061] Preferably, the signature circuit is a CRC (Cyclic Redundancy Check) circuit or other circuits capable of extracting characteristic values.

[0062] Preferably, the algorithm node circuit is an algorithm branch circuit of a 2D CFAR (Constant False Alarm Rate) part in a millimeter wave radar.

[0063] The functional safety control system for high-frequency pipeline computing circuits of the second embodiment uses a combination of software and hardware to detect permanent faults. Its software program module provides a software program guidance circuit test window and a test pattern (vector, graph), which is required to cover all algorithm node paths; its signature hardware algorithm module implements a hardware signature circuit for each algorithm node, and integrates and summarizes the signature circuit network composed of each algorithm node for output.

[0064] In the functional safety control method for a high-frequency pipeline computing circuit of the second embodiment, when detecting a permanent fault, the software program module forms a set of test patterns and stores the final signature results of the set of test patterns. Then the software program of the software program module starts to run the test pattern. If there is a permanent fault in any algorithm node circuit in the signature hardware algorithm module at this time, the signature circuit corresponding to any algorithm node circuit will output an erroneous signature result. This erroneous signature result is converged to the final signature circuit through the algorithm node signature network, resulting in an erroneous final signature result. The software program module compares the final test signature result summarized by the final signature circuit with the final signature results of a stored set of test patterns, and finds inconsistency, thereby detecting a permanent fault and outputting a permanent fault detection result of the high-frequency pipeline computing circuit.

[0065] The functional safety control system for high-frequency pipeline computing circuits of embodiment 2 generally does not have complex control and jump functions, and the test pattern (vector) is easier to achieve for the circuit path. The test pattern (vector) can be developed according to different ASIL indicators, and the coverage rate can reach 90%-99%.

[0066] Embodiment 3

[0067] Based on the functional safety control system for high-frequency pipeline computing circuits of the first embodiment, Figure 4 The algorithm node register parity check (parity) network shown includes a register hardware algorithm module and a software program module;

[0068] The register hardware algorithm module includes a plurality of algorithm node circuits, a plurality of parity check circuits and a final parity check circuit;

[0069] Each algorithm node is connected in a circuit tree;

[0070] Each algorithm node circuit is connected to a parity circuit;

[0071] A parity check circuit correspondingly connected to each of the algorithm node circuits and respectively connected to the final parity check circuit;

[0072] The algorithm node circuit is provided with an internal register group;

[0073] like Figure 3 As shown, when the internal register group of an algorithm node circuit is updated, the parity check circuit corresponding to the algorithm node circuit calculates the parity check value of the data of the internal register group of the algorithm node circuit as the current parity check value (Pre parity reg) of the algorithm node circuit; in each subsequent cycle, the parity check value of the data of the internal register group of the algorithm node circuit is calculated and the subsequent parity check value is updated, and the subsequent parity check value is compared with the current parity check value. If the algorithm node circuit has an instantaneous fault causing the subsequent parity check value to flip, the comparison between the subsequent parity check value and the current parity check value will fail, and the parity check circuit corresponding to the algorithm node circuit outputs the instantaneous fault signal of the algorithm node circuit to the final parity check circuit;

[0074] The final parity check circuit obtains the instantaneous fault detection result of the entire register hardware algorithm module according to the algorithm node circuit instantaneous fault signal sent by each parity check circuit.

[0075] The software program module is used to form a set of software test patterns and output them to the root algorithm node circuits in the register hardware algorithm module. The set of software test patterns is required to cover all algorithm node circuits in the register hardware algorithm module.

[0076] Preferably, the high-frequency pipeline calculation circuit is an algorithm branch circuit of a 2D CFAR (Constant False Alarm Rate) part in a millimeter wave radar.

[0077] In the functional safety control system for high-frequency pipeline computing circuits of the third embodiment, when a transient fault is detected, when a register group inside an algorithm node circuit is updated, the parity value of the register group data is calculated and used as the current parity value (Pre parity reg) of the algorithm node circuit, and the parity value of the register group is calculated in each subsequent cycle and the subsequent parity value (Postparity reg) is updated, and the current parity value (Pre parity reg) is compared with the subsequent parity value (Post parity reg). If a transient fault occurs in any algorithm node circuit, resulting in a value flip, the comparison result between the current parity value (Pre parity reg) and the subsequent parity value (Post parity reg) will fail, thereby identifying the transient fault of a single algorithm node circuit, and integrating the parity (parityparity) results of all algorithm node circuits to obtain the transient fault detection result of the entire register hardware algorithm module.

[0078] In the functional safety control system for high-frequency pipeline computing circuits of Example 3, the algorithm node register parity network cannot cover the situation where a transient fault occurs when the internal register group update of the algorithm node circuit is in the setup window. Except for this situation, in theory, the algorithm node register parity network can identify every change in the register, and the coverage rate can reach more than 90%. Whether it can reach 99% depends on the proportion of the setup window time and the data update frequency.

[0079] Embodiment 4

[0080] Based on the functional safety control system for high-frequency pipeline computing circuits of embodiments 1 to 3, a 2D CFAR circuit is used to implement the algorithm node signature network and the algorithm node register parity network as an example. The circuit has a working clock of 500M, assuming that a cycle can only implement 64-72bit addition and 32bit multiplication at most.

[0081] Some circuit resource assumptions are shown in Table 1.

[0082] Table 1

[0083] Type CRC128 Addition / bit 32-bit multiplication Register / bit Parity / bit Gate count 3000 5 5000 10 8

[0084] by Figure 1 The algorithm structure statistics and original algorithm circuit logic resources are shown in Table 1.

[0085] Table 2

[0086]

[0087] Because data feature values ​​will not be lost when data is accumulated without intervention, only the data at the last level is selected to add CRC signature in the multi-level accumulation PIPE, so the number of added CRC nodes can be reduced;

[0088] According to the statistical results in Table 2, the functional safety cost of this solution is:

[0089] (18000+9138) / 87935=30.8%

[0090] The comparison of functional safety goals and costs is shown in Table 3.

[0091] Table 3

[0092] ASIL Targets Traditional solution cost The cost of this solution ASIL B 90％-100％ 30.8％ ASIL D 100％-120％ Theoretically less than 50%, but the conditions are harsh

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A functional safety control system for a high-frequency pipeline computing circuit, characterized in that: Including algorithm node signature network and algorithm node register parity check network; The algorithm node signature network is used to detect permanent faults in high-frequency pipeline computing circuits; The algorithm node register parity check network is used to detect instantaneous faults in high-frequency pipeline computing circuits.

2. The functional safety control system for high-frequency pipeline computing circuit according to claim 1, characterized in that: The high-frequency pipeline computing circuit is a radar target detection and recognition circuit, an image recognition circuit or an artificial intelligence learning and training circuit.

3. The functional safety control system for high-frequency pipeline computing circuit according to claim 1, characterized in that: The algorithm node signature network includes a signature hardware algorithm module and a software program module; The signature hardware algorithm module includes multiple algorithm node circuits, multiple signature circuits and a final signature circuit; Each algorithm node is connected in a circuit tree; Each algorithm node circuit is connected to a signature circuit; The signature circuits correspondingly connected to the respective algorithm node circuits are respectively connected to the final signature circuit; The signature circuit can perform feature value extraction; If a permanent fault exists in an algorithm node circuit, the signature circuit corresponding to the algorithm node circuit can extract the characteristic value of the permanent fault of the algorithm node circuit and output the signature result to the final signature circuit; The software program module is used to form a set of test patterns and store the final signature results of the set of test patterns; The software program module forms a software test pattern which is output to the signature hardware algorithm module, and the software test pattern can cover all algorithm node circuits in the signature hardware algorithm module; The software program module is used to compare the signature result summarized by the final signature circuit with the final signature result of a stored set of test patterns, and output the permanent fault detection result of the high-frequency pipeline computing circuit.

4. The functional safety control system for high-frequency pipeline computing circuit according to claim 3, characterized in that: The signature circuit is a CRC circuit.

5. The functional safety control system for high-frequency pipeline computing circuit according to claim 3, characterized in that: The algorithm node circuit is an algorithm branch circuit of the 2D CFAR part in the millimeter wave radar.

6. The functional safety control system for high-frequency pipeline computing circuit according to claim 1, characterized in that: The algorithm node register parity check network includes a register hardware algorithm module and a software program module; The register hardware algorithm module includes a plurality of algorithm node circuits, a plurality of parity check circuits and a final parity check circuit; Each algorithm node is connected in a circuit tree; Each algorithm node circuit is connected to a parity check circuit; A parity check circuit correspondingly connected to each algorithm node circuit and respectively connected to the final parity check circuit; The algorithm node circuit is provided with an internal register group; When the internal register group of an algorithm node circuit is updated, the parity check circuit corresponding to the algorithm node circuit calculates the parity check value of the data of the internal register group of the algorithm node circuit as the current parity check value of the algorithm node circuit; in each subsequent cycle, the parity check value of the data of the internal register group of the algorithm node circuit is calculated and the subsequent parity check value is updated, and the subsequent parity check value is compared with the current parity check value. If the algorithm node circuit has a transient fault causing the subsequent parity check value to flip, the comparison between the subsequent parity check value and the current parity check value will fail, and the parity check circuit corresponding to the algorithm node circuit outputs the transient fault signal of the algorithm node circuit to the final parity check circuit; The final parity check circuit obtains the instantaneous fault detection result of the entire register hardware algorithm module according to the algorithm node circuit instantaneous fault signal sent by each parity check circuit; The software program module is used to form a set of software test patterns and output them to the root algorithm node circuits in the register hardware algorithm module. The set of software test patterns is required to cover all algorithm node circuits in the register hardware algorithm module.

7. The functional safety control system for high-frequency pipeline computing circuit according to claim 6, characterized in that: The algorithm node circuit is an algorithm branch circuit of the 2D CFAR part in the millimeter wave radar.

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