448 results about "Pipeline (computing)" patented technology

A federated distributed AI reasoning and action platform utilizing decentralized, partially observable hierarchical computing for neuro-symbolic reasoning. It features a federated Distributed Computational Graph (DCG) system integrating core components like pipeline orchestration, transformers, and marketplaces. The platform enables privacy-preserving dynamic resource allocation, intelligent task scheduling, and variable information sharing across diverse computing environments. By coordinating with an AI-based operating system and analyzing performance metrics, environmental conditions, and resource availability, the system optimizes efficiency across AI workloads and decision-making processes. This results in an adaptive, power-efficient, and scalable AI-enabled data processing system capable of handling complex tasks while maintaining peak performance under various operating conditions.

The invention discloses a low-power-consumption single-emission out-of-order execution RISC-V processor, which comprises seven stages of pipeline architecture, namely an instruction fetch unit, an instruction buffer unit, a decoding unit, an emission unit for single instruction emission, a physical register file, an execution unit for parallel out-of-order calculation and a retirement unit in sequence, and the instruction fetch unit is used as the front end of the RISC-V processor; a five-level pipeline architecture formed by the decoding unit, the transmitting unit, the physical register file, the execution unit and the retirement unit is used as the rear end of the RISC-V processor; through the technical scheme, the invention provides a micro-architecture which is more balanced in performance and power consumption, so that the applicability of a processor core in a scene with high computing requirements and sensitive power consumption is improved.

The invention discloses a hybrid expert model reasoning method based on cooperation of a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and belongs to the field of deep learning. According to the method, a CPU-GPU computing framework of a hybrid expert model is constructed, heterogeneous computing resource loads are effectively balanced, and the hardware utilization rate is remarkably increased; an intelligent cache management mechanism based on dynamic priority scores is provided, high-demand experts are reserved preferentially, and the transmission overhead caused by cache missing is reduced; through pipeline parallel design for separating calculation and transmission tasks, CPU calculation and PCIe transmission are overlapped in the GPU execution period, and delay is effectively hidden. In addition, in combination with a multi-layer expert activation prediction prospective prefetching mechanism, the expert cache hit rate is improved. The method is compatible with hybrid expert models of different scales and structures, and stable and efficient reasoning acceleration is realized on a resource-limited heterogeneous platform.

This disclosure describes techniques relating to development of data flow pipelines. In one example, this disclosure describes a method that includes accessing, by a computing system, metadata identifying characteristics of a data flow pipeline; generating, by the computing system and based on the metadata, the data flow pipeline, wherein the data flow pipeline includes a plurality of stages, and wherein the plurality of stages includes a multi-sourced stage in which data output by each of a subset of stages in the plurality of stages are used as input to the multi-sourced stage; executing, by the computing system, the data flow pipeline; detecting, by the computing system, modifications to the metadata; generating, based on the modifications, an updated data flow pipeline; and executing, by the computing system, the updated data flow pipeline.

An exemplary system and method that generate a finite state automaton of a controller for sequential decision-making of a computing device for a user-requested task, the generation using automaton-based representations derived from outputs of a large-scale generative language model. The exemplary system and method receive a user command and (i) construct the finite state automaton by parsing GLM responses to prompts / queries for candidate steps and sub-steps for the task, and (ii) verify the finite state automaton, e.g., for logical errors, safety specification, performance specification, and intent of the user, and / or update the finite state automaton to meet such specifications. The state machine can be synthesized on the fly for real-time operation via the GLM outputs and evaluated in the same pipeline operation against physical models, safety models, etc., that can be combined to iteratively modify the state machine until it meets the verification requirements.

The invention relates to the technical field of large model computing clusters, in particular to a large model computing cluster service reliability evaluation and optimization method, device and equipment based on parallel policy scheduling and a computer storage medium. According to the large model computing cluster service reliability evaluation and optimization method, the flow line parallel behavior is taken as the core, the influence of the performance difference between different GPUs, the data transmission time and the uncertainty factors on the training time in the training process is comprehensively considered, the existing staggered and non-staggered flow line parallel strategies are combined, and the reliability of the large model computing cluster service is evaluated and optimized. According to the method, a model which fully considers inconsistency of training time and combines various pipeline parallel strategies is established, specific constraints of a training process are given for specific characteristics of large model training, and the model is solved through integer programming so as to realize efficient and reliable training of a large model computing cluster.

The invention discloses a distributed training scheduling and communication optimization method and system of a multi-modal large model on a domestic computing power platform. The method comprises the following steps: virtualizing a heterogeneous computing unit of a preset platform into a virtual device pool, and fusing first-order gradient of a multi-modal sample and Hessian matrix information based on quantitative perception training to generate a sample sensitivity grading atlas; virtual device pool attributes and the sensitivity grading atlas are used as input, an optimal hybrid parallel configuration scheme is automatically generated through a configuration search algorithm, and a parallel combination mode, resource mapping and a high-sensitivity sample scheduling strategy are defined; a distributed training code of an integrated communication optimization strategy is automatically generated according to a configuration scheme, pipeline parallel communication and data parallel gradient synchronization constraint are executed in a topology adjacent equipment subset, and a hierarchical aggregation mechanism is adopted; and dynamically screening a core training set and scheduling a calculation task to complete distributed training. According to the method, efficient cooperative training of the multi-modal large model on the domestic computing power platform is realized.

The invention relates to the technical field of distributed computing and computing power scheduling, in particular to a computing power resource fusion method based on a distributed flow pipeline, which comprises the following steps of: disassembling a user computing power request into a flow pipeline unit for packaging computing logic, an input / output interface and a resource demand label; meanwhile, computing power types, real-time load rates, memory occupancy rates, network round-trip delays, geographic positioning and energy consumption data of cloud edge end nodes are collected, a hierarchical topology network framework is constructed based on the collected data, node computing power available values are calculated, an inter-node transmission cost matrix is generated, a fault probability prediction model is constructed, and a fault probability prediction model is constructed. And finally, analyzing a data dependency relationship of the pipeline unit through a four-dimensional joint decision engine, executing dynamic mapping, and preferentially mapping the high-computing-power demand unit to a GPU cluster node, so as to realize non-interruption reconstruction during pipeline topology operation. And the global computing power resource utilization rate, the task operation efficiency and the service stability are improved.

The invention relates to a cluster-oriented large model parallelization method and device and an electronic device.The method is applied to the field of large models.The method comprises the steps that operator information of a cluster-oriented large model in a preset microprocessing batch and a preset parallelization mode is obtained, the operator information comprises operator time information and operator memory information of operators in the cluster-oriented large model; the cluster comprises one or more types of accelerators; determining an initial operator parallel configuration strategy of a plurality of assembly lines in the large model based on the operator information, model memory information required by the large model and a memory extreme value of an accelerator; and performing recursion processing on the initial operator parallel configuration strategy according to a preset load balancing mode to obtain a target operator parallel configuration strategy, and running the cluster-oriented large model based on the target operator parallel configuration strategy. According to the method and the device, the utilization efficiency of chip calculation performance during large model parallel configuration is improved, and high efficiency and wide application range of large model training are realized.

The embodiment of the invention provides a case and computing equipment, the case is applied to the computing equipment, the case comprises a shell, the computing equipment comprises a computing module, a power supply module and a pipeline group which are arranged in the shell, the computing module comprises a liquid cooling module and a computing force plate, the liquid cooling module is provided with a cooling flow channel for a cooling medium to flow, and the cooling flow channel is provided with a liquid outlet. The cooling flow channel is communicated with the pipeline group, a containing cavity and a pipeline cavity are defined in the case, the containing cavity is used for containing the calculation module and the power module, and the pipeline cavity is used for containing the pipeline group, so that the calculation module, the power module and the pipeline group are integrated, maintenance is easy, and occupied space of the case is reduced; and the appearance of the case is neater and more attractive.

A data pipeline validation system and method configured to partially automate testing of data pipelines in a distributed computing environment. The system includes a data pipeline analytic device equipped with various modules, such as a query generation module, data frame comparison module, and metadata management module. The query generation module employs natural language processing techniques to analyze configuration entries and dynamically generate SQL queries tailored to specific test cases. The data frame comparison module compares the results of different test cases using distributed collections, enabling parallel processing and efficient result comparison. The metadata management module captures and stores relevant metadata for traceability and auditing purposes. The system facilitates comprehensive validation of data pipelines, enabling organizations to ensure the accuracy, reliability, and integrity of data.

The invention provides a BLAS3 structured operator accelerated computing system based on a Hopper architecture GPU, and relates to the technical field of computers. The system comprises: a calculation unit discrimination module for determining a calculation unit used by a current operator during operation, and estimating the maximum row dimension upper bound of the current operator in a tensor core execution path; an instruction sensing block parameter determination module dynamically determines the optimal block size and number of the input matrix in real time; the block matrix loading and aligning module divides an input matrix and a matrix to be updated into sub-matrixes by taking the block size as a basic block and completes loading of the corresponding sub-matrixes; the operator kernel function execution module completes shared memory structured parallel loading and storage of a double-precision floating-point number array of a sub-matrix corresponding to the input matrix, and calls a tensor core to carry out multiply-add accumulation calculation; and the assembly line and concurrent scheduling module adds the block calculation tasks into corresponding task sets and performs multi-stream concurrent scheduling on the task sets.

The invention discloses an efficient hybrid parallel training method for a multi-modal model, and belongs to the technical field of computers. The method comprises the steps that firstly, a multi-modal model architecture is divided into a plurality of independent modal sub-modules according to the multi-modal model architecture, and each sub-module processes one kind of modal data; secondly, formulating a computing power distribution scheme by statically analyzing the computing load of each sub-module; calculating time and parameter quantity of each layer of a modal sub-module are analyzed, then the layers are divided into a plurality of stages by using a partition algorithm, and asynchronous pipeline parallel and data parallel are combined to accelerate training; according to the method, the hardware resource utilization rate is remarkably improved through the calculation power distribution and hybrid parallel strategy for the modal calculation load, and the acceleration of the multi-modal model training process is realized.

Techniques described herein may be implemented in the context of a computing resource service provider. A machine learning (ML) service provides an interface to clients which can be used to create, read, update, and delete ML pipelines. ML pipelines can be converted to a human-readable format, which a server persists. Clients of a machine learning service can start, stop, and resume executions a ML pipeline based on the human-readable format of the ML pipeline.

The invention provides a multi-modal basic model convolution operation optimization framework method suitable for a GPU / DCU. The method is used for solving the technical problems that the optimization process of an existing convolution operator optimization method is time-consuming and cross-layer operator fusion is difficult to capture. The method comprises the following steps: receiving a convolution operator through a parameterized input interface; collecting shape features of each convolution operator in the structured parameter set by using a shape analyzer to realize convolution feature analysis; judging whether batch normalization and nonlinear activation function fusion calculation is started or not; a heuristic optimizer dynamically selects a calculation graph optimization strategy based on convolution parameter characteristics; a calculation task is adapted to a physical architecture of the GPU / DCU, so that hardware resources are utilized to the maximum extent; a convolution calculation kernel function oriented to DCU / GPU architecture optimization is generated based on the convolution parameter features; kernel function assembly line execution is achieved through a DCU / GPU hardware task queue; gradient synchronization among multiple computing units is realized by adopting atomic operation at an equipment end. According to the method, the execution efficiency of the convolution operation in the multi-modal basic model can be remarkably improved.

In an example, an apparatus is described. The apparatus comprises processing circuitry comprising a control module. The control module determines whether a computing device communicatively coupled to the control module is in a specified state for executing a machine learning model controlled by a third party entity. In response to determining that the computing device is in the specified state, the control module is to send, to an attestation module in a data processing pipeline associated with the computing device, an indication that the computing device is in the specified state.

An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a processing circuit with multiple compute circuits for executing wavefronts of a parallel data application. Each compute circuit includes a local memory subsystem for accessing data not found in vector register files of the compute circuit. The local memory subsystem includes a first execution pipeline and a second execution pipeline. The second execution pipeline processes vector stack access instructions that access temporary data such as stack data of a function call used by each wavefront that is generated based on the function call. The first execution pipeline processes other types of vector memory access instructions and includes multiple complex pipeline stages not found in the second execution pipeline. Thus, the second execution pipeline has a latency less than the latency of the first execution pipeline.

A set of features including a first feature and a second feature is received at a server. A subset of the set of features is determined for use in generating a model usable by a device to locally make a malware classification decision. The device has reduced computing resources as compared to computing resources of the server. The subset of the set of features is used to generate the model. The generated model includes the first feature and does not include the second feature. A determination is made, at a time subsequent to the generation of the model, that an updated model should be deployed to the device. An updated model is generated.

The invention relates to a reinforcement learning driven intelligent telescoping and tuning method in a big data pipeline, and relates to the technical field of big data processing and computing, and the method comprises the steps: (1) data pipeline operation and state monitoring; (2) extracting resource indexes and features; (3) data preprocessing and model initialization; (4) a dynamic adjustment algorithm based on LinUCB is operated; (5) a periodic reset and quick response mechanism; (6) applying and evaluating a resource configuration result; (7) saving and continuously optimizing an adjusting and optimizing result; according to the method, on the basis of a dynamic adjustment strategy of a context tiger machine algorithm, system state characteristics of an Apache NiFi data pipeline are collected in real time, an online learning mechanism is combined, the thread count, memory allocation and CPU core number configuration are optimized step by step, and intelligent scaling and tuning of the data pipeline are achieved on the basis, so that the throughput rate, the resource utilization rate and the load balancing capacity are improved.

The invention discloses a detection and correction device and method based on an RISC-V architecture, belongs to the technical field of processor micro-architectures, and aims to solve the technical problem of how to carry out error detection and correction on an instruction execution process, hardware resources, system reliability, instruction storage, a data path and related system performance in the RISC-V architecture. Comprising a computing core, a cross validation module, a dynamic voting module, a lock step execution module and a hardware multiplexing module, the processor is used for comparing and checking the instruction execution results output by the three calculation cores based on a triple modular redundancy technology and a dynamic voting fault-tolerant technology, and determining the instruction execution result with correct voting through a two-out-of-three voting mode; the lock step execution module is used for controlling lock step execution and assembly line rollback operation of the calculation core; and the hardware multiplexing module is used for multiplexing the same RISC-V pipeline to process normal execution, lock step and rollback operations.

The invention provides a hash method, a hash calculation system, electronic equipment and a storage medium, and the method comprises the steps: filling data, and obtaining a to-be-compressed message; inputting the to-be-compressed message and the first group of message words into a first pipeline structure for compression to obtain a first compressed message; inputting the first compressed message into a second pipeline structure; and compressing the second compressed message output by the nth parallel computing unit based on the (n + 1) th message word output by the nth parallel computing unit, and generating an (n + 2) th message word based on the (n + 1) th message word for the (n + 2) th parallel computing unit to compress. Thus, when the compression function module carries out compression, the message word extension module carries out extension calculation of a next message word at the same time to form parallel calculation of the compression function and message word extension, the compression function module and / or the parallel calculation unit are / is connected through the register to form pipeline calculation, and the compression efficiency and the throughput rate of the compression process are improved.

A real-time target detection method and system based on RTSP flow and NPU collaborative optimization belong to the technical field of computer vision and artificial intelligence, and are characterized by comprising the following steps: adopting dynamic memory optimization management of a hybrid pipeline architecture, and performing single-time continuous copying through a CPU (Central Processing Unit); through deep integration of innovative technologies such as DMA direct transmission NPU continuous memory pool management, dynamic batch processing scheduling, hybrid assembly line processing, intelligent equipment load balancing, parallel preprocessing optimization and vectorization post-processing, RTSP flow collaborative optimization and the like, the NPU utilization rate is improved to 85% or above, the overall average FPS is improved by 200% or above, the assembly line parallelism degree achieves three times of performance gain, and the production efficiency is greatly improved. The data transmission delay is reduced by 80%, the system stability is remarkably improved, performance degradation is avoided after long-time operation, and the method is suitable for various scenes such as edge calculation and cloud reasoning.

The invention belongs to the related technical field of distributed system optimization and scheduling, and particularly relates to a distributed parallel training method of a deep neural network in a dynamic computing environment, which comprises the following steps of: determining a model segmentation scheme by minimizing the actual convergence time of an asynchronous pipeline, the model slices corresponding to the segmentation scheme are distributed to corresponding equipment nodes, and the actual convergence time is the product of the upper limit of the number of iterations corresponding to a preset convergence error and the optimal running time of the assembly line required by single iteration; each device node is configured with a trained lightweight random forest model which is used for evaluating the interference influence of the additional load located at the device node on the training efficiency of the model slice located at the device node. After training is started, interference coefficients corresponding to interference influences obtained by the random forest models on all equipment nodes are obtained in real time, a new segmentation scheme is obtained through model search space pruning and a traversal algorithm, and efficient training is achieved through layer migration.

The invention discloses a large-bandwidth network flow protocol identification and analysis method and system, and relates to the technical field of network flow protocol analysis processing. The method comprises the following steps of: receiving original traffic of a network, storing the original traffic in a kernel mode buffer area in a data frame form, and directly mapping the data frame in the kernel mode buffer area to a user mode memory area based on a zero copy technology, logic classification is conducted on the data flow, the data flow is sent to the corresponding calculation processing cores through a dynamic distribution mechanism, and each calculation processing core completes layer-by-layer identification and analysis on a flow protocol and extracts corresponding metadata from a protocol identification result. According to the method, a protocol identification method of a three-level pipeline architecture is adopted in a computing processing core, layer-by-layer identification and analysis of a traffic protocol are completed, high-complexity deep analysis of all traffic is avoided, the whole identification process does not need to be reconstructed in the face of a newly-added protocol or a complex protocol, and each stage is independently optimized.

Systems, methods, and computer-readable storage media for pipeline modeling. A data protection system can include one or more processing circuits including memory and at least one processor configured to verify a state of cybersecurity of an entity based on one or more cybersecurity measures implemented by the entity at a time of a catastrophic incident and generate data comprising the state of the cybersecurity from cybersecurity incident data based on at least on at least one categorized incident and corresponding at least one claim. The at least one processor can determine at least one categorized incident corresponding with at least one claim corresponds to the catastrophic incident based on at least on the data, generate a claim data package comprising the data and the catastrophic incident, and provide the claim data package to a computing system.

The invention relates to the technical field of industrial big data processing and algorithm scheduling, and particularly discloses an industrial algorithm model scheduling method and system for industrial big data, and the method comprises the steps: constructing an algorithm dependency graph of an execution pipeline composed of a plurality of industrial algorithms, bottleneck nodes influencing the overall performance are identified through a critical path analysis algorithm; carrying out operation fusion on algorithm pairs with close dependency relationships; optimal data partitioning strategies are determined for different algorithms, and an elastic execution pipeline is realized; allocating the most matched heterogeneous computing resources for the algorithm operation on the critical path, and adjusting the execution priority of the algorithm operation in real time according to the system load and the operation scene; a fine-grained synchronization system is realized; the industrial algorithm execution efficiency is improved, and the high-performance requirement of an industrial big data processing scene is met.

A method for managing radio and computing resources of a virtualized radio access network (vRAN) includes a number of virtualized radio access points (vRAPs) that share a common pool of central processing units (CPUs). The method includes dividing, per vRAP, an L1 layer processing pipeline into at least one main processing pipeline and into a number of subordinate processing pipelines, and coordinating the execution of the pipelines across multiple vRAPs. The coordinating includes allocating tasks of the main processing pipelines to dedicated CPUs, and allocating tasks of the subordinate processing pipelines to shared CPUs.

This application discloses a model training method and apparatus based on a hybrid parallelism manner. In this method, a neural network model is divided into a plurality of pipeline stages, and each pipeline stage includes a plurality of sub-stages of the neural network model. Computing nodes corresponding to the plurality of pipeline stages are invoked in a hybrid parallelism manner according to a sequence of sub-stages in the neural network model. When iterative training is performed on a network layer in a corresponding pipeline stage, because sub-stages at same locations in adjacent pipeline stages are consecutive in the neural network model, the computing node does not need to wait for completion of forward propagation of a previous pipeline stage, and can perform forward propagation on the corresponding pipeline stage only after forward propagation of the 1st sub-stage in the previous pipeline stage is completed.

A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a compute graph for execution on a reconfigurable dataflow processor comprising a grid of compute units and grid of memory units interconnected with a switching array. The compute graph includes a node specifying an operation on a tensor. The node may be split into multiple nodes that each specify the operation on a distinctive portion of the tensor to produce a first modified compute graph. The first modified compute graph may be executed. In addition, the multiple nodes may be within a single meta-pipeline stage and may be processed in parallel. Furthermore, the compute graph may further comprise a separate node for gathering the distinctive portions of the tensor into a complete tensor, to produce a second modified compute graph.

The invention discloses a GPGPU computing task processing method, device and equipment and a medium, and relates to the technical field of computers, the GPGPU computing task processing method and device are applied to a field programmable gate array of a task distribution terminal in a GPGPU scheduling control end, the GPGPU scheduling control end further comprises a host end, and the task distribution terminal and the host end are connected with a GPGPU resource pool through a CXL switch; comprising the steps of obtaining the total amount of to-be-processed data of a calculation task issued by a host end, a corresponding target task execution strategy and target strategy complexity; processing the parameters by utilizing a resource evaluation algorithm so as to screen out a target task processing mode of the calculation task; and if the target task processing mode is a multi-card pipeline processing mode, splitting the computing task into a plurality of computing sub-tasks, transmitting the computing sub-tasks to each target GPGPU computing card through the CXL switch, and returning processing results output by the computing cards to the host end. The computing task processing efficiency is improved; and the load of a host end is reduced.