42results about How to "Improve hardware utilization" patented technology

A circuit arrangement and method support a multithreaded rendering architecture capable of dynamically routing pixel fragments from a pixel fragment generator to any pixel shader from among a pool of pixel shaders. The pixel fragment generator is therefore not tied to a specific pixel shader, but is instead able to utilize multiple pixel shaders in a pool of pixel shaders to minimize bottlenecks and improve overall hardware utilization and performance during image processing.

A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be configured to (i) load the first program directly from the multiported memory to program a codec function and (ii) generate a video output signal by performing the codec function on a video input signal using video data exchanged with the multiport memory.

The embodiment of the invention discloses an indoor positioning method, device and system based on RFID (radio frequency identification). The method comprises the following steps of controlling an RFID antenna to rotate at the preset angle; obtaining the rotating angle of the RFID antenna for rotating to the current position; scanning a label; obtaining the label signal intensity corresponding to the rotating angle; determining a first elliptic equation and a second elliptic equation corresponding to the label according to the rotating angle, the label signal intensity and the rotating antenna positioning algorithm; processing the first elliptic equation and the second elliptic equation according to the elliptic intersection point calculation algorithm to obtain the corresponding two elliptic intersection points; whether the distance between the intersection point and the origin is greater than the first preset distance or not; if so, the intersection point is output; otherwise, the rotating angle when the RFID antenna rotates to another position is continuously obtained, and the cyclic operation is performed until the final intersection point is obtained. The embodiment of the invention has the advantages that only one RFID antenna is used; the advantages of simple system structure, low cost, low deployment difficulty and high hardware utilization rate are realized.

The invention relates to a content addressing method based on a hash chain table and a corresponding storage circuit. The storage circuit includes a storage unit, a control unit, a register interface and a data search comparison interface. The content addressing method adopts the methods of hash, chain, multi-character parallel storage, comparison and the like, resolves the problem in the prior art of use limit caused by the fact that a special process or a device is adopted to achieve the content addressing storage and the problems of small content addressing search speed, large consumption resources, difficulty in content addressing search depth and width expansion and the like in a traditional design method, has the advantages of being high in generality, high in search speed, high in hardware utilization rate, easy to expand and the like, and is not limited by the chip process or a field programmable gate array (FPGA) device.

The invention discloses a special circuit for a neural network and a related computing platform and implementation method thereof. The special circuit comprises: a data reading module which comprisesa feature map reading sub-module and a weight reading sub-module which are respectively used for reading feature map data and weight data from an on-chip cache to a data calculation module when a depthwise convolution operation is executed, wherein the feature map reading sub-module is also used for reading the feature map data from the on-chip cache to the data calculation module when executing pooling operation; a data calculation module which comprises a dwconv module used for executing depthwise convolution calculation and a pooling module used for executing pooling calculation; and a datawrite-back module which is used for writing a calculation result of the data calculation module back to the on-chip cache. The use of hardware resources is reduced by multiplexing the read logic andthe write-back logic of the two types of operations. The special circuit provided by the invention adopts a high-concurrency pipeline design, so that the computing performance can be further improved.

The present invention provides an internet health detection system with an advertisement network function. The system comprises a communication network, a cloud platform, an advertisement push device, a health advertisement all-in-one machine, a mobile terminal and a big data server that are all communicated with the communication network. The big data server acquires a physical sign database for detection by the health advertisement all-in-one machine from the cloud platform through the communication network, analyzes the physical sign database, determines health defects or lesion existing in the physical sign database, and sends an advertisement push advise related to the defects or lesion to the advertisement push device. The advertisement push device pushes advertisement information suitable for watching by corresponding users to the health advertisement all-in-one machine to play. The mobile terminal is used for identity logging by the user, authenticating or acquiring the physical sign database. Through adoption of the system, a hardware use ratio of a traditional advertisement system is improved, a function of checking detection data and advertisement information remotely at any time is realized, advertisement display attention is increased, and a crowd effect is improved.

The invention provides an H.264 high-speed luminance interpolating device comprising a reference caching module, a register input control module, a register set, a filter input control module, N paths of six-tap filters, an RAM (Random-Access Memory) caching I/O control module and an RAM caching module. The reference caching module reads reference pixel matrixes required for the interpolation of the current luminance block from the outside, the reference pixel matrixes are put in the register set after fully being read in the reference caching module, the N paths of six-tap filters simultaneously and respectively obtain six reference pixels as inputs from the register set through the filter input control module, and 1/2 pixel points are acquired and then are cached in the RAM caching module. The whole interpolating process of the device achieves a saturated state through the steam running of multiple parallel filters so that the device effectively reduces the luminance interpolating clock number, improves maximum calculating frequency and satisfies the demands of the real-time encoding and decoding of multiple high-definition digital video signals.

The invention discloses a coarse-grained reconfigurable array structure design method based on data flow decoupling and a decoupling unit. The invention relates to the field of computer coprocessor acceleration. A data flow coupling phenomenon causing pause of an assembly line in a static CGRA is concluded as mutual influence generated by different data flow rates caused by factors such as memoryaccess, control and the like; decoupling is carried out, the decoupling unit is designed and inserted into the coupling interaction position between different areas, the decoupling unit serves as a unified memory access interface, assembly line pause of different forms is optimized, and the CGRA performance and the resource utilization rate are improved.

A digital logic unit can be reconfigured and includes: a plurality of logic cells (19, 26) that have configurable properties; a memory (13) with a plurality of microprograms (14, 16) that contains information on the functionality of a plurality of logic cells (19, 26), at least one of the microprograms (14, 16) being reprogrammable depending on a certain application at least during the current operation of the logic unit; elements for selecting at least one microprogram (14, 16); and elements for configuring logic cells corresponding to the functionality information of the selected microprogram (14, 16) at least during the current operation of the logic unit.

The invention provides a collaborative data processing method. The method comprises the following steps: keeping data synchronization of a first-zone server and a second-zone server; setting the first-zone server to be in a first-zone data readable and writable state and a second-zone data writable state; setting the second-zone server to be in a first-zone data writable state and a second-zone device readable and writable state; when it is detected that data destruction of more than a predetermined degree occurs to the first-zone server, setting the first-zone data writable state of the second-zone server to be the first-zone data readable and writable state; or when it is detected that the data destruction of more than the predetermined degree occurs to the second-zone server, setting the second-zone data writable state of the first-zone server to be the second-zone data readable and writable state. According to the collaborative data processing scheme, the synchronization speed is high, a business service can be completely provided, and the requirement of double center data consistency can be met.

The invention discloses a flow control method and device, a server and a storage medium. The method comprises the following steps: acquiring first information; wherein the first information representsflows generated on all second servers, the second servers are registered in a distributed cluster corresponding to the first service, and at least two second servers are registered in the distributedcluster; wherein the flow generated on each second server is obtained by counting the query request received by the corresponding second server by the atomic lock; the atomic locks are arranged in the corresponding second servers; according to the flow quota of each second server in the at least two second servers and the first information, flow control about the first service is carried out; wherein the traffic quota of each second server is determined based on the total traffic quota of the first service and the configuration parameters of the corresponding second server.

The invention relates to a system and a client for big data synchronization. Compared with the traditional scheme, the hardware utilization rate is high, the cost is greatly reduced, the socket communication is adopted, the transmission rate is effectively improved, an assembly line model is used for real-time data synchronization demands of a cryo-electron microscope, and the transmission speed can be greatly improved; and the software client is already packaged, the professional does not need to build network service, thereby being convenient, fast and easy to use, and users can use directlyopen the software for use without professional training.

A reconfigurable polar code and low density parity check code decoder comprises an RDU cluster, a decoding controller, a storage controller and a reconfigurable memory, the decoding controller dynamically regroups the RDU of each code word in the RDU cluster according to a decoding mode and a decoding mode, generates an instruction word and outputs the instruction word to the RDU cluster and the storage controller, the storage controller generates a corresponding read-write control signal and an address signal according to the instruction word and outputs the read-write control signal and the address signal to the reconfigurable memory for read-write control, and the reconfigurable memory reads information data from the RDU cluster and writes in or reads information and outputs the information to the RDU cluster. According to the invention, the similarity of BP decoding algorithms of an LDPC code and a polarization code is utilized, the reconfigurable decoder of the reconfigurable LDPC code and the polarization code is realized, and compared with the mode of independently realizing LDPC decoding and polarization code decoding, the decoder has the advantages that hardware resources are saved, and the utilization rate of the hardware resources is improved.

Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.

The embodiment of the invention provides a convolution calculation acceleration method and device, and the method comprises the steps: obtaining a current depth time sequence i when the convolution type is depth-first convolution; inputting the column pixels in the convolution kernel corresponding to the current depth time sequence i and the row pixels in the feature map into a convolution calculation unit, wherein the convolution calculation unit is an array composed of multipliers and adders; if the imodK is equal to 0, translating the first row of pixels of the convolution kernel to the last row, wherein K is the number of rows and columns of the convolution kernel; and if the imodK is equal to 0 and i is greater than or equal to K<2>, taking the (i-k<2>)/k+1 modk th line feature in theconvolution calculation unit as the output feature of the (i-k<2>)/k+1 th line depth first convolution. According to the method and the device provided by the embodiment of the invention, the hardware utilization rate of the convolution calculation unit is effectively improved, the energy waste caused by the idleness of a large number of multipliers is avoided, and the depth-first convolution calculation efficiency is improved.

Presented are systems and methods to automatically find efficient parallelization strategies for deep neural networks (DNNs). A computation graph comprising an efficiently ordered sequence of vertices aids in computing the best parallelizing strategy in a relatively short time. Effectiveness of the parallelization strategies is evaluated on various DNNs, and the performance of the strategies proposed by various embodiments is compared against data parallelism, expert-designed strategies, and other state-of-the-art approaches. Experimental results demonstrate that the proposed strategies outperform a baseline data parallelism strategy and achieve better performance than expert-designed strategies and state-of-the-art approaches.