Coarse-grained reconfigurable array structure design method based on data flow decoupling

A technology of array structure and design method, applied in the direction of program control design, electrical digital data processing, calculation, etc., can solve the problems that spatial mapping is difficult to resist dynamic delay, performance degradation, and decrease of computing unit utilization, and achieve abstract consistency Hardware Utilization, High Hardware Utilization, Effect of Improved Performance and Resource Utilization

Active Publication Date: 2020-07-31
SHANGHAI JIAO TONG UNIV +1
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Static CGRA has higher computing power and lower area power consumption due to the removal of context scheduling overhead, but because space mapping is difficult to resist dynamic delay, it is easy to cause pipeline stalls and cause performance degradation
[0004] Although static CGRA has advantages in computing p

Method used

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  • Coarse-grained reconfigurable array structure design method based on data flow decoupling
  • Coarse-grained reconfigurable array structure design method based on data flow decoupling
  • Coarse-grained reconfigurable array structure design method based on data flow decoupling

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Embodiment Construction

[0036] The following describes several preferred embodiments of the present invention with reference to the accompanying drawings, so as to make the technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned herein.

[0037] Similar numerals indicate. The size and thickness of each component shown in the drawings are shown arbitrarily, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of parts is appropriately exaggerated in some places in the drawings.

[0038] CGRA uses data flow graph (DFG) as an intermediate product between software code and hardware mapping. Data flow graph can effectively express the dependencies between operations, and can remove non-data-related dependencies to achieve higher parallelism. .

[0039]...

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Abstract

The invention discloses a coarse-grained reconfigurable array structure design method based on data flow decoupling and a decoupling unit. The invention relates to the field of computer coprocessor acceleration. A data flow coupling phenomenon causing pause of an assembly line in a static CGRA is concluded as mutual influence generated by different data flow rates caused by factors such as memoryaccess, control and the like; decoupling is carried out, the decoupling unit is designed and inserted into the coupling interaction position between different areas, the decoupling unit serves as a unified memory access interface, assembly line pause of different forms is optimized, and the CGRA performance and the resource utilization rate are improved.

Description

technical field [0001] The invention relates to the field of computer coprocessor acceleration, in particular to a coarse-grained reconfigurable array structure design method based on data flow decoupling. Background technique [0002] The existing coarse-grained reconfigurable array (Coarse-Grained Reconfigurable Array, CGRA) implements the mapping of application functions through a configurable processing unit (Processing Element, PE) and an Internet. Common coarse-grained reconfigurable systems include host interfaces, controllers, storage hierarchies, and PE arrays. The host interface completes the interaction between the CGRA and the main control core, such as task scheduling from the main core to the CGRA, task completion signals from the CGRA to the main core, and so on. The controller completes the scheduling of tasks on the PE array, array configuration before execution, and status monitoring of the PE array. The storage hierarchy provides data storage space for C...

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Application Information

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IPC IPC(8): G06F9/38G06F12/1027
CPCG06F9/3867G06F9/3877G06F12/1027Y02D10/00
Inventor 景乃锋洪途张子涵关宁王琴毛志刚贺光辉蒋剑飞绳伟光
Owner SHANGHAI JIAO TONG UNIV
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