Hardware testing method and device, equipment and storage medium

Abstract

The invention provides a hardware testing method and device, equipment and a storage medium, and the method comprises the steps: dividing a testing diagram into at least two sub-testing diagrams, each sub-testing diagram comprises a * b regions, and a and b are integers equal to or greater than 2; generating a sub-graph state array, wherein the sub-graph state array is used for recording the test state of the region in the sub-test graph; respectively executing the following processing on one or more sub-test diagrams in the at least two sub-test diagrams to obtain a test result diagram corresponding to the to-be-tested hardware: determining a target area from the sub-test diagrams according to the sub-diagram state array; testing the to-be-tested hardware according to the test parameters corresponding to the target area to obtain a test result, and updating the sub-graph state array; performing filling processing on a target area of the test chart according to a test result; and after the test of each target area in the sub-test chart is completed, initializing the sub-chart state array. According to the method, the memory requirement during testing is reduced by multiplexing the sub-graph state array.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of hardware testing technology, and in particular, to a hardware testing method, apparatus, device and storage medium. Background Art

[0002] Chip testing refers to a series of physical and electrical tests after chip manufacturing is completed to ensure that the chip's functions and performance meet the design specifications, while discovering and eliminating any possible defects or problems.

[0003] When testing the performance of a chip, a Shmoo diagram can be used to display the performance of the chip under different conditions, helping engineers quickly locate and debug problems. The Shmoo diagram displays the scan results in a two-dimensional coordinate system by scanning two key performance indicators, such as reference voltage (Vref) and timing (Timing), and intuitively displays the relationship between the two variables. Using Vref and Timing as test variables to test whether the chip has bit errors or the number of bit errors, scan all operating points (Vref, Timing), and the results obtained will form a two-dimensional eye diagram on the Shmoo diagram, which can be called a Shmoo eye diagram.

[0004] The test of Shmoo eye diagram can be implemented by using Flood Fill algorithm. However, whether the Flood Fill algorithm is executed in a recursive or non-recursive manner, it needs to occupy a large amount of memory. Summary of the invention

[0005] In view of this, embodiments of the present application provide a hardware testing method, apparatus, device and storage medium to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, a hardware testing method is provided, the method comprising: dividing a test graph into at least two sub-test graphs, the sub-test graphs comprising a×b areas, a and b being integers equal to or greater than 2; generating a sub-graph state array, wherein the sub-graph state array is used to record the test states of the areas in the sub-test graphs; performing the following processing on one or more of the at least two sub-test graphs, respectively, to obtain a test result graph corresponding to the hardware to be tested: determining a target area from the sub-test graph according to the sub-graph state array; testing the hardware to be tested according to the test parameters corresponding to the target area, obtaining a test result, and updating the sub-graph state array; filling the target area in the test graph according to the test result; and initializing the sub-graph state array after completing the test of each target area in the sub-test graph.

[0007] According to a second aspect of an embodiment of the present application, a hardware testing device is provided, the device comprising: a division module, used to divide a test image into at least two sub-test images, the sub-test images comprising a×b areas, a and b are both integers equal to or greater than 2; a generation module, used to generate a sub-image state array, wherein the sub-image state array is used to record the test status of the areas in the sub-test images; a processing module, used to perform the following processing on one or more sub-test images of the at least two sub-test images, respectively, to obtain a test result image corresponding to the hardware to be tested: determining a target area from the sub-test image according to the sub-image state array; testing the hardware to be tested according to the test parameters corresponding to the target area, obtaining a test result, and updating the sub-image state array; filling the target area in the test image according to the test result; and initializing the sub-image state array after completing the test of each target area in the sub-test image.

[0008] According to the third aspect of an embodiment of the present application, an electronic device is provided, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the hardware testing method provided in the first aspect above.

[0009] According to a fourth aspect of an embodiment of the present application, a computer storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the hardware testing method described in the first aspect is implemented.

[0010] According to a fifth aspect of an embodiment of the present application, a computer program product is provided, comprising computer instructions, wherein the computer instructions instruct a computing device to execute the hardware testing method described in the first aspect above.

[0011] According to the hardware testing solution provided in the embodiment of the present application, the original test graph is divided into multiple sub-test graphs, each sub-test graph includes a×b areas, and a sub-graph state array is generated to record the test status of the areas in the sub-test graph. By reusing the sub-graph state array, the test processing of the hardware to be tested is performed separately for each sub-test graph in one or part of the multiple sub-test graphs. Compared with recording the test status of the entire test graph, the memory required for recording the test status of the sub-test graph is significantly reduced, which greatly reduces the memory requirement during hardware testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0013] Figure 1 is a schematic diagram of an exemplary system used in one embodiment of the present application;

[0014] Figure 2 is a flowchart of a hardware testing method according to an embodiment of the present application;

[0015] Figure 3 is a flowchart of a hardware testing method according to an embodiment of the present application;

[0016] Figure 4 is a schematic diagram of subroutine 1 of an embodiment of the present application;

[0017] Figure 5 is a schematic diagram of subroutine 2 of an embodiment of the present application;

[0018] Figure 6 It is a schematic diagram of updating the state array of one embodiment of the present application;

[0019] Figure 7 It is a schematic diagram of running tests on each sub-test graph of an embodiment of the present application;

[0020] Figure 8 is a schematic diagram of a hardware testing device according to an embodiment of the present application;

[0021] Fig. 9 It is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0024] The Shmoo eye diagram is a two-dimensional chart used to show the performance of a chip under different conditions. Its working principle is to scan two key performance indicators on an automatic test equipment (ATE), an automated test system (ATS) or a traditional test platform, and display the test results in a two-dimensional coordinate system. The displayed test results will be in the shape of an "eye". This chart can intuitively show the working conditions of the chip under different conditions.

[0025] Taking Vref and Timing as key performance indicators, given the working point (Vref, Timing), the transmission (Transmit, Tx) side of the data input / output (Input / Output, I / O) channel sends a known pattern, and the receiving (Receive, Rx) side receives and compares the above pattern, scans all working points (Vref, Timing), records whether there is a bit error or the number of bit errors at each (Vref, Timing), and plots the corresponding test results of whether there is a bit error or the number of bit errors into a two-dimensional eye diagram to obtain a Shmoo eye diagram. The above Shmoo eye diagram can be used as an important basis for evaluating I / O electrical performance, and can also be used as basic data for signal integrity post-silicon signoff.

[0026] Exemplary Systems

[0027] Figure 1 An exemplary system suitable for the hardware testing method of the embodiment of the present application is shown. Figure 1 As shown, the system includes a basic input output system (BIOS), a first chip and a second chip.

[0028] The physical layer 110 of the first chip includes: a built-in self-test (BIST) unit 11, an input / output (I / O) unit 12, a comparator 13 and a result register 14. The built-in self-test unit 11 includes a parameter sweep control unit and a pattern generating unit. The parameter sweep controller can set the sweep range of multiple test parameters. For example, the sweep range of each test parameter can include a sweep start point, a sweep end point and a sweep offset point. The pattern generator can generate a test pattern according to test requirements.

[0029] The physical layer 120 of the second chip includes an input-output unit 21. A transmission connection is established between the input-output unit 12 of the first chip and the input-output unit 21 of the second chip. The first chip transmits a test signal to the second chip according to the test pattern generated by the pattern generator through the transmission connection between the input-output unit 12 and the input-output unit 21; the second chip receives and stores the test signal; the first chip reads the stored test signal from the memory core of the second chip through the input-output unit 12 and the input-output unit 21 again to obtain a feedback signal of the second chip; the input-output unit 12 sends the read feedback signal to the comparator 13, and the comparator 13 compares the test signal and the feedback signal to generate a test result, and sends the test result to the result register 14 for storage.

[0030] In other embodiments, the physical layer 120 of the second chip includes a comparator 22. After receiving the test signal, the second chip can also input the test signal into the comparator 22 through the input / output unit 21; the comparator 22 determines whether the received test signal is consistent with the expected one, generates a test result, and sends the test result to the result register 14 for storage.

[0031] In some other embodiments, the physical layer 120 of the second chip may further include a result register 23 , and the comparator 22 determines whether the received test signal is consistent with the expectation, and outputs the result to the result register 23 .

[0032] In some other embodiments, the physical layer 120 of the second chip may further include a built-in self-test unit 24, which includes a parameter scan controller and a pattern generator. The control signal sent by the basic input and output system can be sent from the first chip to the second chip, and the built-in self-test unit 24 of the second chip performs parameter scanning and test pattern generation; then, a test signal is transmitted to the first chip according to the test pattern; after receiving the test signal, the input and output unit 12 of the first chip inputs it to the comparator 13, and the comparator 13 determines whether the received test signal is consistent with the expected, generates a test result, and sends the test result to the result register 14 for storage.

[0033] It should be noted that the built-in self-test unit may be arranged in the physical layer of the chip, or arranged in the controller of the chip. In this embodiment, the built-in self-test unit is arranged in the physical layer of the chip for explanation.

[0034] The test algorithm provided in the embodiment of the present application is used to implement the hardware test method provided in the embodiment of the present application, wherein the hardware to be tested is the physical layer of the first chip or the second chip. The test algorithm can be run in BIOS, or in the inside of the chip controller, or in the inside of the physical layer, or in the inside of the BIST, or in the processor, so as to test the hardware to be tested.

[0035] Hardware Testing Methods

[0036] Based on the above system, an embodiment of the present application provides a hardware testing method, which can be executed by the ATS in the above system embodiment. The hardware testing method is described in detail through multiple embodiments below.

[0037] Figure 2 FIG. 1 is a flowchart of a hardware testing method according to an embodiment of the present application. Figure 2 As shown, the hardware testing method includes the following steps:

[0038] Step 210: divide the test graph into at least two sub-test graphs.

[0039] The sub-test image includes a×b areas, and a and b are both integers equal to or greater than 2.

[0040] The total size of the test image and the partition size used to divide the sub-test image are pre-set in the computer, for example, the partition size is a row and b column; the test image is divided into at least two sub-test images according to the partition size, so that each sub-test image includes a×b areas. If the total size of the test image is (a×m)×(b×n), the test image is divided into m×n sub-test images, where m and n are both integers greater than 1. For example, the total size of the test image pre-set in the computer is 128×64, and the partition size is 32×32. According to the partition size, the test image can be divided into 4×2 sub-test images, and each sub-test image includes 32×32 areas.

[0041] The total size of the test chart is set according to the number of combinations of the two test variables. For example, by taking different values ​​of the two test variables, we get (c×m)×(d×n) combinations, that is, (c×m)×(d×n) test working points. Then the total size of the test chart is set to (a×m)×(b×n), where c and d are both integers greater than 2, a is e times c, b is f times d, and e and f are both positive integers.

[0042] The above-mentioned area refers to a pixel area, and each pixel area may be composed of e×f pixels.

[0043] Step 220, generating a subgraph state array.

[0044] The sub-image state array is used to record the test state of the area in the sub-test image. The sub-image state array includes two arrays, namely a first array and a second array, wherein the first array is used to record the tested state of the area in the sub-test image, and the second array is used to record the state to be tested of the area in the sub-test image. Optionally, the sub-image state array can be in the form of a matrix, such as a Boolean matrix.

[0045] The computer can generate a sub-image state array according to the size of the sub-test image; or, generate a sub-image state array according to the number of areas included in the sub-test image. Optionally, the number of elements contained in each array in the sub-image state array is the same as the number of areas included in the sub-test image, and one element corresponds to the test state of one area. For example, if the sub-test image includes a×b areas, the sub-image state array includes 2×a×b elements. If the sub-image state array is a Boolean matrix, the size of the Boolean matrix corresponding to each array is also the same as the size of the sub-test image, and the sizes of both are a×b. Alternatively, the number of elements contained in each array is greater than the number of areas included in the sub-test image and less than twice the number of areas included in the sub-test image. For example, if the sub-test image includes a×b areas, the sub-image state array includes 2×(a+1)×(b+1) elements.

[0046] Step 230, perform the following processing on one or more sub-test images in at least two sub-test images, respectively, to obtain a test result image corresponding to the hardware to be tested: determine the target area from the sub-test image according to the sub-image state array; test the hardware to be tested according to the test parameters corresponding to the target area, obtain the test result, and update the sub-image state array; fill the target area in the test image according to the test result; after completing the test of each target area in the sub-test image, initialize the sub-image state array.

[0047] The computer performs the following processing for each sub-test pattern in the one or more sub-test patterns:

[0048] According to the test state marked by the sub-image state array, determine the test state as the target area to be tested from the sub-test image; test the hardware to be tested according to the test parameters corresponding to the target area, obtain the test results, and update the sub-image state array; fill the target area of ​​the test image according to the test results;

[0049] If it is determined that the sub-graph state array also includes the state information to be tested, returning to the step of determining the target area, and continuing the test of the hardware to be tested in the sub-test graph;

[0050] If it is determined that the sub-image state array does not include the state information to be tested, the sub-image state array is initialized, and the next sub-test image is determined, and the above processing is performed for the next sub-test image until the hardware test for one or more sub-test images is completed.

[0051] During the test process, the target area determined each time may be one or more. If there are multiple target areas, the following processing can be performed on each target area in turn: the hardware to be tested is tested according to the test parameters corresponding to the target area, the test results are obtained, and the sub-graph state array is updated; and the target area of ​​the test graph is filled according to the test results.

[0052] The obtained test results include the number of bit errors. After the hardware to be tested is tested according to the test parameters corresponding to the target area, the test status of the target area is updated to tested in the sub-graph state array, and if the number of bit errors indicated by the test result is within the value range, the test status of the untested area adjacent to the target area is also marked as pending, completing the update of the sub-graph state array.

[0053] Regarding the update of the test status of the target area, the value representing the test status of the target area in the first array is updated from the first value to the second value, and the value representing the test status of the target area in the second array is updated from the third value to the fourth value, which indicates that the target area is updated to have been tested. Regarding the update of the test status of the untested area adjacent to the target area, the value representing the test status of the area to be tested in the second array is updated from the fourth value to the third value, wherein the area to be tested is the untested area adjacent to the target area in the test diagram. For example, the first array and the second array are both Boolean matrices. If the test status of an area is tested, the value representing the test status of the area in the first array is 1, and the value representing the test status of the area in the second array is 0; if the test status of an area is to be tested, the value representing the test status of the area in the first array is 0, and the test status of the area in the second array is 1; if the test status of an area is untested, the value representing the test status of the area in the first array is 0, and the test status of the area in the second array is 0. The "untested" test status here refers to a test status other than tested and to be tested. After the test, update the test status of the target area, update the value of the test status of the target area in the first array from 0 to 1, and update the value of the test status of the target area in the second array from 1 to 0; update the test status of the area to be tested, update the value of the test status of the area to be tested in the second array from 0 to 1, and the value of the test status of the area to be tested in the first array remains unchanged and remains 0.

[0054] Regarding the determination of the target area, the areas in the sub-test image whose values ​​of the test state are the third values ​​may be determined as target areas according to the second array; or, the areas in the sub-test image whose values ​​of the test state are the third values ​​may be determined as target areas according to the second array. For example, the area in the sub-test image corresponding to the value 1 in the second array may be determined as the target area.

[0055] When the values ​​representing the test status in the second array are all fourth values, it means that there is no area to be tested in the sub-test image of the current test, the test of the sub-test image is ended, and the next sub-test image is determined and the test is continued for the next sub-test image.

[0056] Regarding the determination of the area to be tested, it needs to be executed based on the test results. A value range is pre-set in the computer. If the number of bit errors indicated by the test result is within the value range, the test status of the untested area adjacent to the target area is marked as to be tested. If the number of bit errors indicated by the test result is outside the value range, the status update of the relevant area to be tested is not performed. Optionally, the value range is (0,255), that is, greater than 0 and less than 255. If the number of bit errors indicated by the test result is within (0,255), the test status of the untested area adjacent to the target area is marked as to be tested; if the number of bit errors indicated by the test result is 0 or 255, the status update of the relevant area to be tested is not performed.

[0057] Optionally, the test result diagram is an eye diagram. For example, the test diagram is a Shmoo eye diagram. In a possible implementation, a filling process is performed in the target area of ​​the test diagram according to the test result, and the filling process may be digital filling or color filling. If data filling is adopted, the number of bit errors indicated by the test result is filled into the target area of ​​the test diagram. If color filling is adopted, if the number of bit errors indicated by the test result is within a value range, the color corresponding to the value range is filled into the target area of ​​the test diagram; wherein the value range includes at least three, and different value ranges correspond to different filling colors. For example, if the number of bit errors is within (0,255), the target area is filled with yellow; if the number of bit errors is 0, the target area is filled with green; if the number of bit errors is 255, the target area is filled with red.

[0058] Here, "plurality" means two or more.

[0059] To summarize, the hardware testing method provided in the embodiment of the present application divides the original test graph into multiple sub-test graphs, each sub-test graph includes a×b areas, and generates a sub-graph state array to record the test status of the areas in the sub-test graph. By reusing the sub-graph state array, the test processing of the hardware to be tested is performed separately for each sub-test graph in one or part of the multiple sub-test graphs. Compared with recording the test status of the entire test graph, the memory required to record the test status of the sub-test graph is significantly reduced, thereby greatly reducing the memory requirement during hardware testing.

[0060] In one possible implementation, based on Figure 2 The embodiment shown also uses an edge state array to record the test states of edge areas in multiple sub-test images. After a sub-test image is tested, the sub-test image for the next test is determined based on the edge state array. The edge state array is described in three parts below.

[0061] Generation of edge state array

[0062] The computer also generates an edge state array, wherein the edge state array is used to record the test state of the edge area in at least two sub-test images. The edge state array includes two arrays, namely a third array and a fourth array, wherein the third array is used to record the tested state of the edge area in at least two sub-test images, and the fourth array is used to record the state to be tested of the edge area in at least two sub-test images. Optionally, the edge state array can be in the form of a matrix, such as a Boolean matrix.

[0063] The computer may generate an edge state array according to the size of the sub-test image; or, generate an edge state array according to the number of edge regions included in the sub-test image. Optionally, the number of elements contained in each array in the edge state array is the same as the sum of the edge regions in at least two sub-test images. For example, if the sub-test image includes a×b regions, then the sub-test image uses (2a+2b-4)×2 elements in the edge state array accordingly, and if the sub-test image includes m×n regions, then the edge state array includes (2a+2b-4)×2×m×n elements. Alternatively, the number of elements used in each array by each sub-test image is 4 more than the number of edge regions in the sub-test image. For example, if the sub-test image includes a×b regions, then the sub-test image uses (2a+2b)×2 elements in the edge state array accordingly, and if the sub-test image includes m×n regions, then the edge state array includes (2a+2b)×2×m×n elements.

[0064] Optionally, the edge state array may be in the form of a matrix, for example, the edge state array may be a Boolean matrix. For example, each array in the edge state array may be a Boolean matrix of size m×n×(2a+2b).

[0065] The edge state array can be used to record the test states of the edge regions of all sub-test images. In the embodiments provided in the present application, the edge state array is used to record the test states of the edge regions of one or a part of the sub-test images.

[0066] The subgraph state array and the edge state array may be generated in a sequential order or simultaneously, and there is no restriction on the generation order of the two.

[0067] Update of edge state array

[0068] After testing the hardware to be tested according to the test parameters corresponding to the target area, it is determined that the target area is located at the edge of the sub-test graph, and the test state of the target area in the edge state array is updated to tested.

[0069] That is, during the update process of the test status, it is also necessary to determine whether the target area is located at the edge of the sub-test image. If the target area is located at the edge of the sub-test image, the test status of the target area in the edge status array is updated. If the target area does not belong to the edge of the sub-test image, the test status of the target area is not updated in the edge status array.

[0070] For the update of the edge status array, if the test status of the target area is updated to tested, the value representing the test status of the target area in the third array is updated from the fifth value to the sixth value, and the value representing the test status of the target area in the fourth array is updated from the seventh value to the eighth value.

[0071] Regarding the test status update of the edge area, if the test status of an edge area is tested, the value of the test status of the edge area in the third array is 1, and the value of the test status of the edge area in the fourth array is 0; if the test status of an edge area is to be tested, the value of the test status of the edge area in the third array is 0, and the test status of the edge area in the fourth array is 1; if the test status of an edge area is untested, the value of the test status of the edge area in the third array is 0, and the test status of the edge area in the fourth array is 0.

[0072] After the test, the test status of the target area is updated. If the target area is the edge area of ​​the sub-test image, the value representing the test status of the target area in the third array is updated from 0 to 1, and the value representing the test status of the target area in the fourth array is updated from 1 to 0.

[0073] Optionally, after determining that the area to be tested is located at the edge of any sub-test image, the computer updates the test status of the area to be tested in the edge status array, that is, if the area to be tested is located at the edge of any sub-test image in at least two sub-test images, the test status of the area to be tested in the edge status array is marked as to be tested, wherein the area to be tested is an untested area adjacent to the target area in the test image.

[0074] The area to be tested may be located at the edge of the sub-test image under test, or may be located at the edge of other sub-test images adjacent to the sub-test image. If the area to be tested is located at the edge of the sub-test image under test, the test status of the area to be tested in the sub-image state array and the edge state array needs to be updated to be tested; if the area to be tested is located at the edge of other sub-test images adjacent to the sub-test image, the test status of the area to be tested in the edge state array needs to be updated to be tested. If the area to be tested does not belong to the edge of any sub-test image, the test status of the area to be tested in the edge state array will not be updated.

[0075] If the test status of the area to be tested is updated to under test, the value representing the test status of the area to be tested in the fourth array is updated from the eighth value to the seventh value, for example, the value representing the test status of the edge area in the fourth array is updated from 0 to 1.

[0076] If there is an update of the edge state array, it can be executed simultaneously or sequentially with the update of the subgraph state array, and the execution order of the two is not limited.

[0077] Determine the subtest graph for the next test based on the edge state array

[0078] After completing the test of each target area in the sub-test image, determine the sub-test image for the next test according to the edge area to be tested in the edge state array corresponding to the test state; update the test state of the edge area of ​​the sub-test image for the next test from the edge state array to the initialized sub-image state array, and perform the test of each target area in the sub-test image for the next test.

[0079] For example, when there is a seventh value in the fourth array, the sub-test graph where the area corresponding to the test state having the value of the seventh value is located is determined as the sub-test graph for the next test; and the value of the test state of the edge area of ​​the sub-test graph for the next test is copied from the fourth array to the initialized second array.

[0080] If the sub-image state array indicates that there is no area to be tested in the sub-test image, the test of each target area in the sub-test image is completed, and then the sub-test image with the edge area to be tested is determined as the sub-test image for the next test according to the edge state array, and the test state of the edge area of ​​the sub-test image for the next test is updated from the edge state array to the corresponding position in the initialized sub-image state array, and then the process returns to step 330, and the sub-test image for the next test is determined again based on the edge state array until the edge state array indicates that there is no sub-test image to be tested, and the hardware test corresponding to one or more sub-test images is completed.

[0081] To summarize, the hardware testing method provided in the embodiment of the present application divides the original test graph into multiple sub-test graphs, each sub-test graph includes a×b areas, and generates a sub-graph state array to record the test status of the areas in the sub-test graph. After each test of a sub-test graph is completed, the sub-graph state array is initialized, and the initialized sub-graph state array is used to continue to participate in the test of the next sub-test graph. By reusing the sub-graph state array, the test processing of one or more sub-test graphs is completed. Compared with recording the test status of the entire test graph, the memory required to record the test status of the sub-test graph is significantly reduced. Therefore, the generation and reuse of the sub-graph state array can greatly reduce the memory requirements during hardware testing.

[0082] The method also generates an edge state array to record the test states of edge areas of multiple sub-test images. In the process of selecting a test area, a test area may be selected from edge areas of other sub-test images adjacent to the sub-test image, and the test state of the test area is updated to the edge state array. After completing the test of the sub-test image, the test state existing in the edge state array can be used to accurately locate the sub-test image for the next test, without the need to test the sub-test image where the target area does not exist, thereby reducing the workload of hardware testing and improving the speed of hardware testing.

[0083] Figure 3 FIG. 1 is a flowchart of a hardware testing method according to an embodiment of the present application. Figure 3 As shown, an exemplary description is given of one of the hardware testing methods provided in the above embodiment, and the steps are as follows:

[0084] Step 301, start.

[0085] Step 302, partition size: (a×b); total size of the test image: (a×m)×(b×n); number of sub-test images: (m×n).

[0086] The pre-set partition size is (a×b) and the total size of the test image is (a×m)×(b×n). The computer divides the test image with a total size of (a×m)×(b×n) into (m×n) sub-test images according to the partition size (a×b). The partition size refers to the size used to divide the sub-test images.

[0087] Among them, (a×b) means a rows×b columns; (m×n) means m rows×n columns; (a×m)×(b×n) means (a×m) rows×(b×n) columns.

[0088] Step 303, initialize the following Boolean arrays to all False: visited; to_visit; edge_visited; edge_to_visit.

[0089] In the Boolean array, the value 0 represents False, and the value 1 represents True. Generate and initialize the following Boolean arrays: visited; to_visit; edge_visited; edge_to_visit; where visited refers to the first array; to_visit refers to the second array; edge_visited refers to the third array; and edge_to_visit refers to the fourth array.

[0090] The Boolean arrays are generated based on the size of the subtest graph, visited and to_visit are Boolean matrices of size (a×b), and edge_visited and edge_to_visit are Boolean matrices of size m×n×(2a+2b).

[0091] Step 304: obtain the center point (V0, T0) of the test graph through I / O Training.

[0092] The computer determines the center point (V0, T0) from the test image through input / output (I / O) training.

[0093] In this embodiment, the test variables Vref and Timing are used as examples. One area in the test graph is represented by one grid. In the test graph set according to the test variables, each grid corresponds to a working point, and one working point corresponds to a set of test parameters (Vref, Timing). The center point refers to the working point located at the center of the test graph.

[0094] Step 305, starting from (V0, T0) and moving in one direction, each time moving one grid, running a test for its corresponding test parameters until the test result is within the range of interest, and taking the last tested working point (V, T) as the initial working point.

[0095] The range of interest is the range of values. Start from (V0, T0) and move in one direction, which can be up, down, left, or right. For example, start from (V0, T0) and move downward. Each time you move down one grid, run a test for the corresponding test parameter until the test result is within (0, 255). The last tested working point (V, T) is used as the initial working point.

[0096] Step 306, calculating the sub-test graph where the initial working point is located.

[0097] The test pattern is divided into m rows × n columns of sub-test patterns, and the initial working point is located at the position (ri, rj) in the above m × n sub-test pattern array. The floor function is used to calculate (ri, rj):

[0098] ri = floor(V / a);

[0099] rj = floor(T / b);

[0100] Among them, the values ​​of i and j are both positive integers.

[0101] Step 307, set visited to all False; set to_visit to all False.

[0102] Before the test of each sub-test graph begins, visited and to_visit are initialized and both visited and to_visit are set to all False.

[0103] Step 308, copy the 2 (a+b) values ​​in edge_to_visit[ri,rj] to the upper, lower, left and right edges of to_visit.

[0104] Among them, edge_to_visit[ri,rj] represents the address of the test state of the edge area of ​​the sub-test graph (ri,rj) in edge_to_visit. The relationship of copying 2 (a+b) values ​​from edge_to_visit[ri,rj] to to_visit is as follows:

[0105] Upper edge: to_visit[0,:] = edge_to_visit[ri,rj,2a:2a+b];

[0106] Lower edge: to_visit[a-1,:] = edge_to_visit[ri,rj,2a+b:2a+2b];

[0107] Left edge: to_visit[:,0] = edge_to_visit[ri,rj,:a];

[0108] Right edge: to_visit[:,b-1] = edge_to_visit[ri,rj,a:2a];

[0109] Where to_visit is a two-dimensional Boolean matrix of a×b, to_visit[0,:] represents the b positions of the upper edge with a starting position of 0 in to_visit, to_visit[a-1,:] represents the b positions of the lower edge with a starting position of (a-1) in to_visit, to_visit[:,0] represents the a positions of the left edge with a terminal position of 0 in to_visit, and to_visit[:,b-1] represents the a positions of the right edge with a terminal position of (b-1) in to_visit; edge_to_visit is a three-dimensional Boolean matrix of m×n×2(a+b), edge_to_visit[ri,rj,:a] represents the position of the right edge with a terminal position of (b-1) in edge_to_visit. ri,rj), edge_to_visit[ri,rj,a:2a] represents the positions a to (2a-1) among the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit, edge_to_visit[ri,rj,2a:2a+b] represents the positions (2a-1) to (2a+b-1) among the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit, and edge_to_visit[ri,rj,2a+b:2a+2b] represents the positions (2a+b) to (2a+2b-1) among the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit.

[0110] Step 309, calculating the position (ci, cj) of the working point (V, T) in the sub-test graph.

[0111] The sub-test graph includes a rows and b columns, and it is determined that the working point (V, T) is located at the position (ci, cj) in the above a×b sub-test graph.

[0112] Use the modulo function to calculate (ci,cj):

[0113] ci=V mod a;

[0114] cj=T mod b.

[0115] Step 310, configure the I / O operating point to (V, T), run the test and record the results.

[0116] The computer configures the test parameters of the I / O operation as V and T, runs the test, and records the results of the test on the hardware under test, such as the number of error codes.

[0117] Step 311, update visited and to_visit.

[0118] Update the values at the position (ci, cj) in to_visit and visited:

[0119] to_visit[ci,cj] = False;

[0120] visited[ci,cj] = True.

[0121] Step 312, execute Subroutine 1: update edge_to_visit[ci,cj] and edge_visited[ci,cj].

[0122] Execute Subroutine 1 to determine the position of the operating point (V, T) in the sub-test graph. If the operating point (V, T) is located on the edge of the sub-test graph, update edge_to_visit and edge_visited. As Figure 4 shown, the update process of Subroutine 1 is as follows:

[0123] Judge the value of ci;

[0124] If ci = 0, it means that the operating point (V, T) is on the upper edge of the sub-test graph, and update edge_to_visit and edge_visited:

[0125] edge_to_visit[ri,rj,2a+cj] = False; edge_visited[ri,rj,2a+cj] = Ture;

[0126] If ci = a - 1, it means that the operating point (V, T) is on the lower edge of the sub-test graph, and update edge_to_visit and edge_visited:

[0127] edge_to_visit[ri,rj,2a+b+cj] = False; edge_visited[ri,rj,2a+b+cj] = Ture;

[0128] If 0 < ci < a - 1, then judge the value of cj;

[0129] If cj = 0, it indicates the left edge of the sub-test pattern at the working point (V, T), and update edge_to_visit and edge_visited:

[0130] edge_to_visit[ri,rj,ci] = False; edge_visited[ri,rj,ci] = True;

[0131] If cj = b - 1, it indicates the right edge of the sub-test pattern at the working point (V, T), and update edge_to_visit and edge_visited:

[0132] edge_to_visit[ri,rj,a + ci] = False; edge_visited[ri,rj,a + ci] = True;

[0133] If 0 < cj < b - 1, it indicates that the working point (V, T) is not located at the edge of the sub-test pattern.

[0134] Step 313, determine whether the test result is within the range of interest.

[0135] If the test result is within the range of interest, execute Step 314; if not, that is, the test result is not within the range of interest, execute Step 315. For example, determine whether the number of error codes is within (0, 255). If so, execute Step 314; if not, execute Step 315.

[0136] Step 314, execute Subroutine 2: update to_visit and edge_to_visit.

[0137] Execute Subroutine 2 to determine whether there are still untested areas in the upper, lower, left, and right regions adjacent to (ci, cj). If there are still such areas, mark them as to be tested. As Figure 5 shown, the update process of Subroutine 2 is as follows:

[0138] · Determine the value of ci.

[0139] 1) If ci = 0, it indicates that the working point (V, T) is located at the upper edge of the sub-test pattern. Mark the area (ci + 1, cj) below (ci, cj) as to be tested, that is, update to_visit:

[0140] to_visit[ci + 1, cj] = ~visited[ci + 1, cj], where "~" represents the negation operation. For example, if visited[ci + 1, cj] = False, then ~visited[ci + 1, cj] = True, and after update, to_visit[ci + 1, cj] = True. Conversely, if visited[ci + 1, cj] = True, then ~visited[ci + 1, cj] = False, and after update, to_visit[ci + 1, cj] = False;

[0141] After updating to_visit, determine whether ri > 0;

[0142] If ri > 0, it means that there is a sub-test graph (ri - 1, rj) above the sub-test graph (ri, rj) in the sub-test graph array. Update the test status of the area adjacent to (ci, cj) and above (ci, cj) in the sub-test graph (ri - 1, rj) in edge_to_visit:

[0143] edge_to_visit[ri - 1, rj, k] = ~edge_visited[ri - 1, rj, k], k = 2a + b + cj;

[0144] If ri > 0 is not true, it means that the sub-test graph (ri, rj) is located at the upper edge of the sub-test graph array, and execute the step of "judging the value of cj".

[0145] 2) If ci = a - 1, it means that the working point (V, T) is located at the lower edge of the sub-test graph. Mark the area (ci - 1, cj) above (ci, cj) as to be tested, that is, update to_visit as:

[0146] to_visit[ci - 1, cj] = ~visited[ci - 1, cj];

[0147] After updating to_visit, determine whether ri < m - 1;

[0148] If ri < m - 1, it means that there is a sub-test graph (ri + 1, rj) below the sub-test graph (ri, rj) in the sub-test graph array. Update the test status of the area adjacent to (ci, cj) and below (ci, cj) in the sub-test graph (ri + 1, rj) in edge_to_visit:

[0149] edge_to_visit[ri + 1, rj, k] = ~edge_visited[ri + 1, rj, k], k = 2a + cj;

[0150] If ri < m - 1 does not hold, it means that the sub-test pattern (ri, rj) is located at the lower edge of the sub-test pattern array, and the step of "judging the value of cj" is executed.

[0151] 3) If 0 < ci < a - 1, it means that the operating point (V, T) is not located at the upper or lower edge position of the sub-test pattern. Mark the area (ci - 1, cj) above (ci, cj) and the area (ci + 1, cj) below it as to be tested. That is, update to_visit as follows:

[0152] to_visit[ci - 1, cj] = ~visited[ci - 1, cj]; to_visit[ci + 1, cj] = ~visited[ci + 1, cj];

[0153] After updating to_visit, execute the step of "judging the value of cj".

[0154] · Judge the value of cj.

[0155] 1) If cj = 0, it means that the operating point (V, T) is located at the left edge of the sub-test pattern. Mark the area (ci, cj + 1) on the right side of (ci, cj) as to be tested. That is, update to_visit:

[0156] to_visit[ci, cj + 1] = ~visited[ci, cj + 1];

[0157] After updating to_visit, judge whether rj > 0;

[0158] If rj > 0, it means that there is a sub-test pattern (ri, rj - 1) on the left side of the sub-test pattern (ri, rj) in the sub-test pattern array. Update the test status of the area adjacent to (ci, cj) and on the left side of (ci, cj) in the sub-test pattern (ri, rj - 1) in edge_to_visit:

[0159] edge_to_visit[ri, rj - 1, k] = ~edge_visited[ri, rj - 1, k], where k = a + ci;

[0160] If ri > 0 does not hold, it means that the sub-test pattern (ri, rj) is located at the left edge of the sub-test pattern array, and execute step 315.

[0161] 2) If cj = b - 1, it means that the operating point (V, T) is located at the right edge of the sub-test pattern. Mark the area (ci, cj - 1) on the left side of (ci, cj) as to be tested. That is, update to_visit:

[0162] to_visit[ci, cj - 1] = ~visited[ci, cj - 1];

[0163] After updating to_visit, determine whether rj < n - 1;

[0164] If rj < n - 1, it means that there is a sub-test graph (ri, rj + 1) on the right side of the sub-test graph (ri, rj) in the sub-test graph array. Update the test status of the area adjacent to (ci, cj) and on the right side of (ci, cj) in the sub-test graph (ri, rj + 1) in edge_to_visit:

[0165] edge_to_visit[ri, rj + 1, k] = ~edge_visited[ri, rj + 1, k], k = ci;

[0166] If ri is not < n - 1, it means that the sub-test graph (ri, rj) is located at the right edge of the sub-test graph array, and execute step 315.

[0167] 3) If 0 < cj < b - 1, it means that the working point (V, T) is not located at the left or right edge position of the sub-test graph. Mark the left area (ci, cj - 1) and the right area (ci, cj + 1) of (ci, cj) as to be tested, that is, update to_visit as:

[0168] to_visit[ci, cj - 1] = ~visited[ci, cj - 1]; to_visit[ci, cj + 1] = ~visited[ci, cj + 1];

[0169] After updating to_visit, execute step 315.

[0170] Step 315, determine whether to_visit is all False.

[0171] After completing the test of the working point (V, T), determine whether to_visit is all False, that is, determine whether there is still an area to be tested in the sub-test graph. If so, execute step 318; if not, execute step 316.

[0172] Step 316, find a new set of (ci, cj) such that to_visit[ci, cj] = True and visited[ci, cj] = False.

[0173] Redetermine a (ci, cj) in the sub-test graph. This newly determined (ci, cj) has to_visit[ci, cj] = True and visited[ci, cj] = False, that is, this is an area to be tested.

[0174] Step 317, calculate the new working point corresponding to (ci, cj).

[0175] According to the re-determined working point corresponding to (ci, cj) in the test diagram, the calculation method is as follows:

[0176] v = ri × a + ci;

[0177] t=rj×b+cj.

[0178] After executing step 317 , return to step 310 .

[0179] Step 318, determine whether edge_to_visit is all False.

[0180] Determine whether edge_to_visit is all False, that is, determine whether there is a sub-test graph to be tested. If edge_to_visit is all False, it means there is no sub-test graph to be tested, and execute step 320; if not, that is, edge_to_visit is not all False, it means there is a sub-test graph to be tested, and execute step 319.

[0181] Step 319, find a new set of (ri, rj) so that edge_to_visit[ri, rj] is not all False.

[0182] A sub-test graph (ri, rj) is re-determined in the sub-test graph. In the re-determined sub-test graph (ri, rj), not all edge_to_visit[ri, rj] are False, that is, this is a sub-test graph to be tested.

[0183] like Figure 6As shown in the figure, the test run is illustrated. First, for the sub-test graph (ri, rj) on the right side of the demarcation line, the hardware under test is tested. The test is run at the operating point 601, and the number of error codes (errcnt) is recorded as 64. The status of the operating point 601 is marked as measured in this area. If 0 < errcnt = 64 < the maximum number of error codes (err_max), the operating points on the lower three sides (left, lower, and right) of the operating point 601 are marked as to be tested in this area. Move one grid to the left, run the test at the operating point 602, record the number of error codes as 133, and mark the status of the operating point 602 as measured in this area. If 0 < errcnt = 133 < err_max, the operating points on the lower left two sides of the operating point 602 are marked as to be tested in this area. Continue to move one grid to the left, run the test at the operating point 603, record the number of error codes as 169, and mark the status of the operating point 603 as measured in this area. If 0 < errcnt = 169 < err_max, the operating point 603 is located at the left edge of the sub-test graph (ri, rj), the operating points on the upper and lower sides of the operating point 603 are marked as to be tested in this area, and the operating points on the left side of the operating point 603 are marked as to be tested at the edge. Move one grid down, run the test at the operating point 604, record the number of error codes as 194, and mark the status of the operating point 604 as measured in this area. If 0 < errcnt = 194 < err_max, the operating point 604 is located at the left edge of the sub-test graph (ri, rj), the operating point on the lower side of the operating point 604 is marked as to be tested in this area, and the operating points on the left side of the operating point 604 are marked as to be tested at the edge;... until the measurement of the sub-test graph (ri, rj) is completed. According to the marking of to be tested at the edge, the measurement of the next sub-test graph (ri, rj - 1) is started. The test is run starting from the operating point 605, record the number of error codes as 209, mark the status of the operating point 605 as measured in this area. If 0 < errcnt = 209 < err_max, the operating point 605 is located at the right edge of the sub-test graph (ri, rj - 1), the operating points on the upper, lower, and left three sides of the operating point 605 are marked as to be tested in this area,... until the measurement of the sub-test graph (ri, rj - 1) is completed. Again, according to the marking of to be tested at the edge, the measurement of the next sub-test is started, and so on. As Figure 7 , after the measurement of the sub-test graph 701 is completed, the measurement of the sub-test graph 702 is started according to the marking of to be tested at the edge, and then the tests of the sub-test graph 703, sub-test graph 704, sub-test graph 705, and sub-test graph 706 are completed in sequence until the measurement of the test graph is completed. Among them, marking measured in this area and to be tested in this area is to mark the test status in the sub-graph status array; marking to be tested at the edge is to mark the test status in the edge status array.

[0184] Step 320, end.

[0185] The test result diagram in this embodiment is an eye diagram. If an eye diagram of (a×m)×(b×n) needs to be generated, the sub-test diagram is divided according to the size of a×b. For the memory requirement, visited requires a×b / 8 (Bytes), to_visit requires a×b / 8 (Bytes), edge_to_visit requires m×n×(2×a+2×b) / 8 (Bytes), and edge_visited requires m×n×(2×a+2×b) / 8 (Bytes). As shown in Table 1 below, different eye diagram sizes and different partition sizes are combined to provide the memory required for testing the hardware to be tested. If the eye diagram size is 128×128 and the partition size is 32×32, the total memory required for testing is 0.75 kB (kilobytes). Among them, Bytes is bytes, and 1 kB=1024 Bytes. As shown in Table 1, if the partition size is 32×32, then Shmoo measurements below 128×128 can all be satisfied by 1kB of memory.

[0186] Table 1

[0187]

[0188] The hardware testing method provided in the embodiment of the present application reduces the memory requirement required for hardware testing, and can solve the problem that the Basic Input / Output System (BIOS) resources are limited and the memory usage needs to be limited to within 1kB. For a 128×128 eye diagram, 34kB of memory is required when Shmoo measurement is performed in a recursive manner, and 4kB of memory is required when Shmoo measurement is performed in a non-recursive manner, both of which cannot meet the memory requirement.

[0189] Hardware test equipment

[0190] Corresponding to the above method embodiment, Figure 8 FIG. 1 shows a schematic diagram of a hardware testing device. Figure 8 As shown, the hardware test device includes:

[0191] A division module 801 is used to divide the test image into at least two sub-test images, where the sub-test images include a×b areas, where a and b are both integers greater than 2;

[0192] A generating module 802 is used to generate a sub-image state array, wherein the sub-image state array is used to record the test state of the area in the sub-test image;

[0193] The processing module 803 is used to perform the following processing on one or more sub-test images in at least two sub-test images to obtain a test result image corresponding to the hardware to be tested: determine the target area from the sub-test image according to the sub-image state array; test the hardware to be tested according to the test parameters corresponding to the target area to obtain the test result, and update the sub-image state array; fill the target area in the test image according to the test result; after completing the test of each target area in the sub-test image, initialize the sub-image state array.

[0194] In one possible implementation, the processing module 803 updates the sub-image state array, including: updating the test state of the target area in the sub-image state array to tested; if the number of bit errors indicated by the test result is within a value range, marking the test state of the untested area adjacent to the target area as to be tested; wherein the target area is determined from the area marked as to be tested in the sub-test image.

[0195] In a possible implementation, the subgraph state array includes a first array and a second array;

[0196] The processing module 803 updates the test status of the target area to tested in the sub-graph status array, including: updating the value representing the test status of the target area in the first array from the first value to the second value, and updating the value representing the test status of the target area in the second array from the third value to the fourth value;

[0197] The processing module 803 marks the test status of the untested area adjacent to the target area as to be tested, including: updating the value representing the test status of the to-be-tested area in the second array from the fourth value to the third value, wherein the to-be-tested area is the untested area adjacent to the target area in the test image.

[0198] In a possible implementation, the processing module 803 determines the target area from the sub-test image according to the sub-image state array, including: according to the second array, determining the areas in the sub-test image whose values ​​of the test state are third values ​​as the target areas.

[0199] In a possible implementation, the generating module 802 is further used to generate an edge state array, wherein the edge state array is used to record the test states of the edge areas in at least two sub-test images;

[0200] The processing module 803 is further used to determine that the target area is located at the edge of the sub-test graph after testing the hardware to be tested according to the test parameters corresponding to the target area, and update the test status of the target area in the edge status array to tested.

[0201] In one possible implementation, the edge state array includes a third array and a fourth array;

[0202] The processing module 803 updates the to-be-tested state of the target area in the edge state array to tested, including: updating the value representing the test state of the target area in the third array from the fifth value to the sixth value, and updating the value representing the test state of the target area in the fourth array from the seventh value to the eighth value.

[0203] In a possible implementation, the processing module 803 is further used to mark the test state of the area to be tested in the edge state array as to be tested if the area to be tested is located at the edge of any sub-test image in at least two sub-test images, wherein the area to be tested is an untested area adjacent to the target area in the test image.

[0204] In a possible implementation, the processing module 803 marks the test state of the area to be tested in the edge state array as to be tested, including: updating the value representing the test state of the area to be tested in the fourth array from the eighth value to the seventh value.

[0205] In one possible implementation, the processing module 803 is further used to determine the sub-test image for the next test after completing the test of each target area in the sub-test image according to the edge area to be tested in the edge state array corresponding to the test state; update the test state of the edge area of ​​the sub-test image for the next test from the edge state array to the initialized sub-image state array, and perform the test of each target area in the sub-test image for the next test.

[0206] In a possible implementation manner, the test result diagram is an eye diagram.

[0207] In one possible implementation, the processing module 803 performs filling processing on the target area of ​​the test image according to the test results, including: filling the target area of ​​the test image with the number of bit errors indicated by the test results; or, if the number of bit errors indicated by the test results is within a value range, filling the target area of ​​the test image with a color corresponding to the value range, wherein the value range includes at least three, and different value ranges correspond to different filling colors.

[0208] It should be noted that the hardware testing device of this embodiment is used to implement the corresponding hardware testing method in the aforementioned method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0209] Electronic devices

[0210] Fig. 9 This is a schematic block diagram of an electronic device provided in an embodiment of the present application. The specific embodiment of the present application does not limit the specific implementation of the electronic device. Fig. 9As shown, the electronic device may include: a processor (processor) 902, a communication interface (Communications Interface) 904, a memory (memory) 906, and a communication bus 908. Among them:

[0211] The processor 902 , the communication interface 904 , and the memory 906 communicate with each other via a communication bus 908 .

[0212] The communication interface 904 is used to communicate with other electronic devices or servers.

[0213] The processor 902 is used to execute the program 910, and specifically can execute the relevant steps in any of the aforementioned hardware testing method embodiments.

[0214] Specifically, the program 910 may include program codes, which include computer operation instructions.

[0215] The processor 902 may be a central processing unit (CPU), or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs; or may be processors of different types, such as one or more CPUs and one or more ASICs.

[0216] RISC-V is an open source instruction set architecture based on the Reduced Instruction Set (RISC) principle. It can be applied to various aspects such as single-chip microcomputers and FPGA chips. Specifically, it can be applied to the fields of IoT security, industrial control, mobile phones, personal computers, etc., and because it is designed with small, fast, and low-power realities in mind, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems. With the rise of artificial intelligence Internet of Things (AIoT), the RISC-V instruction set architecture has also received more and more attention and support, and is expected to become the next generation of widely used CPU architecture.

[0217] The computer operation instructions in the embodiment of the present application may be computer operation instructions based on the RISC-V instruction set architecture, and correspondingly, the processor 902 may be designed based on the RISC-V instruction set. Specifically, the chip of the processor in the electronic device provided in the embodiment of the present application may be a chip designed with the RISC-V instruction set, and the chip may execute executable code based on the configured instructions, thereby implementing the hardware testing method in the above embodiment.

[0218] The memory 906 is used to store the program 910. The memory 906 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0219] The program 910 may be specifically used to enable the processor 902 to execute the hardware testing method in any of the aforementioned embodiments.

[0220] The specific implementation of each step in program 910 can refer to the corresponding description of the corresponding steps and units in any of the aforementioned hardware testing method embodiments, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the aforementioned method embodiments, which will not be repeated here.

[0221] Computer storage media

[0222] The present application also provides a computer-readable storage medium storing instructions for causing a machine to execute the hardware testing method as described herein. Specifically, a system or device equipped with a storage medium may be provided, on which a software program code implementing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or device is enabled to read and execute the program code stored in the storage medium.

[0223] In this case, the program code read from the storage medium itself can implement the function of any one of the above embodiments, so the program code and the storage medium storing the program code constitute part of the present application.

[0224] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0225] Computer program product

[0226] An embodiment of the present application also provides a computer program product, including computer instructions, which instruct a computing device to perform any corresponding operation in the above-mentioned multiple method embodiments.

[0227] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0228] The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a special-purpose processor or programmable or special-purpose hardware (such as an ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a special-purpose computer for executing the method shown here.

[0229] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0230] The above implementation methods are only used to illustrate the embodiments of the present application, and are not limitations on the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be limited by the claims.

Claims

1. A hardware testing method, the method comprising: Divide the test image into at least two sub-test images, each sub-test image including a×b areas, where a and b are both integers equal to or greater than 2; Generate a sub-image state array, wherein the sub-image state array is used to record the test state of the area in the sub-test image; The following processing is performed on one or more sub-test images among the at least two sub-test images to obtain a test result image corresponding to the hardware to be tested: determine the target area from the sub-test image according to the sub-image state array; test the hardware to be tested according to the test parameters corresponding to the target area to obtain the test result, and update the sub-image state array; fill the target area in the test image according to the test result; after completing the test of each target area in the sub-test image, initialize the sub-image state array.

2. The method according to claim 1, wherein: The updating of the sub-graph state array comprises: updating the test status of the target area in the sub-image status array to tested; If the number of bit errors indicated by the test result is within the value range, marking the test status of the untested area adjacent to the target area as pending test; The target area is determined from the area marked as to-be-tested in the sub-test image.

3. The method according to claim 2, wherein: The sub-graph state array includes a first array and a second array; The updating the test state of the target area in the sub-image state array to tested comprises: updating the value representing the test state of the target area in the first array from a first value to a second value, and updating the value representing the test state of the target area in the second array from a third value to a fourth value; Marking the test status of the untested area adjacent to the target area as to be tested includes: updating the value representing the test status of the area to be tested in the second array from the fourth value to the third value, wherein the area to be tested is the untested area adjacent to the target area in the test image.

4. The method according to claim 3, wherein: The step of determining a target area from the sub-test image according to the sub-image state array comprises: According to the second array, the regions in the sub-test graph whose values ​​of the corresponding test states are the third values ​​are respectively determined as the target regions.

5. The method according to any one of claims 2 to 4, wherein: The method further comprises: Generate an edge state array, wherein the edge state array is used to record the test states of the edge areas in the at least two sub-test images; After testing the hardware to be tested according to the test parameters corresponding to the target area, it is determined that the target area is located at the edge of the sub-test graph, and the test state of the target area in the edge state array is updated to tested.

6. The method according to claim 5, wherein: The edge state array includes a third array and a fourth array; The updating the to-be-tested state of the target area in the edge state array to tested includes: The value representing the test status of the target area in the third array is updated from the fifth value to the sixth value, and the value representing the test status of the target area in the fourth array is updated from the seventh value to the eighth value.

7. The method according to claim 6, wherein: The method further comprises: If the area to be tested is located at the edge of any of the at least two sub-test images, the test state of the area to be tested in the edge state array is marked as to be tested, wherein the area to be tested is an untested area in the test image adjacent to the target area.

8. The method according to claim 7, wherein: The step of marking the test state of the to-be-tested area in the edge state array as to-be-tested comprises: The value representing the test status of the area to be tested in the fourth array is updated from the eighth value to the seventh value.

9. The method according to claim 5, wherein: The method further comprises: After completing the test of each target area in the sub-test image, determining the sub-test image to be tested next according to the edge area to be tested corresponding to the test state in the edge state array; The test status of the edge area of ​​the sub-test graph of the next test is updated from the edge status array to the initialized sub-graph status array, and the test of each target area in the sub-test graph of the next test is performed.

10. The method according to any one of claims 1 to 4, wherein: The filling process is performed on the target area of ​​the test image according to the test result, including: Filling the number of bit errors indicated by the test result into the target area of ​​the test pattern; or, If the number of bit errors indicated by the test result is within a value range, the target area of ​​the test chart is filled with a color corresponding to the value range, wherein the value range includes at least three values, and different value ranges correspond to different filling colors.

11. A hardware testing device, comprising: A division module, used to divide the test image into at least two sub-test images, wherein the sub-test images include a×b areas, where a and b are both integers equal to or greater than 2; A generating module, used for generating a sub-image state array, wherein the sub-image state array is used for recording the test state of the area in the sub-test image; A processing module is used to perform the following processing on one or more sub-test images of the at least two sub-test images, respectively, to obtain a test result image corresponding to the hardware to be tested: determining a target area from the sub-test image according to the sub-image state array; testing the hardware to be tested according to the test parameters corresponding to the target area, obtaining a test result, and updating the sub-image state array; filling the target area in the test image according to the test result; and initializing the sub-image state array after completing the test of each target area in the sub-test image.

12. An electronic device comprising: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute an operation corresponding to the hardware testing method as claimed in any one of claims 1 to 10.

13. A computer storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the hardware testing method according to any one of claims 1 to 10 is implemented.

14. A computer program product, comprising computer instructions, wherein the computer instructions instruct a computing device to execute the hardware testing method according to any one of claims 1 to 10.

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