Memory system and operation method thereof, electronic device and operation method thereof

Abstract

The present disclosure relates to a memory system and an operation method thereof, an electronic device and an operation method thereof. The memory system comprises: a storage device and a volatile memory device; wherein the storage device comprises a non-volatile memory device, a first memory controller coupled to the non-volatile memory device, and a first interface; the first memory controller is configured to control the non-volatile memory device; the volatile memory device comprises a second interface; the second interface is coupled to the first interface so that the storage device and the volatile memory device can interact.

Description

Technical Field

[0001] The present disclosure relates to the field of computer communications, and in particular to a memory system and an operating method thereof, an electronic device and an operating method thereof. Background Art

[0002] In the related art, the interaction between the host and the volatile memory device can be realized by the controller of the volatile memory device in the host, and the interaction between the host and the non-volatile memory device can be realized by the controller of the non-volatile memory device in the host. However, when the controller of the volatile memory device in the host is turned off, the volatile memory device cannot be accessed, resulting in a waste of resources. How to improve the utilization rate of the volatile memory device has become an urgent problem to be solved. Summary of the invention

[0003] To overcome the problems existing in the related art, the present disclosure provides a memory system and an operating method thereof, an electronic device and an operating method thereof.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0005] Storage device and volatile memory device; wherein,

[0006] The storage device includes a non-volatile memory device, a first memory controller coupled to the non-volatile memory device, and a first interface; the first memory controller is configured to control the non-volatile memory device; the volatile memory device includes a second interface; the second interface is coupled to the first interface so that the storage device can interact with the volatile memory device.

[0007] In some embodiments, the volatile memory device includes a double data rate synchronous dynamic random access memory; the storage device includes a universal flash memory or an embedded multimedia card.

[0008] In some embodiments, the storage device and the volatile memory device are packaged on the same substrate.

[0009] In some embodiments, the first interface includes a first clock signal pin area, a first power signal pin area, a first command address signal pin area, and a first data pin area; the second interface includes a second clock signal pin area, a second power signal pin area, a second command address signal pin area, and a second data pin area;

[0010] The first clock signal pin area is coupled to the second clock signal pin area; the first power signal pin area is coupled to the second power signal pin area; the first command address signal pin area is coupled to the second command address signal pin area; and the first data pin area is coupled to the second data pin area.

[0011] According to a second aspect of an embodiment of the present disclosure, an electronic device is provided, comprising a memory system as described in any of the above embodiments, and a host; the host comprises a second memory controller and a third memory controller, the second memory controller is coupled to the storage device, and the third memory controller is coupled to the volatile memory device.

[0012] In some embodiments, the third memory controller includes a third interface; the third interface is coupled to the second interface.

[0013] In some embodiments, the third memory controller includes a third interface, the volatile memory device further includes a fourth interface; and the third interface is coupled to the fourth interface.

[0014] In some embodiments, the volatile memory device includes a plurality of modules; the first interface and the second interface also include a mutually coupled function signal pin area, the function signal pin area includes a first chip select signal pin and a second chip select signal pin;

[0015] The first chip select signal pin in the second interface is configured to receive a first chip select signal; the volatile memory device is configured to operate a specified module among the plurality of modules according to the first chip select signal;

[0016] The second chip select signal pin in the second interface is configured to receive a second chip select signal; the volatile memory device is configured to select to interact with the third memory controller or the storage device according to the second chip select signal.

[0017] According to a third aspect of an embodiment of the present disclosure, there is provided a method for operating a memory system, including:

[0018] Based on the storage device being coupled to the volatile memory device, the storage device interacts with the volatile memory device; the storage device includes a non-volatile memory device and a first memory controller coupled to the non-volatile memory device.

[0019] According to a fourth aspect of an embodiment of the present disclosure, there is provided a method for operating an electronic device, including:

[0020] Based on the volatile memory device being coupled to both the host and the storage device, the volatile memory device interacts with the host and / or the storage device.

[0021] In some embodiments, the host includes a second memory controller and a third memory controller; the second memory controller is coupled to the storage device, and the third memory controller is coupled to the volatile memory device;

[0022] The volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including:

[0023] When the third memory controller is in a closed state, the volatile memory device interacts with the storage device;

[0024] When the third memory controller is in an on state, the volatile memory device interacts with the host.

[0025] In some embodiments, the volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including:

[0026] When the bandwidth share of the host to the volatile memory device is less than or equal to a preset value, the volatile memory device interacts with the host and the storage device;

[0027] When the bandwidth proportion of the host to the volatile memory device is greater than a preset value, the volatile memory device interacts with the host.

[0028] In some embodiments, the volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including:

[0029] A first storage area in the volatile memory device interacts with the host, and a second storage area in the volatile memory device interacts with the storage device.

[0030] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0031] The disclosed embodiment sets a first interface in the storage device, sets a second interface in the volatile memory device, and couples the first interface with the second interface, thereby realizing control of the volatile memory device by the first memory controller in the storage device, so that the storage device and the volatile memory device can interact directly, thereby improving the utilization rate of the volatile memory device and the working efficiency of the storage device; and the storage device can directly interact with the volatile memory device without relying on the host, thereby saving host resources and not requiring additional hardware costs. By using this technology, the competitiveness of consumer electronics such as mobile phones can be improved.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0034] Figure 1 is a block diagram of a memory system according to an exemplary embodiment;

[0035] Figure 2 is a schematic diagram showing a first interface coupled to a second interface according to an exemplary embodiment;

[0036] Figure 3 is a block diagram of an electronic device according to an exemplary embodiment;

[0037] Figure 4 is a flow chart showing an operating method of a memory system according to an exemplary embodiment;

[0038] Figure 5 The present invention is a flowchart of an operating method of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0039] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0040] Figure 1is a block diagram of a memory system 10 according to an exemplary embodiment, the memory system 10 includes: a storage device 100 and a volatile memory device 200; wherein,

[0041] The storage device 100 includes a non-volatile memory device 110, a first memory controller 120 coupled to the non-volatile memory device 110, and a first interface 130; the first memory controller 120 is configured to control the non-volatile memory device 110; the volatile memory device 200 includes a second interface 230; the second interface 230 is coupled to the first interface 130 so that the storage device 100 and the volatile memory device 200 can interact.

[0042] The storage device 100 in the embodiment of the present disclosure includes but is not limited to a Universal Flash Storage (UFS) device and an embedded Multi-Media Card (eMMC).

[0043] The storage device 100 includes a non-volatile memory device 110 and a first memory controller 120. The non-volatile memory device 110 includes, but is not limited to, NAND Flash Memory, NOR Flash Memory, and Read-Only Memory (ROM). The non-volatile memory device 110 refers to a memory device that can retain stored data after the power is turned off. In the embodiment of the present disclosure, the storage device 100 is described as a UFS device, but it should be understood that the present disclosure is not limited thereto.

[0044] The first memory controller 120 in the implementation of the present disclosure may be configured to control the non-volatile memory device 110. In some embodiments, the first memory controller 120 may interact with the non-volatile memory device 110 based on instructions sent by the host. In other embodiments, the first memory controller 120 may also interact with the non-volatile memory device 110 based on instructions embedded in the non-volatile memory device 110. In the embodiment of the present disclosure, the storage device 100 may be a UFS device, and accordingly, the first memory controller 120 may be an internal controller of the UFS device.

[0045] The volatile memory device 200 in the implementation of the present disclosure includes but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), etc. In the embodiment of the present disclosure, the volatile memory device 200 is described as LPDDR5 in DDR SDRAM, and it should be understood that the present disclosure is not limited to this.

[0046] In some embodiments, when the storage device 100 is a UFS device, the nonvolatile memory device 110 may be a NAND flash memory, and the first memory controller 120 may be an internal controller of the UFS device.

[0047] In some embodiments, when the storage device 100 is an eMMC, the non-volatile memory device 110 may be a NAND flash memory, and the first memory controller 120 may be an eMMC internal controller.

[0048] The storage device 100 in the embodiment of the present disclosure includes a first interface 130, and the volatile memory device 200 includes a second interface 230, and the first interface 130 is coupled to the second interface 230. In this way, the storage device 100 and the volatile memory device 200 can interact with each other through the first interface 130 and the second interface 230. In some embodiments, the interaction between the storage device 100 and the volatile memory device 200 includes but is not limited to: writing data from the storage device 100 to the volatile memory device 200, reading data from the volatile memory device 200 and storing it in the storage device 100, erasing data in the volatile memory device 200 using the storage device 100, and the like.

[0049] Here, the coupling mode between the first interface 130 and the second interface 230 may be a direct electrical connection or an indirect electrical connection. For example, the first interface 130 and the second interface 230 may be indirectly connected by a lead, thereby realizing an indirect electrical connection. For another example, the first interface 130 may include a plurality of metal pins, and the second interface 230 may also include a plurality of metal pins, and the plurality of metal pins of the first interface 130 may directly contact the plurality of metal pins corresponding to the second interface 230, thereby realizing a direct electrical connection.

[0050] The first memory controller 120 may also be configured to control the volatile memory device 200. Here, the first memory controller 120 may interact with the volatile memory device 200 based on instructions sent by the host, and may also interact with the volatile memory device 200 based on instructions embedded in the non-volatile memory device 110. The interaction here includes but is not limited to operations such as reading data, erasing data, and writing data to the volatile memory device 200.

[0051] In some embodiments, the storage device 100 may be an external storage, and the volatile memory device 200 may be an internal memory. It should be noted that the storage device 100 may have an additional volatile memory device 200, but the storage device 100 uses the non-volatile memory device 110 therein as a storage medium, and uses the volatile memory device 200 in the storage device 100 as a buffer, which can temporarily store write data provided by the host or data read from the non-volatile memory 110. The volatile memory device 200 itself serves as a storage medium.

[0052] The embodiment of the present disclosure sets a first interface 130 in the storage device 100, sets a second interface 230 in the volatile memory device 200, and couples the first interface 130 with the second interface 230, thereby realizing control of the volatile memory device 200 by the first memory controller 120 in the storage device 100, allowing the storage device 100 and the volatile memory device 200 to interact directly, thereby improving the utilization rate of the volatile memory device 200 and the working efficiency of the storage device 100. By using this technology, the competitiveness of consumer electronics such as mobile phones can be improved.

[0053] In some embodiments, the storage device 100 and the volatile memory device 200 are packaged on the same substrate.

[0054] In the embodiment of the present disclosure, the storage device 100 may be a UFS device, and the volatile memory device 200 may be LPDDR5. The storage device 100 and the volatile memory device 200 may be stacked and packaged on the same substrate using multi-chip packaging technology (Multi Chip Package, MCP) to form a universal flash memory multi-layer packaging chip (UFS Multi Chip Package, uMCP).

[0055] In some embodiments, the storage device 100 may be an eMMC, and the volatile memory device 200 may be an LPDDR5, and both may be stacked and packaged on the same substrate using multi-chip packaging technology to form an embedded Multi-Media Card Multi-Chip-Package (eMCP).

[0056] By stacking the storage device 100 and the volatile memory device 200 vertically on the substrate, the area occupied by the storage device 100 and the volatile memory device 200 can be saved, making the uMCP chip or eMCP chip formed after packaging more suitable for miniaturized mobile phones and computers.

[0057] Figure 2 1 is a schematic diagram showing a coupling of a first interface 130 and a second interface 230 according to an exemplary embodiment, wherein the first interface 130 includes a first clock signal pin area 410, a first power signal pin area 420, a first command address signal pin area 430, and a first data pin area 440; the second interface 230 includes a second clock signal pin area 510, a second power signal pin area 520, a second command address signal pin area 530, and a second data pin area 540;

[0058] The first clock signal pin area 410 is coupled correspondingly to the second clock signal pin area 510; the first power signal pin area 420 is coupled correspondingly to the second power signal pin area 520; the first command address signal pin area 430 is coupled correspondingly to the second command address signal pin area 530; the first data pin area 440 is coupled correspondingly to the second data pin area 540.

[0059] In the embodiment of the present disclosure, the first clock signal pin area 410 and the second clock signal pin area 510 may include multiple groups of clock signal pins, each group of clock signal pins including two clock signal pins.

[0060] The volatile memory device 200 in the embodiment of the present disclosure is LPDDR5, and the first clock signal pin area 410 and the second clock signal pin area 510 may each include three groups of clock signal pins. The first group of clock signal pins may include a CK_t pin and a CK_c pin. The CK_t pin is configured to send or receive a CK_t clock signal, and the CK_c pin is configured to send or receive a CK_c clock signal. The CK_t clock signal and the CK_c clock signal are a group of differential signals.

[0061] In some implementations, the address, command, and control input signals are sampled at the rising edge of the CK_t clock signal, and the data strobe signal (DQS) is sampled at the intersection of the CK_t clock signal and the CK_c clock signal.

[0062] The second group of clock signal pins may include a WCK[1:0]_t pin and a WCK[1:0]_c pin. The WCK[1:0]_t pin is configured to send or receive a WCK[1:0]_t clock signal, and the WCK[1:0]_c pin is configured to send or receive a WCK[1:0]_c clock signal. The WCK[1:0]_t clock signal and the WCK[1:0]_c clock signal are a group of differential signals. The WCK[1:0]_t clock signal and the WCK[1:0]_c clock signal are a group of write clock signals for write operations.

[0063] The third group of clock signal pins may include an RDQS[1:0]_t pin and an RDQS[1:0]_c pin. The RDQS[1:0]_t pin is configured to send or receive an RDQS[1:0]_t clock signal, and the RDQS[1:0]_c pin is configured to send or receive an RDQS[1:0]_c clock signal. The RDQS[1:0]_t clock signal and the RDQS[1:0]_c clock signal are a group of differential signals, denoted as RDQS signals. The RDQS[1:0]_t clock signal and the RDQS[1:0]_c clock signal are a group of read clock signals for a read operation.

[0064] The DQS signal is a data clock signal, and the RDQS signal is a reverse data clock signal. The DQS signal is used to control data transmission, and the RDQS signal is used to control data reception. The DQS signal and the RDQS signal appear in pairs, and their phase relationship is very important, and precise matching is required to ensure the correct transmission of data.

[0065] In some embodiments, RDQS can be configured to single-ended mode through a mode register, that is, only one of RDQS[1:0]_t or RDQS[1:0]_c is used, and used in low-speed and power-saving scenarios.

[0066] In the embodiment of the present disclosure, the clock signals received by the multiple groups of clock signal pins in the second interface 230 may come from the clock signals output by the multiple groups of clock signal pins in the corresponding first interface 130 .

[0067] The first power signal pin area 420 and the second power signal pin area 520 may each include a plurality of power signal pins. In the embodiment of the present disclosure, five power signal pins may be included. The first power signal pin is configured to send or receive a VDDQ power signal, the second power signal pin is configured to send or receive a VDD1 power signal, the third power signal pin is configured to send or receive a VDD2H power signal, and the fourth power signal pin is configured to send or receive a VDD2L power signal. The fifth power signal pin is configured to send or receive a VSS power signal.

[0068] In the embodiment of the present disclosure, the VDDQ power signal can be used to power the second interface 230 of the volatile memory device 200, so the required voltage is relatively small, for example, it can be 0.5V. The VDD1 power signal, the VDD2H power signal and the VDD2L power signal are used to power the peripheral circuits in the volatile memory device 200. For example, the VDD1 power signal can be 1.8V. The VDD2H power signal is generally higher than the VDD2L power signal, the VDD2H power signal can be 1.05V, and the VDD2L power signal can be 0.95V. The VSS power signal can be 0V.

[0069] In some other embodiments, for example, the non-volatile memory device 110 is LPDDR4, which includes four power signal pins, which are respectively configured to send or receive a VDDQ power signal, a VDD1 power signal, a VDD2 power signal (similar to the VDD2H power signal in LPDDR5), and a VSS power signal.

[0070] Compared with LPDDR4, LPDDR5 can use low voltage VDD2L, thus saving power consumption.

[0071] It can be understood that the first power signal pin area 420 and the second voltage signal pin area 520 include the same number and type of power pins, and the number and type of power pins can be set according to actual needs.

[0072] In the embodiment of the present disclosure, the power signals received by the multiple power signal pins in the second interface 230 may come from the power signals output by the multiple power signal pins in the first interface 130 .

[0073] In the embodiment of the present disclosure, both the first command address signal pin area 430 and the second command address signal pin area 530 may include a plurality of command address signal pins.

[0074] In the embodiment of the present disclosure, 7 command address signal pins may be included. The 7 command address signal pins are configured to receive or output command address signals in the format of CA[6:0]. It should be understood that the number of the above command address signal pins is only an example, and the present disclosure does not limit the specific number of command address signal pins.

[0075] In the embodiment of the present disclosure, the command address signals received by the multiple command address signal pins in the second interface 230 may come from the command address signals output by the multiple command address signal pins in the first interface 130 .

[0076] In the embodiment of the present disclosure, both the first data pin area 440 and the second data pin area 540 may include a plurality of data signal pins.

[0077] In the embodiment of the present disclosure, 16 data signal pins may be included. The 16 data signal pins are configured to receive or output data signals in the format of DQ[15:0]. It should be understood that the number of the above data signal pins is only an example, and the present disclosure does not limit the specific number of data signal pins.

[0078] In the embodiment of the present disclosure, the data signals received by the multiple data signal pins in the second interface 230 may come from the data signals output by the multiple data signal pins in the first interface 130, or the data signals received by the multiple data signal pins in the first interface 130 may come from the data signals output by the multiple data signal pins in the second interface 230.

[0079] In the embodiment of the present disclosure, the first interface 130 and the second interface 230 may both include a function signal pin area.

[0080] Figure 3It is a block diagram of an electronic device 20 according to an exemplary embodiment, including the memory system 10 as described in the above embodiment, and a host 300; the host 300 includes a second memory controller 310 and a third memory controller 320, the second memory controller 310 is coupled to the storage device 100, and the third memory controller 320 is coupled to the volatile memory device 200.

[0081] In the disclosed embodiment, the electronic device 20 may include: a terminal device, for example, a mobile terminal or a fixed terminal. The mobile terminal may include: a mobile phone, a tablet computer, a laptop computer, a wearable electronic device, etc. The fixed terminal may include: a desktop computer, a smart TV, a vehicle-mounted device, etc.

[0082] The host 300 in the embodiment of the present disclosure also includes a processor 330, which may be a processor 330 of the electronic device 20 (e.g., a central processing unit (CPU)) or a processor 330 of a system on chip (SoC) (e.g., an application processor (AP)).

[0083] The embodiment of the present disclosure is described by taking the host 300 as a system on chip as an example, and it should be understood that the present disclosure is not limited thereto. The system on chip includes a processor 330 , a second memory controller 310 , and a third memory controller 320 .

[0084] The interaction between the system on chip and the volatile memory device 200 can be implemented through the processor 330 and the third memory controller 320. The third memory controller 320 is a hardware module in the system on chip, which is responsible for managing the read and write operations of the volatile memory device 200. The processor 330 of the system on chip obtains instructions and sends the instructions to the third memory controller 320. The third memory controller 320 converts these commands and data into a format that the volatile memory device 200 can understand and sends them to the volatile memory device 200. When the volatile memory device 200 completes the read and write operations, the third memory controller 320 returns the results to the processor 330 of the system on chip. In this way, the system on chip can interact with the volatile memory device 200 through the third memory controller 320.

[0085] The interaction between the system on chip and the storage device 100 (eg, a UFS device) may be implemented through the second memory controller 310 .

[0086] The communication between the host 300 and the UFS device is a hierarchical communication architecture based on the Internet Small Computer System Interface (SCSI) model. For example, the specific process of the host 300 interacting with the UFS device can be: the application layer of the host 300 (including the processor 330 (for example, the application processor)) issues a SCSI command, the transport layer of the host 300 (including the second memory controller 310) receives the SCSI command and encapsulates it into a UFS Protocol Information Unit (UPIU) command that can be recognized by the UFS, and the interconnection layer of the host 300 sends the UPIU command to the interconnection layer of the UFS device in the form of an electrical signal (here, the interconnection layer of the host and the interconnection layer of the UFS device are used to realize the link between the host and the UFS device). The interconnection layer of the UFS device receives the electrical signal and re-encapsulates it into a UPIU command through the transport layer of the UFS device. The application layer of the UFS device receives the UPIU command and responds.

[0087] In some embodiments, the third memory controller 320 further includes a third interface; the third interface is coupled to the second interface 230 .

[0088] Here, the interconnection layer of the host 300 may be the third interface, and the interconnection layer of the UFS device may be the second interface in the storage device.

[0089] In the embodiment of the present disclosure, the volatile memory device 200 is coupled to both the host 300 and the UFS device through the second interface 230 .

[0090] In the embodiment of the present disclosure, the first interface 130 of the UFS device is coupled to the second interface 230 of the volatile memory device 200. The third interface of the host 300 is also coupled to the second interface 230 of the volatile memory device 200. It can be understood that the UFS device and the host 300 can share the second interface 230 in the volatile memory device 200, and the UFS device and the host 300 are both coupled to the second interface 230 in the volatile memory device 200, so that the host and the UFS device can access the volatile memory device in a time-sharing manner.

[0091] In some embodiments, the third memory controller 320 includes a third interface, and the volatile memory device 200 further includes a fourth interface; the third interface is coupled to the fourth interface.

[0092] In the embodiment of the present disclosure, the first interface 130 of the UFS device is coupled to the second interface 230 of the volatile memory device 200, and the third interface of the third memory controller 320 is coupled to the fourth interface of the volatile memory device 200. It can be understood that the UFS device and the host 300 may not share the same interface in the volatile memory device 200, so that the volatile memory device 200 can interact with the host 300 and the UFS device at the same time.

[0093] In the embodiment of the present disclosure, by setting the first interface 130 on the storage device 100 and setting the second interface 230 on the volatile memory device 200, and coupling the first interface 130 with the second interface 230, the storage device 100 can also interact with the volatile memory device 200. The host 300 and the storage device 100 can interact with the volatile memory device 200 at the same time, and the host 300 and the storage device 100 can also interact with the volatile memory device 200 in a time-sharing manner, thereby improving the utilization rate of the volatile memory device 200.

[0094] In some embodiments, the volatile memory device includes a plurality of modules (RANK); the first interface and the second interface also include mutually coupled functional signal pin areas, and the functional signal pin area includes a first chip select signal pin.

[0095] In some embodiments, the volatile memory device may include multiple RANKs. Each RANK may include a first chip select signal pin configured to receive a first chip select signal. When the first chip select signal on the corresponding RANK is valid, a read and write operation may be performed on the specified RANK. In some embodiments, the first chip select signal is valid at a low level; in other embodiments, the first chip select signal is valid at a high level. This may be set according to the corresponding specification.

[0096] In some embodiments, the volatile memory device includes a plurality of modules; the first interface and the second interface also include a mutually coupled function signal pin area, the function signal pin area includes a first chip select signal pin and a second chip select signal pin;

[0097] The first chip select signal pin in the second interface is configured to receive a first chip select signal; the volatile memory device is configured to operate a specified module among the plurality of modules according to the first chip select signal;

[0098] The second chip select signal pin in the second interface is configured to receive a second chip select signal; the volatile memory device is configured to select to interact with the third memory controller or the storage device according to the second chip select signal.

[0099] In some embodiments, both the first interface and the second interface may include a second chip select signal pin, the second chip select signal pin on the first interface is configured to send a second chip select signal, and the second chip select signal pin on the second interface is configured to receive a second chip select signal. When the second chip select signal is at a first level, other pins on the second interface are configured to allow reception of signals sent by the host and prohibit reception of signals sent by the storage device. When the second chip select signal is at a second level, other pins on the second interface are configured to allow reception of signals sent by the storage device and prohibit reception of signals sent by the host. By setting the second chip select signal pin in the functional signal pin area, the host and the storage device can access the volatile memory device in a time-sharing manner. Here, the first level can be a high level or a low level. Exemplarily, when the first level is a high level, the second level is a low level; when the first level is a low level, the second level is a high level.

[0100] In some embodiments, the functional signal pin area further includes a data bus flip pin, which is configured to send or receive a DMI data bus flip signal. When the data on the data bus flips, the DMI is a high signal, and when the data on the data bus is normal, the DMI is a low signal. A DMI data bus flip signal can be connected after each byte of data.

[0101] In some embodiments, the functional signal pin area further includes a ZQ (reference resistor) pin, which is used to calibrate the output drive strength and terminal resistance. LPDDR5 may include one or more Dies (chips), each of which may include multiple BANKs. Each Die includes a ZQ pin.

[0102] In some embodiments, the function signal pin further includes a reset signal pin, and the reset signal pin is configured to send or receive a Reset_n reset signal. When the Reset_n reset signal is valid, multiple channels on the Die can be reset. The Reset_n reset signal can be low level valid.

[0103] In some embodiments, the functional signal pins may also include other pins specified by the Joint Electron Device Engineering Council (JEDEC) standard as needed, and are set according to relevant JEDEC specifications, which will not be repeated here.

[0104] Figure 4 is a flow chart showing an operation method of a memory system according to an exemplary embodiment. Figure 4 As shown, the operation method includes:

[0105] In step 101, based on the coupling of a storage device to a volatile memory device, the storage device interacts with the volatile memory device; the storage device includes a non-volatile memory device and a first memory controller coupled to the non-volatile memory device.

[0106] In some implementations, by setting a first interface in a storage device, setting a second interface in a volatile memory device, and coupling the first interface with the second interface, a first memory controller in the storage device can be used to interact with the volatile memory device, thereby improving the utilization rate of the volatile memory device.

[0107] Figure 5 is a flow chart of an operating method of an electronic device according to an exemplary embodiment. Figure 5 As shown, the operation method includes:

[0108] In step 201 , based on the volatile memory device being coupled to both a host and a storage device, the volatile memory device interacts with the host and / or the storage device.

[0109] In some embodiments, the host and the storage device may interact with the volatile memory device at the same time, or the host and the storage device may interact with the volatile memory device in a time-sharing manner.

[0110] In the embodiment of the present disclosure, by setting a first interface in a storage device, setting a second interface in a volatile memory device, and coupling the first interface with the second interface, a first memory controller in the storage device can be used to interact with the volatile memory device. The electronic device in this embodiment also includes a host. The host and the storage device can interact with the volatile memory device in a time-sharing or simultaneous manner, thereby improving the utilization rate of the volatile memory device and the performance of the storage device. The storage device can directly interact with the volatile memory device without relying on the host, thereby saving the resources of the host.

[0111] In some embodiments, the host includes a second memory controller and a third memory controller; the second memory controller is coupled to the storage device, and the third memory controller is coupled to the volatile memory device;

[0112] The volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including:

[0113] When the third memory controller is in a closed state, the volatile memory device interacts with the storage device;

[0114] When the third memory controller is in an on state, the volatile memory device interacts with the host.

[0115] In some embodiments, the UFS device performs garbage collection operations in the background to ensure that the space in the flash memory is used to the maximum extent. In other embodiments, the UFS device performs bad block management operations in the background to ensure that bad blocks in the flash memory do not affect system performance and reliability. In still other embodiments, the UFS device performs data recovery operations in the background to ensure that data in the flash memory is not lost. Garbage collection, bad block management, and data recovery can all be performed during idle time to avoid affecting system performance.

[0116] In some embodiments, when the host is in low power mode, the third memory controller can be turned off and the volatile memory device DDR is in an idle state. At this time, the storage device 100 can use the high bandwidth and large capacity of DDR to quickly complete garbage collection, bad block management and other tasks.

[0117] For example, when the UFS device is performing garbage collection, the valid data in the garbage block to be collected in the UFS device can be first moved to part of the storage area of ​​the DDR. After the UFS device completes the erasing operation on the data in the garbage block, the valid data cached in the DDR is concentrated and stored in the designated storage block in the UFS device.

[0118] For another example, when the UFS device is performing bad block management, part of the storage area in the DDR can be used to replace the area where the bad block in the UFS device is located, and the information in the bad block of the UFS device is transferred to the target storage area in the DDR.

[0119] It is understandable that part of the storage area in the DDR may be a designated storage area or a randomly written storage area, which is not limited here.

[0120] In some embodiments, when the host is in normal power consumption mode, the third memory controller is turned on, and the third memory controller can be used to interact with the non-volatile memory device to complete garbage collection, bad block management and other tasks.

[0121] In the embodiment of the present disclosure, by coupling the storage device to the volatile memory device, and coupling the host to the storage device and the volatile memory device respectively, time-sharing access to the volatile memory device for the host and the storage device can be achieved, thereby improving the utilization rate of the volatile memory device.

[0122] In some embodiments, the volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including:

[0123] When the bandwidth share of the host to the volatile memory device is less than or equal to a preset value, the volatile memory device interacts with the host and the storage device;

[0124] When the bandwidth proportion of the host to the volatile memory device is greater than a preset value, the volatile memory device interacts with the host.

[0125] In some embodiments, a preset value can be set for the bandwidth share of the host to the volatile memory device LPDDR5. When the bandwidth share of the host to LPDDR5 is less than or equal to the preset value, it can be considered that the performance of LPDDR5 is not fully utilized at this time. The preset value can be 30% or 40%. This value can be set by the user or by default before leaving the factory. When the bandwidth share of the host to LPDDR5 is less than or equal to the preset value, the UFS device and the host can be allowed to interact with LPDDR5 at the same time.

[0126] In some embodiments, the host, UFS device and LPDDR5 can form a mobile phone. When the characteristics of the application used by the mobile phone are relatively simple, such as only basic data storage and reading operations are required, and the host's share of LPDDR5 bandwidth is less than or equal to a preset value, the UFS device can use a portion of the DDR memory to improve data storage and reading operations.

[0127] In some embodiments, when the host's bandwidth share of LPDDR5 is greater than a preset value, it can be considered that LPDDR5 is no longer suitable for interacting with the UFS device, and LPDDR5 can be prohibited from receiving interaction requests from UFS. When the mobile phone is using large or multiple applications, the UFS device is not allowed to interact with DDR.

[0128] In the embodiment of the present disclosure, when the bandwidth of the volatile memory device occupied by the host accounts for a small proportion, the storage device and the host can interact with the volatile memory device at the same time, thereby improving the utilization rate of the volatile memory device.

[0129] In some embodiments, the volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including:

[0130] A first storage area in the volatile memory device interacts with the host, and a second storage area in the volatile memory device interacts with the storage device.

[0131] In some embodiments, the storage area in LPDDR5 can be partitioned, where the first storage area is used to interact with the host and the second storage area is used to interact with the storage device. In this way, the host and the UFS device can interact with the LPDDR5 at the same time without interfering with each other.

[0132] In some embodiments, the most obvious benefit brought by the large-capacity LPDDR5 in mobile phones is the increase in the number of resident background applications. However, in actual applications, it is difficult to fully use the space of the large-capacity LPDDR5. At this time, the UFS device can use part of the DDR memory as a buffer to improve the reading and writing speeds.

[0133] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0134] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0135] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0136] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0137] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0138] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims above.

[0139] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A memory system, characterized in that: include: Storage device and volatile memory device; wherein, The storage device includes a non-volatile memory device, a first memory controller coupled to the non-volatile memory device, and a first interface; the first memory controller is configured to control the non-volatile memory device; the volatile memory device includes a second interface; the second interface is coupled to the first interface so that the storage device can interact with the volatile memory device.

2. The memory system according to claim 1, wherein: The volatile memory device includes a double rate synchronous dynamic random access memory; the storage device includes a universal flash memory and an embedded multimedia card.

3. The memory system according to claim 1, wherein: The storage device and the volatile memory device are packaged on the same substrate.

4. The memory system according to claim 2, wherein: The first interface includes a first clock signal pin area, a first power signal pin area, a first command address signal pin area and a first data pin area; the second interface includes a second clock signal pin area, a second power signal pin area, a second command address signal pin area and a second data pin area; The first clock signal pin area is coupled to the second clock signal pin area; the first power signal pin area is coupled to the second power signal pin area; the first command address signal pin area is coupled to the second command address signal pin area; and the first data pin area is coupled to the second data pin area.

5. An electronic device, characterized in that: It includes a memory system as described in any one of claims 1 to 4, and a host; the host includes a second memory controller and a third memory controller, the second memory controller is coupled to the storage device, and the third memory controller is coupled to the volatile memory device.

6. The electronic device according to claim 5, characterized in that: The third memory controller includes a third interface; the third interface is coupled to the second interface.

7. The electronic device according to claim 5, characterized in that: The third memory controller includes a third interface, and the volatile memory device further includes a fourth interface; the third interface is coupled to the fourth interface.

8. The electronic device according to claim 5, characterized in that: The volatile memory device includes a plurality of modules; the first interface and the second interface also include mutually coupled function signal pin areas, the function signal pin area includes a first chip select signal pin and a second chip select signal pin; The first chip select signal pin in the second interface is configured to receive a first chip select signal; the volatile memory device is configured to operate a specified module among the plurality of modules according to the first chip select signal; The second chip select signal pin in the second interface is configured to receive a second chip select signal; the volatile memory device is configured to select to interact with the third memory controller or the storage device according to the second chip select signal.

9. A method for operating a memory system, characterized in that: include: Based on the storage device being coupled to the volatile memory device, the storage device interacts with the volatile memory device; The storage apparatus includes a nonvolatile memory device and a first memory controller coupled to the nonvolatile memory device.

10. A method for operating an electronic device, characterized in that: include: Based on the volatile memory device being coupled to both the host and the storage device, the volatile memory device interacts with the host and / or the storage device.

11. The operating method according to claim 10, characterized in that: The host includes a second memory controller and a third memory controller; the second memory controller is coupled to the storage device, and the third memory controller is coupled to the volatile memory device; The volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including: When the third memory controller is in a closed state, the volatile memory device interacts with the storage device; When the third memory controller is in an on state, the volatile memory device interacts with the host.

12. The operating method according to claim 10, characterized in that: The volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including: When the bandwidth share of the host to the volatile memory device is less than or equal to a preset value, the volatile memory device interacts with the host and the storage device; When the bandwidth proportion of the host to the volatile memory device is greater than a preset value, the volatile memory device interacts with the host.

13. The operating method according to claim 10, characterized in that: The volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and / or the storage device, including: A first storage area in the volatile memory device interacts with the host, and a second storage area in the volatile memory device interacts with the storage device.

Images