Memory system, data exchange method and electronic device of multi-core graphics processor

Abstract

The present application discloses a memory system and an electronic device of a multi-core graphics processor (GPU). The memory system comprises: a multi-level storage structure; the multi-level storage structures communicate with each other via a first bus; each level of the storage structure comprises a plurality of cache blocks; the plurality of cache blocks communicate with each other via a second bus; a first cache block among the plurality of cache blocks at each level is used to transmit first cache data to a second cache block among the plurality of cache blocks via the second bus.

Description

Technical Field

[0001] The present application relates to, but is not limited to, the field of computer technology, and in particular to a memory system, a data exchange method, and an electronic device of a multi-core graphics processor. Background Art

[0002] Large-scale graphics processing units (GPUs) usually include multiple GPU cores. The memory required by multi-core GPUs for data processing includes distributed cache blocks. These cache blocks are multi-level storage structures connected through a multi-level interconnection system. Among them, the first-level storage structure communicates directly with the GPU core, and each core is set with a corresponding cache block to store the real-time data required for the corresponding core calculation; the last-level storage structure includes dynamic random access memory (DRAM), which has a large storage space. Since the communication between different cache blocks needs to be transferred through DRAM, the communication delay is high, which affects the processing performance of the multi-core GPU. Summary of the invention

[0003] The embodiments of the present application provide a memory system, a data exchange method and an electronic device of a multi-core graphics processor GPU. The cache blocks in each level of storage structure can communicate through a second bus, which can reduce the communication delay between different cache blocks, thereby improving the data processing performance of the multi-core GPU.

[0004] The technical solution of this application is implemented as follows:

[0005] The present application embodiment provides a memory system of a multi-core graphics processor GPU, including:

[0006] A multi-level storage structure; the multi-level storage structures communicate with each other via a first bus; each level of the storage structure includes a plurality of cache blocks; the plurality of cache blocks communicate with each other via a second bus;

[0007] A first cache block among the multiple cache blocks of each level is used to transmit the first cache data to a second cache block among the multiple cache blocks through a second bus.

[0008] The present application provides a data exchange method, which is applied to a memory system of a multi-core graphics processor GPU, wherein the memory system includes a multi-level storage structure; the multi-level storage structures communicate with each other through a first bus; each level of the storage structure includes a plurality of cache blocks; the plurality of cache blocks communicate with each other through a second bus; the data exchange method includes:

[0009] The second core sends a data interaction command to the first core;

[0010] The first core responds to the data interaction command and transmits the read data indication information to the first cache block through the first bus; the read data indication information represents the need for the second core to read the first cache data;

[0011] The first cache block transmits the first cache data to the second cache block through the second bus based on the read data indication information;

[0012] The second core reads the first cache data from the second cache block.

[0013] An embodiment of the present application provides an electronic device, including a multi-core GPU and a memory system of the multi-core GPU. The multi-core GPU stores an executable computer program, and the steps of the above method are implemented when the multi-core GPU executes the program.

[0014] The embodiments of the present application provide a memory system and an electronic device of a multi-core graphics processor (GPU). Since a second bus is provided between multiple cache blocks in each level of storage structure, multiple cache blocks at the same level can communicate with each other through the second bus. In combination with the first bus between storage structures at different levels, when data is transmitted between any two cache blocks, there is no need to transfer data at a fixed level, thereby reducing the delay of the data transmission process and improving the data processing performance of the multi-core GPU.

[0015] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0017] Figure 1 A schematic diagram of the structure of a multi-core GPU memory system in a related technology provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of a data exchange process in a related technology provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the structure of a memory system of a multi-core GPU provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a data exchange process provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of a process of using a near-stored parameter provided in an embodiment of the present application;

[0022] Figure 6 A flowchart of a data interaction method provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0025] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0028] To facilitate understanding of the present solution, before describing the embodiments of the present application, the application background of the embodiments of the present application is described.

[0029] Figure 1 FIG. 4 shows a memory system of a multi-core GPU in the related art. Figure 1As shown, the memory system 10 of multiple cores corei (cores core1-core4 are shown as an example) includes a two-level storage structure. The first-level storage structure 101 includes multiple cache blocks L1i (L11-L14 are shown as an example) corresponding to the multiple cores, and i is an integer greater than 1. Each core and the corresponding cache block Li communicate through a crossbar bus of a crossbar switch matrix. The second-level storage structure 102 includes multiple cache blocks L2j (L21-L24 are shown as an example) and DRAM Dj corresponding to each cache block (D1-D4 are shown as an example), and j is an integer greater than 1. The cache blocks L1i in the first-level storage structure and the cache blocks L2j in the second-level storage structure communicate through crossbar; the cache blocks L2j in the second-level storage structure communicate with the corresponding Dj through crossbar. It can be seen that any L1i and any L2j can communicate with each other, and any corei can directly obtain the data in the L1i corresponding to itself, and obtain the data in any other L2j through the L1i. Based on Figure 1 , Figure 2 shows a data exchange process, such as Figure 2 As shown, the process includes:

[0030] S01, core1 issues a data refresh command.

[0031] In S01, the data refresh command can be transmitted from core1 to the corresponding L11, and the data in L11 can be exchanged with other cores.

[0032] S02 and L11 flush data to L23.

[0033] S03 and L23 transfer data to D3.

[0034] When core1 exchanges data with other cores other than core1, the data must be flushed out first. Here, the DRAM saved after the data is flushed out is D3, and it needs to be transferred to D3 through L23.

[0035] S04, core2 issues a read data instruction.

[0036] In S04, after the data is saved in D3, if other cores want to read the data, they need to issue a read data instruction to their corresponding L1i, notifying L1i to read the data in D3 through L23.

[0037] S05, L12 forwards the read data instruction to L23.

[0038] S06, L23 read data from D3.

[0039] S07 and L23 transfer data to L12.

[0040] It can be seen that data exchange between L11 and L12 needs to be realized through L2 and DRAM, which leads to low efficiency of data exchange and affects the data processing efficiency of multi-core GPU.

[0041] In order to solve the above problems, an embodiment of the present application provides a memory system of a multi-core graphics processor GPU, which is arranged in an electronic device including a multi-core GPU. The electronic device may refer to any device that needs to use a multi-core GPU for computing, such as a server, a laptop, a tablet computer, a desktop computer, a smart TV, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a portable gaming device), etc.

[0042] Figure 3 A schematic diagram of an optional memory system of a multi-core graphics processor GPU is shown, Figure 3 As shown, the memory system 30 includes a multi-level storage structure (two-level storage structures 301 and 302 are shown as an example); the multi-level storage structures communicate with each other through a first bus B1; each level of storage structure includes multiple cache blocks (multiple cache blocks L31c in 301 and multiple cache blocks L32d in 302 are shown as an example) c and d are both integers greater than 0 and less than 5); multiple cache blocks of the kth level in the multi-level communicate with each other through a second bus B2k (B21 and B22 are shown as an example); the first cache block in the multiple cache blocks of each level is used to transfer the first cache data to the second cache block in the multiple cache blocks through the second bus.

[0043] In the embodiment of the present application, the first-level storage structure 301 in the multi-level storage structure communicates directly with the multi-core of the GPU through the first bus B1, and the other level storage structures except the first-level storage structure 301 communicate with the multi-core through the first-level storage structure 301. Among them, the number of multiple cache blocks L31m in the first-level storage structure 301 is the same as the number of multi-cores, and each core has a corresponding cache block. The cache data stored in L311 is the real-time data required by core1, the cache data stored in L312 is the real-time data required by core2, the cache data stored in L313 is the real-time data required by core3, and the cache data stored in L314 is the real-time data required by core4.

[0044] In an embodiment of the present application, multiple cache blocks in any one-level storage structure communicate through the second bus of that level. Cache blocks in two adjacent levels of storage structures communicate through the first bus between the two levels; any two cache blocks in two adjacent levels can communicate through the first bus. Among them, the first bus and the second bus are both buses that can transmit information. The bus may include: a cross bar bus, a ring bus, a mesh bus, a torus bus, etc., which is not limited by the embodiment of the present application.

[0045] In some embodiments, the first bus and the second bus may be the same bus. For example, the first bus and the second bus may both be cross bar buses with relatively large bandwidths, so as to ensure that the memory system 30 performs data transmission with relatively high data transmission efficiency.

[0046] In some embodiments, the bandwidth of the first bus may be greater than the bandwidth of the second bus. Since the data transmission requirements between cache blocks of the same level are not high, using a second bus with a small bandwidth can reduce bus costs.

[0047] In some embodiments, the first bus is a cross bar bus. In this way, the memory system 30 can set a transmission structure of the second bus on each cache block of the same level based on the existing technology, which can reduce the implementation cost of the memory system.

[0048] In some embodiments, the first bus is a cross bar bus, and the second bus is a ring bus. Due to the topological interconnection mechanism of the ring bus, the ring bus has a lower cost in the physical line of sight of the chip, which can reduce the bus cost.

[0049] In an embodiment of the present application, among multiple cache blocks of the same level, the first cache block can transfer the first cache data to the second cache block through the second bus. The first cache data is the data stored in the first cache block. In some embodiments, the first cache block is any one of the multiple cache blocks, and the second cache block is any one of the other cache blocks other than the first cache block. Exemplarily, L311 can upload the first cache data to the second bus, and L312 can receive the first cache data through the second bus. In some embodiments, the first cache block is any one of the multiple cache blocks, and the second cache block is all other cache blocks other than the first cache block. Exemplarily, L311 can upload the first cache data to the second bus, and L312-L314 can receive the first cache data through the second bus.

[0050] In an embodiment of the present application, the second cache block can receive all data on the second bus, and can also receive data sent to itself. In this regard, the present application is not limited. In some embodiments, the first cache data carries an identifier of the second cache block, and the second cache block can receive the first cache data when the identifier of the first cache data is the same as itself.

[0051] In some embodiments, the second cache block may receive the first cache data on the second bus only when there are free cache units in the second cache block.

[0052] In the embodiment of the present application, data can be transmitted between cache blocks distributed in any two-level storage structure 301 through cache blocks in all levels of storage structure between the two levels, and cache blocks in any one or more levels of the same level storage structure. The cache data of a cache block in any one-level storage structure is transmitted to a cache block in another level of storage structure through the first bus and the second bus. Exemplarily, L311 can send cache data to L322 through the first bus, and L322 can send cache data to L324 through the second bus.

[0053] In the embodiment of the present application, the first cache data may be cache data that the second cache block needs to read from the first cache block, or may be response information fed back to the second cache block after the first cache block reads the cache data of the second cache block. The embodiment of the present application does not limit this.

[0054] In the embodiment of the present application, each cache block may reserve an interface of the second bus at the boundary, and interconnection in the second bus is achieved through the interface.

[0055] It can be understood that since a second bus is set between multiple cache blocks in each level of storage structure, multiple cache blocks at the same level can communicate through this second bus; combined with the first bus between different levels of storage structures, when data is transmitted between any two cache blocks, there is no need to transfer data at a fixed level, which reduces the delay of the data transmission process and improves the data processing performance of the multi-core GPU.

[0056] In some embodiments of the present application, the first cache block is further used to package the cache identifier of the second cache block and the first cache data and upload them to the second bus; the other cache blocks except the first cache block among the multiple cache blocks are used to determine that they are the second cache block when the identifier of the second cache block of the first level is the same as their own cache identifier; and receive the first cache data.

[0057] In an embodiment of the present application, when the first cache block needs to send the first cache data to the designated second cache block, the first cache data and the cache identifier of the second cache block can be packaged into a data packet, and the data packet can be uploaded to the second bus. Here, the second cache block can be at least one of the other cache blocks other than the first cache block.

[0058] In the embodiment of the present application, the first cache data is transmitted on the second bus, and all cache blocks connected by the second bus can compare the cache identifier of the first cache data with their own cache identifier to obtain a comparison result. If the comparison result indicates that the two are the same, it is determined that it is the second cache block and receives the first cache data.

[0059] In some embodiments, the second bus is provided with an addressing bus and a data bus, the addressing bus is used to transmit the cache identifier of the second cache block, and the data bus is used to transmit the first cache data. When the cache identifier carried by the first cache data is the same as its own cache identifier, the signal on the addressing bus can enable the data receiving function of the second cache block, so that the second cache block can receive the first cache data. Wherein, the cache identifiers of different cache blocks in each level of storage structure are different.

[0060] In some embodiments, the cache flag may be a preset number of level signals; for example, L311 may be 00, L312 may be 01, L313 may be 10, and L314 may be 11.

[0061] In some embodiments, multiple cache blocks in each level of the storage structure communicate through a corresponding second bus; the cache identifier of each cache block is used to characterize the unique address of the cache block in a corresponding second bus. For example, cache block L31c in the first-level storage structure communicates through the second bus B21. L311 corresponds to address 1 in B21, L312 corresponds to address 2 in B21, L313 corresponds to address 3 in B21, and L314 corresponds to address 4 in B21. Multiple cache blocks at the same level can form a cache block group, which communicates with cache block groups at other levels through the first bus and can be used as a first-level shared cache for any core in a multi-core GPU; in this way, the cache space of each core can be expanded, and the flexibility of cache allocation of each core can be improved.

[0062] It is understandable that, since the first cache block packages the cache identifier of the second cache block and the first cache data and uploads them to the second bus, the cache block receiving the first cache data is specified by the cache identifier, which can improve the accuracy of data transmission.

[0063] In some embodiments of the present application, the second cache block is further used to receive the first cache data when there are free cache units in the second cache block.

[0064] In the embodiment of the present application, each cache block includes a plurality of cache units, and each cache unit stores a cache data in English. The second cache block can check its own free cache units, and only receive the first cache data when there are free cache units in itself. In this way, the situation where the second cache block receives the first cache data but cannot save it can be reduced, so that the second cache block can correctly receive the first cache data.

[0065] In some embodiments of the present application, the second cache block can perform an address comparison on a data packet transmitted on the second bus when it has a free cache unit, and receive the first cache data in the data packet when the comparison result indicates that the cache identifier of the second cache block is the same as the cache identifier of the data packet.

[0066] In some embodiments of the present application, the second cache block may first perform an address comparison on the data packet transmitted on the second bus, and when the comparison result indicates that the cache identifier of the second cache block is the same as the cache identifier of the data packet, it is then determined whether there is a free cache unit in itself. If there is a free cache unit in itself, the first cache data in the data packet is received.

[0067] In some embodiments of the present application, the second cache block is further used to receive the first cache data when the sum of the spaces of the free cache units is greater than or equal to the cache space required by the first cache data.

[0068] In an embodiment of the present application, the first cache data may include multiple data packets. When the second cache block determines that it has free cache units, it may first determine the sum of the free cache units and the size of the cache space required for the first cache data. When the sum of the free cache units is greater than or equal to the cache space required for the first cache data, it is determined that the space of the second cache block is sufficient for caching the first cache data. At this time, the first cache data is received again. The first cache data errors caused by insufficient space for caching the first cache data in the second cache block are reduced, thereby improving the accuracy of transmitting the first cache data between the first cache block and the second cache block.

[0069] In some embodiments of the present application, the second cache block is further used to transfer the first cache data to multiple cache blocks in the storage structure at the level of the second cache block through a second bus without receiving the first cache data, until the first cache data is transferred to the second cache block and the second cache block is able to receive the first cache data.

[0070] In the embodiment of the present application, after the first cache block uploads the first cache data to the second bus, a cache block after the first cache block can determine whether to receive the first cache data. If the cache block is not the second cache block, or the cache block is the second cache block but there is no free cache unit, the first cache data is not received. The cache block can continue to transmit the first cache data to the next cache block of the cache block until the second cache block receives the first cache data, completing the transmission of the first cache data.

[0071] In some embodiments, the second bus is a ring bus, each cache block has two adjacent cache blocks, and all cache blocks form a ring connection structure through the second bus. Data can be transmitted in a clockwise or counterclockwise direction on the second bus, and the first cache data can be transmitted in multiple rounds on the second bus. The second cache block has an opportunity to receive the first cache data in each round. If the second cache block does not receive the first cache data when it arrives, it needs to wait until the next round to receive it.

[0072] It is understandable that, when the first cache data is not received, it can be cyclically transmitted on the second bus according to the transmission order, so as to improve the flexibility of the second cache block in receiving the first cache data.

[0073] In some embodiments of the present application, the second bus includes an enable line for transmitting an enable signal and a data line for transmitting data; the first cache block is also used to generate a data signal based on the first cache data when the first enable signal indicates that the read data is valid; and transmit the data signal through the data line; the second cache block is also used to receive the data signal through the data line to obtain the first cache data when the second enable signal indicates that the write data is valid.

[0074] In an embodiment of the present application, the second bus of each level of storage structure includes an enable line and a data line. The data line is used to transmit the first cache data; the enable line is used to transmit the enable signal. Each cache block can control the writing or reading of data by transmitting the enable signal. When the transmission enable signal indicates that the write data is valid, the cache block can write the data on the data line; when the transmission enable signal indicates that the read data is valid, the cache block can upload the data to the data line.

[0075] In some embodiments, the enable line includes one, the first level of the enable signal indicates that the write data is valid, and the second level of the enable signal indicates that the read data is valid. In some embodiments, the enable line includes two, one for transmitting the write enable signal and the other for transmitting the read enable signal. In some embodiments, the write enable signal and the read enable signal can be valid at the same time, or only one can be valid; this is not limited in the embodiments of the present application.

[0076] In the embodiment of the present application, when the transmission enable signal indicates that the read data is valid, the first cache block can upload the first cache data to the data line in the form of a data signal. When the transmission enable signal indicates that the write data is valid, the second cache block can receive the data signal on the data line to obtain the first cache data.

[0077] In the embodiment of the present application, the transmission enable signal is controlled by each cache block itself. If the first cache block needs to upload its own first cache data, the transmission enable signal can be controlled so that the transmission enable signal indicates that the read data is valid. If the second cache block determines that it can receive the first cache data, the transmission enable signal can be controlled so that the transmission enable signal indicates that the write data is valid.

[0078] It can be understood that since the second bus includes different lines, different signals are transmitted respectively; wherein the enable line is used to transmit an enable signal for controlling the reception of the data signal on the data line; thus, the accuracy of transmitting different signals on the second bus can be improved.

[0079] In some embodiments of the present application, the second bus also includes an addressing line for transmitting an addressing signal; when the destination address indicated by the addressing signal matches its own cache identifier and the transmission enable signal indicates that the write data is valid, a data signal is received.

[0080] In the embodiment of the present application, the addressing line is used to transmit the addressing signal, the addressing signal is used to represent the destination address of the data signal transmitted on the data line, and the destination address is used to indicate the source of the data, that is, the cache block in the second bus.

[0081] In an embodiment of the present application, the first cache block can determine that the destination address matches its own cache identifier when the transmission enable signal indicates that the read data is valid and the destination address indicated by the first addressing signal is the corresponding address of the first cache block in the second bus; read the first cache data, and upload the first cache data and the second addressing signal for indicating the second cache block to the second bus; wherein the first cache data is transmitted through the data line, and the second addressing signal is transmitted through the addressing line.

[0082] In an embodiment of the present application, the second cache block can determine that the destination address matches its own cache identifier when the destination address represented by the second addressing signal is the corresponding address of the second cache block in the second bus. At this time, if there is an idle cache unit in the second cache block, the control enables the transmission signal to indicate that the write data is valid, thereby receiving the data signal and obtaining the first cache data.

[0083] In some embodiments, the data lines include 32 for transmitting 32-bit data signals; the addressing lines include 10 for transmitting 10-bit addressing signals; and the enable line includes 1 for transmitting a 1-bit transmission enable signal.

[0084] It is understandable that, since the second bus includes addressing lines, each cache block on the second bus can combine the signal on the addressing line to accurately read the first cache data on the data signal from the first cache block and write it into the second cache block, thereby improving data transmission accuracy.

[0085] In some embodiments of the present application, the first cache block is located at the first level in a multi-level storage structure; each cache block in the first level is used to store the immediate cache data of a corresponding core; the first cache block is also used to respond to read data indication information from the corresponding first core and transmit the first cache data to the second cache block through the second bus; the read data indication information represents the need of the second core to read the first cache data.

[0086] In an embodiment of the present application, multiple cache blocks in the first-level storage structure communicate with corresponding cores through the first bus. In the case where the first cache block is a cache block in the first-level storage structure, the first cache block can receive read data indication information from the corresponding first core, upload the first cache data to the second bus in response to the read data indication information, and transmit it to the second cache block through the second bus. The read data indication information is used to characterize the need for the second core to read the first cache data; the read data indication information includes a cache identifier of the second cache block corresponding to the second core.

[0087] In the embodiment of the present application, the plurality of cache blocks in the first level can be implemented as local memory, local cache, or a mixture of the two. This can be set according to actual needs, and the embodiment of the present application does not limit this.

[0088] For example, Figure 4 shows a data exchange process, such as Figure 4 As shown, the process includes:

[0089] S41, core3 sends a data exchange command to core2.

[0090] S42, core2 sends read data indication information to L312.

[0091] The read data indication information carries the cache identifier of core2.

[0092] S43, L312 sends data to L313 through the second bus.

[0093] After L312 uploads the data to the second bus, it can feedback the data read completion information to core2. Core2 then feedbacks the exchange completion information to core3, indicating that core3 can read the data.

[0094] S44, core3 reads data from L313.

[0095] During the above data exchange process, if core3 wants to read the real-time cache data of core2, it can be achieved through data transmission between L313 and L312 without having to transfer through DRAM, thereby improving the efficiency of timely cache data exchange between multiple cores.

[0096] In some embodiments of the present application, the second cache block is further used to upload first response information through the second bus after receiving the first cache data from the first cache block; the first response information indicates that the first cache data is received successfully.

[0097] In the embodiment of the present application, the second cache block feeds back the first response to the first cache block, which helps the first cache block to know whether the first cache data is sent successfully, and make the next step of processing accordingly.

[0098] In some embodiments, if the first cache block does not receive the first response within the preset response time, it can determine that the second cache block fails to receive the first cache data and re-upload the first cache data. The preset response time can be set according to actual needs and is not limited in the embodiments of the present application.

[0099] For example, Figure 4 As shown, after S43, the process may further include:

[0100] S45, L313 sends the data receiving feedback information to L312 via the second bus.

[0101] The data reception feedback information indicates that L313 successfully receives the data.

[0102] S46, L312 responds to data receiving feedback information and feeds back data reading completion information to core2.

[0103] S47, core2 feeds back exchange completion information to core3.

[0104] S44, core3 reads data from L313

[0105] Among them, core2 can feedback the exchange completion information to core3 by changing the exchange indication label flag. For example, the flag defaults to 0. After core2 receives the data reception feedback information from L312, it can change the flag to 1. When core3 reads the flag and finds that the flag is 1, it can know that the data exchange is completed and can read data from L313.

[0106] It is understandable that the second cache block feeds back the first response to the first cache block, so that the first cache block can timely know the reception status of the first cache data and notify other cache blocks or the GPU core to respond, thereby improving the processing efficiency of the GPU core.

[0107] In some embodiments of the present application, the second bus includes a response enable line, a response addressing line and a response status line; the first cache block is also used to receive a first response on the response status line when the response enable signal on the response enable line is valid and the destination address represented by the addressing signal on the response addressing line matches its own cache identifier.

[0108] In the embodiment of the present application, the second bus includes a response line for transmitting the first response, and the response line includes a response enable line, a response addressing line, and a response status line. The response enable line is used to transmit a response enable signal, and the response addressing signal on the response addressing line is used to characterize the response destination address of the first response; the response status line is used to transmit the reception result.

[0109] In an embodiment of the present application, the first cache block can determine that the response destination address matches its own cache identifier and obtain the reception result from the response status line when the response enable signal is valid and the response destination address represented by the response addressing signal is the corresponding address of the first cache block in the second bus.

[0110] It is understandable that the second bus is provided with a response line, which can separate the physical transmission lines of the response signal and the first cache data, so that the cache block can identify the corresponding signal through different physical transmission lines, thereby improving the signal processing efficiency of the cache block.

[0111] In some embodiments of the present application, the first cache block is located at the second level in the multi-level storage structure; the second level also includes memory blocks corresponding one to one with the cache blocks; the first cache block is also used to respond to the near memory calculation indication instruction from the second cache block, read the near memory parameters from the first memory block through the first bus, and use the near memory parameters as the first cache data; the second cache block is also used to complete the near memory calculation based on the calculation data and the near memory parameters.

[0112] In an embodiment of the present application, the multi-level storage structure includes two levels, and the second level includes multiple memory blocks corresponding to the multiple cache blocks one by one. The storage space of the memory block is larger than the cache block. Each cache block in the second level can be used to perform near memory calculations, and the near memory parameters used for the near memory calculations are stored in the first memory block. When the second cache block needs to perform near memory calculations, it can send a near memory calculation indication instruction to the first cache block corresponding to the first memory block through the second bus. The first cache block responds to the near memory calculation indication instruction, obtains the near memory parameters from the first memory block through the first bus, uploads the near memory parameters to the second bus, and sends them to the second cache block through the second bus.

[0113] In the embodiment of the present application, the second cache block can obtain the calculation data and complete the near memory calculation of the calculation data based on the near memory parameter. Here, the calculation data can come from any cache block of any level.

[0114] It can be understood that since multiple cache blocks in the second level can communicate through the second bus, when the near memory parameters only exist in a specific memory block, the near memory parameters can be obtained by the cache block corresponding to the memory block and sent to any cache block in the second level through the second bus, thereby reducing the delay of the cache blocks in the second level obtaining the near memory parameters and improving the data processing efficiency of the multi-core GPU.

[0115] In some embodiments of the present application, the second cache block is further used to return the near memory parameters to the first cache block through the second bus after completing the near memory calculation; the first cache block is further used to return the near memory parameters to the first memory block through the first bus.

[0116] In the embodiment of the present application, the second cache block obtains the near memory parameter from the first cache block. After completing the near memory calculation using the near memory parameter, the second cache block needs to return the near memory parameter to the first memory block for other cache blocks to perform near memory calculation. The second cache block can send the near memory parameter to the first cache block via the second bus, and then the first cache block sends it to the corresponding first memory block via the first bus.

[0117] It is understandable that any cache block in the second level needs to obtain the near memory parameters from the first memory block when performing near memory calculation. Therefore, after the near memory calculation is completed, the near memory parameters are returned to the first memory block for subsequent use by other cache blocks.

[0118] For example, Figure 5 shows a process of using the near-stored parameters, such as Figure 5 As shown, the recent parameters are stored in D3. The process includes:

[0119] When near memory calculation is needed, S51 and L322 send near memory calculation instruction to L323.

[0120] S52 and L323 obtain the recent storage parameters from D3.

[0121] S53 and L323 send the recently stored parameters to L322 via the second bus.

[0122] S54. After L322 completes the near memory calculation based on the near memory parameters, it returns the near memory parameters to L323 through the second bus.

[0123] S55 and L323 return the recently stored parameters to D3 via the first bus.

[0124] The present application embodiment provides a data interaction method, which is applied to the above-mentioned multi-core graphics processor GPU, such as Figure 6 As shown, the data interaction method includes the following steps 601 to 604:

[0125] Step 601: The second core sends a data interaction command to the first core.

[0126] Here, the second core refers to Figure 4 core3 in the first core refers to Figure 4 core2 in.

[0127] Step 602: The first core responds to the data interaction command and transmits read data indication information to the first cache block through the first bus; the read data indication information represents the need for the second core to read the first cache data.

[0128] Here, the first cache block refers to Figure 4 L312 in.

[0129] Step 603: The first cache block transmits the first cache data to the second cache block through the second bus based on the read data indication information.

[0130] Here, the second cache block refers to Figure 4 L313 in.

[0131] Step 604: The second core reads the first cache data from the second cache block.

[0132] Among them, the specific implementation method of step 604 can be: the second cache block sends the data reception feedback information to the first cache block through the second bus; the first cache block responds to the data reception feedback information and feeds back the data reading completion information to the first core; the first core feeds back the exchange completion information to the second core; the second core reads the first cache data from the second cache block.

[0133] In other embodiments, the data exchange method provided in the embodiment of the present application may further include the following steps 605 to 609:

[0134] Step 605: When the third cache block needs to perform near memory calculation, the third cache block sends a near memory calculation instruction to the fourth cache block.

[0135] Here, the third cache block may be any cache block in the second-level storage structure. For example, the third cache block may refer to Figure 5 The fourth cache block may refer to L322 in Figure 5 L323 in.

[0136] Step 606: The fourth cache block obtains the near memory parameter from the first memory block.

[0137] Here, the first memory block refers to a memory block storing near memory parameters. For example, the first memory block may refer to Figure 5 D3 in .

[0138] Step 607: The fourth cache block sends the recent storage parameters to the third cache block via the second bus.

[0139] Step 608: After the third cache block completes the near memory calculation based on the near memory parameter, the near memory parameter is returned to the fourth cache block through the second bus.

[0140] Step 609: The fourth cache block returns the recent storage parameter to the first memory block via the first bus.

[0141] The present application also provides a structure of an electronic device, such as Figure 7 As shown, the electronic device 700 includes a multi-core GPU 701 and a memory system 30. The multi-core GPU 701 and the memory system 30 are connected via a first bus.

[0142] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The serial numbers of the embodiments of the present application mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0143] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0144] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0145] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0146] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0147] The above is only an embodiment of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A memory system of a multi-core graphics processor GPU, characterized in that: The memory system includes a multi-level storage structure; the multi-level storage structures communicate with each other via a first bus; Each level of the storage structure includes a plurality of cache blocks; the plurality of cache blocks communicate with each other via a second bus; A first cache block among the multiple cache blocks of each level is used to transmit first cache data to a second cache block among the multiple cache blocks through the second bus.

2. The memory system according to claim 1, wherein: The first cache block is further used to package the cache identifier of the second cache block and the first cache data and upload them to the second bus; The other cache blocks among the multiple cache blocks except the first cache block are used to determine that they are the second cache block when the identifier of the second cache block is the same as the cache identifier of the own cache block; and receive the first cache data.

3. The memory system according to claim 2, characterized in that: The second cache block is further configured to receive the first cache data when there is a free cache unit in the second cache block.

4. The memory system according to any one of claims 1 to 3, characterized in that: The multiple cache blocks in each level of the storage structure communicate via a corresponding second bus; the cache identifier of each cache block is used to represent a unique address of the cache block in a corresponding second bus.

5. The memory system according to any one of claims 1 to 3, characterized in that: The second cache block is further used to transfer the first cache data to multiple cache blocks in the storage structure at the level where the second cache block is located through the second bus without receiving the first cache data, until the first cache data is transferred to the second cache block and the second cache block is able to receive the first cache data.

6. The memory system according to any one of claims 1 to 3, characterized in that: The second bus includes an enable line for transmitting an enable signal and a data line for transmitting data; The first cache block is further configured to generate a data signal based on the first cache data when a transmission enable signal indicates that the read data is valid; and transmit the data signal through the data line; The second cache block is further configured to receive the data signal through the data line to obtain the first cache data when the transmission enable signal indicates that the write data is valid.

7. The memory system according to claim 6, characterized in that: The second bus also includes an addressing line for transmitting an addressing signal; The second cache block is further configured to receive the data signal when the destination address indicated by the addressing signal matches its own cache identifier and the transmission enable signal indicates that the write data is valid.

8. The memory system according to any one of claims 1 to 3, characterized in that: The first cache block is located at the first level in a multi-level storage structure; each cache block in the first level is used to store the immediate cache data of a corresponding core; The first cache block is also used to respond to read data indication information from the corresponding first core and transmit the first cache data to the second cache block through the second bus; the read data indication information represents the need of the second core to read the first cache data.

9. The memory system according to any one of claims 1 to 3, characterized in that: The second cache block is further used to upload a first response through the second bus after receiving the first cache data from the first cache block; the first response represents a result of receiving the first cache data; The receiving result includes receiving success or receiving failure.

10. The memory system according to claim 9, characterized in that: The second bus includes a response enable line, a response addressing line and a response status line; The first cache block is further configured to receive the receiving result on the corresponding response status line when the response enable signal on the response enable line is valid and the destination address represented by the response addressing signal on the response addressing line matches its own cache identifier.

11. The memory system according to any one of claims 1 to 3, characterized in that: The first cache block is located at the second level in the multi-level storage structure; the second level also includes memory blocks corresponding to the cache blocks one by one; The first cache block is further used to respond to the near memory calculation instruction from the second cache block, read the near memory parameter from the first memory block through the first bus, and use the near memory parameter as the first cache data; The second cache block is further used to complete the near memory calculation based on the calculation data and the near memory parameter.

12. The memory system according to claim 11, wherein: The second cache block is further used to return the near memory parameter to the first cache block through the second bus after completing the near memory calculation; The first cache block is further used to return the near memory parameter to the first memory block through the first bus.

13. The memory system according to any one of claims 1 to 3, characterized in that: The bandwidth of the first bus is greater than the bandwidth of the second bus.

14. The memory system according to claim 13, wherein: The first bus is a crossbar switch matrix bus; the second bus is a ring bus.

15. A data exchange method, characterized in that: A memory system applied to a multi-core graphics processor GPU, the memory system comprising a multi-level storage structure; the multi-level storage structures communicate with each other via a first bus; Each level of the storage structure includes a plurality of cache blocks; The plurality of cache blocks communicate with each other via a second bus; The data exchange method comprises: The second core sends a data interaction command to the first core; The first core responds to the data interaction command and transmits the read data indication information to the first cache block through the first bus; the read data indication information represents the need of the second core to read the first cache data; The first cache block transmits the first cache data to the second cache block through the second bus based on the read data indication information; The second core reads the first cache data from the second cache block.

16. An electronic device, characterized in that: A method comprising a multi-core graphics processor (GPU) and a memory system of the multi-core GPU as claimed in any one of claims 1 to 14, wherein the multi-core GPU stores an executable computer program, and wherein the multi-core GPU implements the steps of the method of claim 15 when executing the program.

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