Device, method and system for real-time data transmission between asynchronous processors

Abstract

The present invention discloses a device, method and system for real-time data transmission between asynchronous processors. The device provided by the present invention comprises: a plurality of port modules, respectively connected to a plurality of asynchronous processors, configured to instantly receive data transfer messages sent by the plurality of asynchronous processors, wherein the data transfer messages indicate that a sender processor in the plurality of asynchronous processors is to send data to a receiver processor in the plurality of asynchronous processors; a scheduling and control module, connected to the plurality of port modules, configured to: check the plurality of port modules according to a predefined timing to obtain the data transfer message; and parse the data transfer message to determine the storage space in the storage device for the data to be sent, wherein the storage device is connected to the device; and a storage device management module, connected to the scheduling and control module, configured to write the data to be sent into the determined storage space.

Description

Technical Field

[0001] The present invention generally relates to the field of computing systems, and in particular to an apparatus, method and system for real-time data transmission between multiple asynchronous processors in a multi-processor computing system. Background Art

[0002] In recent years, the requirements for real-time performance of computing systems have become increasingly higher, which has put forward higher requirements for data transmission between various components of computing systems. Especially in multi-processor systems, in the entire data transmission link from the sending processor, the sending bus controller, the receiving bus controller to the receiving processor, a coordination mechanism is required between each link to ensure the real-time performance of the entire system and avoid data delay and loss in each link of the link. The existing technology has made many explorations to solve the problem of real-time performance of multi-processor systems.

[0003] Reference now Figure 1 1 to describe a typical multi-processor computing system 100. The computing system 100 may include multiple processors, as examples, Figure 1 The figure shows a processor 110 and a processor 120. The processors 110 and 120 may have various differences in a series of quality metrics including architecture, microarchitecture, thermal, power consumption characteristics, etc., and may include a processing unit, an operating system (OS), and an application (App).

[0004] like Figure 1 As shown in , in a multi-processor computing system 100, a processor 110 and a processor 120 are connected and communicated through an I / O bus, and the processor 110 and the processor 120 manage data communication on the I / O bus through corresponding I / O bus controllers 130 and 140, respectively. Consider a scenario where the processor 110 is a sender and the processor 120 is a receiver, that is, the processor 110 sends data to the processor 120 via the I / O bus. After receiving the data sent by the I / O bus controller 130, the I / O bus controller 140 will send an interrupt signal to notify the processor 120 to read the data. However, if the processor 120 is not ready to receive data, data overflow will occur. A typical scenario is that a processor that uses a software time-sharing multiplexing mechanism such as an ARINC 653 operating system has made great restrictions on the processor's IO interrupt-response mechanism to ensure that each software task runs according to a predetermined time plan, which will cause the processor to be unable to receive IO data. Therefore, a certain coordination mechanism is needed to alleviate this data overflow problem.

[0005] One type of prior art has made efforts in synchronizing multiple processors. For example, the prior art uses hard-wired synchronization, where the processor to be synchronized responds to a synchronization signal and serves as the starting point for the software task to run, thereby ensuring that the actions of each processor to be synchronized are consistent and solving the time coordination problem of transmission. However, hard-wired synchronization requires a complex synchronization mechanism to synchronize each processor to a consistent clock, so the design is complex and prone to errors, and failures can easily spread to multiple processors, causing the failure of the entire system.

[0006] Another type of prior art implements data exchange between processors through asynchronous dual-port memory devices, keeps each processor running in an asynchronous clock mode, and avoids complex hard-wire synchronization. For example, an asynchronous dual-port RAM (Asynchronous Dual Port Random Access Memory, Asynchronous DPRAM) is used to provide two independent data buses, address buses and read-write control lines for two processors to exchange data. However, when two processors access the same storage space in the DPRAM at the same time (such as two processors write to the same storage unit at the same time, or one processor writes to a storage unit while another processor reads the storage unit), contention for the DPRAM will occur, resulting in the read value or the written value not being the expected value, so an additional conflict resolution mechanism is required to resolve the simultaneous access conflict. In addition, the storage space of the DPRAM is limited and difficult to expand, and the transmission distance of the data line and the control line is limited, which cannot meet the application of complex systems. For another example, the prior art also uses reflective memory technology to transmit data between multiple processing nodes, wherein each processing node is inserted with a reflective memory card and connected to the reflective memory network, and a bus controller is used to manage a large-capacity local memory. When the sending processing node sends data to its local memory, the data and its storage location in the local memory will be broadcast to other processing nodes in the reflective memory network. These processing nodes will create a local copy of the data at the same location of their local reflective memory card and read the local copy to obtain the required data when needed. However, the use of this reflective memory technology requires the creation of a local copy of the data sent by each processor, which requires a special professional board, which is also complex and costly.

[0007] Therefore, a scalable and cost-effective technology is needed to support real-time data transfer between processors. Summary of the invention

[0008] The present invention is provided in order to achieve a scalable and cost-effective solution for real-time data transfer between processors.

[0009] According to one aspect of the present invention, there is provided an apparatus for real-time data transmission between multiple asynchronous processors, characterized in that it comprises: multiple port modules, respectively connected to the multiple asynchronous processors, the multiple port modules are configured to instantly receive data transfer messages sent by the multiple asynchronous processors, wherein the data transfer messages indicate that a sending processor among the multiple asynchronous processors is to send data to a receiving processor among the multiple asynchronous processors; a scheduling and control module, connected to the multiple port modules, the scheduling and control module is configured to: check the multiple port modules according to a predefined timing to obtain the data transfer messages; and parse the data transfer messages to determine a storage space in a storage device for the data to be sent, wherein the storage device is connected to the apparatus; and a storage device management module, connected to the scheduling and control module, the storage device management module is configured to write the data to be sent into the determined storage space.

[0010] The device as described above is characterized in that the data transfer message has a predefined message format, and the predefined message format is reflected by a message definition and mapping configuration table.

[0011] The device as described in any of the above items is characterized in that the predefined message format includes a message type identifier field and a payload field, wherein the value of the message type identifier field is used to uniquely identify the type of the data transfer message, and the value of the payload field indicates the transmitted data.

[0012] The device as described in any of the above items is characterized in that the scheduling and control module is further configured to: parse the data transfer message to obtain a message type identifier of the data transfer message; query the message definition and mapping configuration table based on the message type identifier to determine an entry in the message definition and mapping configuration table that matches the data transfer message; and determine the storage space based on the entry.

[0013] The device as described in any of the above items is characterized in that the storage device is a first storage device, and the message definition and mapping configuration table is a static configuration table that is pre-set and stored in a second storage device.

[0014] The device as described in any of the above items is characterized in that the device communicates with the multiple asynchronous processors through the multiple port modules via a peripheral component interconnect express (PCIe) bus, and wherein each of the multiple port modules has a corresponding block storage unit to buffer the data transfer message.

[0015] The device as described in any of the above items is characterized in that the scheduling and control module is further configured to set the predefined timing based on the transmission rate of the PCIe bus and the read and write rate of the first storage device.

[0016] The device as described in any of the above items is characterized in that the scheduling and control module is further configured to check the multiple port modules in a static time-sharing polling manner to obtain the data transfer message.

[0017] The device as described in any of the above items is characterized in that the scheduling and control module is further configured to adopt a dynamic manner to check the multiple port modules to obtain the data transfer message based on the priorities of the multiple asynchronous processors and / or based on the order in which the multiple asynchronous processors send the data transfer messages.

[0018] An apparatus as described in any of the above items, characterized in that the data transfer message indicates that the receiving processor is to receive data from the sending processor, wherein the scheduling and control module is further configured to: check the multiple port modules according to a predefined timing to obtain the data transfer message; and parse the data transfer message to determine the storage space for the received data; and the storage device management module is further configured to: read data from the determined storage space; and return the read data to the scheduling and control module; wherein the scheduling and control module further transmits the received data to the receiving processor via the corresponding port module.

[0019] An apparatus as described in any of the above items, characterized in that the data transfer message includes a port number of a target to receive data from the sending processor, wherein the scheduling and control module is further configured to: parse the port number from the data transfer message to determine whether one or more receiving processors have access rights to the determined storage space.

[0020] The device as described in any of the above items is characterized in that the storage device is implemented by a field programmable gate array FPGA.

[0021] According to another aspect of the present invention, a method for real-time data transmission between multiple asynchronous processors is provided, characterized in that it includes: promptly receiving data transfer messages sent by the multiple asynchronous processors, wherein the data transfer message indicates that a sending processor among the multiple asynchronous processors is to send data to a receiving processor among the multiple asynchronous processors; processing the data transfer message according to a predefined timing to determine a storage space in a storage device for the data to be sent; and writing the data to be sent into the determined storage space.

[0022] The method as described above is characterized in that the data transfer message has a predefined message format, and the predefined message format is reflected by a message definition and a mapping configuration table.

[0023] A method as described in any of the above items, characterized in that the predefined message format includes a message type identifier field and a payload field, wherein the value of the message type identifier field is used to uniquely identify the type of the data transfer message, and the value of the payload field indicates the transmitted data.

[0024] A method as described in any of the above items, characterized in that the method further includes: parsing the data transfer message according to the predefined timing to obtain a message type identifier of the data transfer message; querying the message definition and mapping configuration table based on the message type identifier to determine an entry in the message definition and mapping configuration table that matches the data transfer message; and determining the storage space based on the entry.

[0025] The method as described in any one of the above items is characterized in that the method further comprises: buffering the data transfer message in a block storage unit associated with a processor among the multiple asynchronous processors that issues the data transfer message.

[0026] A method as described in any of the above items, characterized in that the data transfer message indicates that the receiving processor is to receive data from the sending processor, wherein the method further includes: processing the data transfer message according to a predefined timing to determine a storage space for the received data; reading data from the determined storage space; and transmitting the read data to the receiving processor.

[0027] A method as described in any of the above items, characterized in that the data transfer message includes a port number of a target to receive data from the sending processor, wherein the method further includes: parsing the port number from the data transfer message to determine whether one or more receiving processors have access rights to the determined storage space.

[0028] According to another aspect of the present invention, there is provided a computing system, characterized in that it comprises: a plurality of asynchronous processors; a device as described in any one of the above items, the device being connected to the plurality of asynchronous processors; and the storage device.

[0029] The apparatus, method and system for real-time data transmission between multiple asynchronous processors according to the embodiments of the present invention are easily scalable and cost-effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Some examples of apparatus and / or methods will be described below by way of example only and with reference to the accompanying drawings, in which:

[0031] Figure 1 FIGURE 1 is a block diagram of a multiprocessor system;

[0032] Figure 2 A block diagram illustrating a multi-processor system according to an embodiment of the present invention;

[0033] Figure 3 A block diagram illustrating an apparatus for real-time data transmission between multiple asynchronous processors according to an embodiment of the present invention;

[0034] Figure 4 Schematically illustrates storage space allocation according to an embodiment of the present invention;

[0035] Figure 5 A flow chart illustrating a method for real-time data transmission between multiple asynchronous processors according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In the following description, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description.

[0037] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0038] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0039] In the following description and claims, the term "connected" and its derivatives may be used. In certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. However, "connected" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0040] As modern applications have increasingly higher computing requirements, computing systems that only include a single processor often cannot meet application requirements, and the use of multi-processor computing systems is becoming increasingly common. A typical multi-processor computing system usually includes multiple processors that communicate with each other, and these processors execute their corresponding workloads and communicate with each other.

[0041] Figure 2 FIG. 2 shows a multi-processor computing system 200 according to an embodiment of the present invention, in which the data transmission coordination mechanism proposed by the present invention is adopted. Figure 2 As shown, computing system 200 includes multiple processors for illustrative purposes only. Figure 2 Processors 212, 214, 216 are shown, but those skilled in the art will appreciate that system 200 may include more Figure 2 According to an embodiment of the present invention, the processors 212, 214, 216 communicate via the coordination device 220, and communicate with the storage device 230 via the coordination device 220.

[0042] According to an embodiment of the present invention, processors 212, 214, 216 can actively send data to coordination device 220 and actively read data from coordination device 220, that is, processors 212, 214, 216 can send data to coordination device 220 and / or receive data from coordination device 220 at any required time. For illustrative purposes only, processor 212 is described below as a sender processor, that is, a processor that sends data at any required time; and processors 214 and processor 216 are described as receiver processors, that is, processors that receive data at any required time.

[0043] During operation, the processor 212 actively sends a data transfer message including data A to the coordination device 220. The coordination device 220 promptly receives the data transfer message, sets a storage space in the storage device 230 for storing data A according to the data transfer message, and stores the received data A in the set storage space.

[0044] When the processor 214 and / or the processor 216 need to read data A, the processor 214 and / or the processor 216 sends a data transfer message to the coordination device 220. The coordination device 220 receives the data transfer message immediately, determines the storage space where the data A is located according to the data transfer message, reads the data A from the storage space, and transfers the data A to the processor 214 and / or the processor 216. That is, the coordination device 220 provides coordination for processor data transmission and processor data reception, which can solve the time difference problem between processor data reception and processor data transmission. Therefore, through the coordination device 220, the processors 212, 214, and 216 do not need to be synchronized by interrupt-response. In addition, the coordination device 220 can buffer the received data transfer message and process the data requests of the processors 212, 214, and 216 based on a predefined timing and / or a predefined order, thereby avoiding the contention of the processors for the storage space, thereby avoiding memory access conflicts.

[0045] In some embodiments, the storage device 230 may be an external storage device; in other embodiments, the storage device 230 may also be a storage device inside the coordination device 220. The storage device 230 may be easily expandable, so as to be well adapted to complex system applications.

[0046] exist Figure 2 In the embodiment shown in , the processors 212, 214, 216 transmit data via the coordination device 220, and each processor itself does not need to make hardware changes; the coordination device 220 only uses the storage device 230 to temporarily store data, and does not need to perform complex calculations, so there is no need to use complex hardware settings. As a preferred embodiment, a field programmable gate array (FPGA) can be used to implement such a coordination device 220.

[0047] Figure 3 1 shows a block diagram of a multi-processor computing system 300 according to an embodiment of the present invention, wherein the details of each module of the coordination device 320 are shown in detail. Figure 3 Only three processors 310a, 310b, and 310c are illustrated in FIG. 1 , and the processor 310a is described as a transmitting-side processor, and the processors 310b and 310c are described as receiving-side processors.

[0048] like Figure 3 As shown, the coordination device 320 is connected to the processors 310a, 310b, and 310c. More specifically, the coordination device 320 is communicatively connected to the corresponding port modules 312a, 312b, and 312c in the processors 310a, 310b, and 310c through its port modules 322a, 322b, and 322c, respectively. As a non-limiting embodiment, the coordination device 320 can be connected to the processors 310a, 310b, and 310c via a peripheral component interconnect express (PCIe) bus. In this case, the multiple port modules 322a, 322b, and 322c of the coordination device 320 can be implemented as PCIe endpoint (EndPoint, EP) modules. These PCIe EP modules are connected to the corresponding processors 310a, 310b, and 310c via the PCIe bus, respectively. More specifically, the corresponding port modules 312a, 312b, 312c of the processors 310a, 310b, and 310c may be implemented as PCIe root complex (RC) modules, and the PCIe EP module is connected to the corresponding PCIe RC module via a PCIe bus.

[0049] Reference to above Figure 2 Similar to the description, the processors 310a, 310b, 310c may actively send data transfer messages to the coordination device 320. Specifically, refer to Figure 3 As a sending processor, the processor 310a can actively send a data transfer message including data A to the coordination device 320 via its port module 312a. According to an embodiment of the present invention, the coordination device 320 instantly receives the data transfer message via the port module 322a connected to the port module 312a of the processor 310a. Similarly, as receiving processors, the processors 310b and 310c can actively send corresponding data transfer messages to the coordination device 320 via their port modules 312b and 312c, respectively, and the coordination device 320 instantly receives the data transfer messages via their port modules 322b and 322c, respectively.

[0050] Continue to refer Figure 3 According to an embodiment of the present invention, the coordination device 320 may further include a scheduling and control module 324, which is used to schedule and control the processing of data transfer messages. Specifically, the scheduling and control module 324 may obtain the data transfer messages received by the port modules 322a, 322b, and 322c from the port modules.

[0051] According to an embodiment of the present invention, the scheduling and control module 324 can act as a master to obtain data transfer messages from the port modules 322a, 322b, 322c acting as slaves, that is, the scheduling and control module 324 can access each port module 322a, 322b, 322c based on a predefined timing.

[0052] In some embodiments, the scheduling and control module 324 may sequentially access each port module 322a, 322b, 322c in a time-sharing polling manner, wherein the polling time slice may be appropriately set based on the time for the scheduling and control module 324 to process the data transfer message. For example, the scheduling and control module 324 may first poll the port module 322a, thereby obtaining the data transfer message received by the port module 322a and processing the data transfer message. At this time, if the port module 322b and / or the port module 322c have received the data transfer message, the port module 322b and / or the port module 322c respectively buffers the data transfer message received to wait for the next round of polling.

[0053] In some embodiments, the port modules 322a, 322b, 322c each have a dedicated block storage unit 350a, 350b, 350c. According to an embodiment of the present invention, the port module 322a can buffer the data transfer message it receives into its dedicated block storage unit 350a, the port module 322b can buffer the data transfer message it receives into its dedicated block storage unit 350b, and similarly, the port module 322c can buffer the data transfer message it receives into its dedicated block storage unit 350c.

[0054] According to an embodiment of the present invention, when the scheduling and control module 324 polls the port module 322a, the block storage unit 350a dedicated to the port module 322a is accessed to obtain the data transfer message buffered therein from the block storage unit 350a. Similarly, when the scheduling and control module 324 polls the port module 322b, the block storage unit 350b dedicated to the port module 322b is accessed to obtain the data transfer message buffered therein from the block storage unit 350b dedicated to the port module 322b; when the scheduling and control module 324 polls the port module 322c, the block storage unit 350c dedicated to the port module 322c is obtained from the data transfer message buffered therein.

[0055] As an alternative embodiment, the port modules 322a, 322b, 322c may receive the data transfer message and keep the received data transfer message in the port modules 322a, 322b, 322c until the scheduling and control module 324 polls the corresponding port module.

[0056] Therefore, by means of static time scheduling, the scheduling and control module 324 can effectively prevent conflicts between the multiple processors 310a, 310b, and 310c.

[0057] According to an embodiment of the present invention, the scheduling and control module 324 first parses the acquired data storage request message. According to an embodiment of the present invention, the data transfer message has a predefined format, which can be reflected by a predefined message definition and mapping configuration table. Thus, the scheduling and control module 324 can set the storage space based on the received data transfer message according to the message definition and mapping configuration table.

[0058] As a non-limiting example, the following Table 1 shows an example of a predefined message definition and mapping configuration table.

[0059]

[0060] To simplify the description, in the example shown in Table 1, it is assumed that the new data sent by the sending processor will overwrite the original data in the corresponding storage space set by the coordination device, even if the original data has not been read by the receiving processor. As a non-limiting embodiment, for applications where both the original data and the new data need to be read by the receiving processor, the scheduling and control module 324 can manage the storage space in a queue manner, and accordingly, the corresponding queue information is additionally recorded in the predefined message definition and mapping configuration table. As shown in Table 1, the example predefined message definition and mapping configuration table records: a message type identifier (identifier, ID), which is used to uniquely identify the type of data transfer message sent by the processor; a "source port", which is used to indicate the source of the data, that is, to indicate which processor of the multiple processors the data comes from, for example, as shown in Table 1, the source port 0x01 indicates processor 310a, and the source port 0x02 indicates processor 310b; a "destination port", which is used to indicate the destination of the data, that is, to indicate which and / or which processors of the multiple processors the data is to be received by, for example, as shown in Table 1, the destination port 0x01 indicates processor 310a, and the source port 0x02 indicates processor 310b; a "destination port", which is used to indicate the destination of the data, that is, to indicate which and / or which processors of the multiple processors the data is to be received by, for example, as shown in Table 1, the destination port 0x02 indicates processor 310b. 0x02 indicates processor 310b, and destination port 0x05 indicates processors 310a and 310c; "data length" is used to indicate the length of the data to be written and / or to be queried (for example, the length in bytes); "starting address" is used to indicate the starting address of the storage space allocated for the data; and "ending address" is used to indicate the ending address of the storage space allocated for the data, wherein the data sent by the sending processor is written to the storage space defined by the "starting address" and "ending address", and / or the data to be queried by the receiving processor is taken out from the storage space defined by the "starting address" field and the "ending address" field.

[0061] Alternatively, in other embodiments, such message definition and mapping configuration table having more or fewer items than those shown in Table 1 may be defined according to actual needs, or the format of the data transfer message and the storage space mapping may be reflected with different values ​​than those shown in Table 1. According to a further embodiment of the present invention, the message definition and mapping configuration table may be a static configuration table pre-set according to a specific application scenario, and the configuration table may be stored in the coordination device 320 or in a storage device outside the coordination device 320. As an example, the storage device may be implemented as a NOR flash memory to enable fast reading of the configuration table.

[0062] Specifically, once the computing system 300 is configured to execute a certain application, it is easy to determine the workload to be executed by each processor in the computing system 300, the related timing of each processor, and the data communication scenario involved between the processors. Thus, the developer can pre-set a static configuration table based on the application scenario of the computing system 300 (or more specifically, the coordination device 320).

[0063] According to an embodiment of the present invention, the predefined message definition and mapping configuration table may be pre-programmed in the scheduling and control module 324. Alternatively, as an alternative embodiment, Figure 3 As shown, the coordination device 320 may further include a storage device management module 328, and the coordination device 320 is connected to the storage device 340 via the storage device management module 328. The storage device 340 is used to store predefined message definitions and mapping configuration tables, and the storage device management module 328 is used to read the predefined configuration table from the storage device 340 in response to the instruction of the scheduling and control module 324. As a non-limiting embodiment, the storage device 340 may be implemented as a volatile storage device, a non-volatile storage device, a flash memory, etc.

[0064] As described above, the data transfer message has a predefined format. As a non-limiting example, the data transfer message may have a message type ID field for indicating the message type ID of the data transfer message. Additionally, the data transfer message may also have a payload field for carrying the transferred data.

[0065] like Figure 3 As shown, the coordination device 320 may further include a storage device management module 326. The storage device management module 326 is used to manage the storage space in the storage device 330 and access the corresponding storage space in the storage device based on the instruction of the scheduling and control module 324.

[0066] The present invention is described in detail below with reference to a case where the sending-side processor 310 a periodically reads temperature data measured by a temperature sensor and sends the read temperature data to the receiving-side processor 310 b as an example.

[0067] According to a non-limiting embodiment of the present invention, when the sender processor 310a needs to send the temperature data it reads, the sender processor 310a sends a data transfer message to the coordination device 320. Specifically, the sender processor 310a can actively send a data transfer message carrying temperature data to the coordination device 320 via the port module 312a at any required time.

[0068] According to a non-limiting embodiment of the present invention, the coordination device 320 passively receives the data transfer message from the sender processor 310a via the port module 322a. Further, the port module 322a can buffer the data transfer message in a block storage unit 350a dedicated to the port module 322a.

[0069] Subsequently, according to a non-limiting embodiment of the present invention, the scheduling and control module 324 may obtain the data transfer message buffered therein from the block storage unit 350a at a predefined timing, and parse the data transfer message to obtain the message type ID 0x03 indicated in its message type ID field and the temperature data carried by the payload field. As an example, the scheduling and control module 324 may search the predefined message definition and mapping configuration table based on the message type ID 0x03, and determine the entry corresponding to the data transfer message in the predefined message definition and mapping configuration table (i.e., the example 1 entry shown in Table 1). Further, based on the fact that the data transfer message is sent by the processor 310a, that is, corresponding to the source port 0x01 in Example 1, the scheduling and control module 324 may thereby determine that the data transfer message indicates a data write request to the scheduling and control module 324. In addition, by searching the predefined message definition and mapping configuration table, the scheduling and control module 324 can also determine the storage space indicated in the corresponding entry and allocated for the temperature data (in this example, the corresponding entry indicates that the allocated storage space has a starting address of 0x6000FF00 and an ending address of 0x6000FF1F). Thus, according to an embodiment of the present invention, based on the message type ID (e.g., 0x03) of the data transfer message, the scheduling and control module 324 can search for an entry corresponding to the message type ID in the predefined message definition and mapping configuration table, and can further determine the starting address 0x6000FF00 and the ending address 0x6000FF1F of the storage space allocated for the temperature data carried in the data transfer message. In this case, the scheduling and control module 324 can instruct the storage device management module 326 to write the temperature data into the storage space S1 defined by the starting address 0x6000FF00 and the destination address 0x6000FF1F.

[0070] The above describes the message data transmission between the sender side and the coordination device according to an embodiment of the present invention. The following will further describe the query of temperature data by the receiver side through the coordination device according to an embodiment of the present invention.

[0071] According to a non-limiting embodiment of the present invention, when the receiving processor 310b needs temperature data, the receiving processor 310b can send a data transfer message to the coordination device 320. Specifically, the receiving processor 310b can actively send a data transfer message to the coordination device 320 via the port module 312b at any required time.

[0072] According to a non-limiting embodiment of the present invention, the coordination device 320 passively receives the data transfer message from the receiving processor 310b via the port module 322b. Further, the port module 322b can buffer the data transfer message in a block storage unit 350b dedicated to the port module 322b.

[0073] Subsequently, according to a non-limiting embodiment of the present invention, the scheduling and control module 324 may obtain the data transfer message buffered therein from the block storage unit 350b at a predefined timing, and parse the data transfer message to obtain the message type ID 0x03 indicated in its message type ID field and the payload field (in this case, the payload field is empty). As an example, the scheduling and control module 324 may search the predefined message definition and mapping configuration table based on the message type ID 0x03, and determine the entry corresponding to the data transfer message in the predefined message definition and mapping configuration table (i.e., the example 1 entry shown in Table 1). Further, based on the fact that the data transfer message is sent by the processor 310b, that is, corresponding to the destination port 0x02 in Example 1, the scheduling and control module 324 may thereby determine that the data transfer message indicates a data query request to the scheduling and control module 324. In addition, by searching the predefined message definition and mapping configuration table, the scheduling and control module 324 can also determine the storage space where the data queried by the receiving processor 310b is located as indicated in the corresponding entry (in this example, the corresponding entry indicates that the starting address of the allocated storage space is 0x6000FF00 and the ending address is 0x6000FF1F). Therefore, according to an embodiment of the present invention, based on the message type ID (e.g., 0x03) of the data transfer message, the scheduling and control module 324 can search for the entry corresponding to the message type ID in the predefined message definition and mapping configuration table, and can further determine the starting address 0x6000FF00 and the ending address 0x6000FF1F of the storage space. In this case, the scheduling and control module 324 can instruct the storage device management module 326 to read the corresponding temperature data from the storage space S1 defined by the starting address 0x6000FF00 and the destination address 0x6000FF1F. Subsequently, the scheduling and control module 324 may transmit the temperature data read by the storage device management module 326 to the port module 312b of the receiving processor 310b via the corresponding port module 322b. According to a non-limiting embodiment of the present invention, the scheduling and control module 324 may buffer the temperature data read by the storage device management module 326 in a block storage unit 350b dedicated to the port module 322b.

[0074] Thus, via the coordination device 320 , the receiving processor 310 b can actively query the required temperature data from the storage space managed by the coordination device 320 at any time when it needs the temperature data.

[0075] The present invention will be described in detail below with reference to a case where the sending-side processor 310b periodically reads humidity data measured by the humidity sensor and sends the read humidity data to the receiving-side processors 310a and 310c as another example.

[0076] Different from the case described herein where the sender processor 310a sends temperature data to the receiver processor 310b (i.e., the case where the sender processor and the receiver processor perform one-to-one data transmission), the receiver processors 310a and 310c both need to query humidity data for further processing (i.e., a one-to-many data transmission form between the sender processor and the receiver processor). The message data transmission between the sender side and the coordination device will not be described in detail below.

[0077] According to a non-limiting embodiment of the present invention, when the receiving processor 310a, 310c needs humidity data, the receiving processor 310a, 310c can send a data transfer message to the coordination device 320. Specifically, the receiving processor 310a, 310c can actively send a data transfer message to the coordination device 320 via the port modules 312a, 312c at any required time.

[0078] According to a non-limiting embodiment of the present invention, the coordination device 320 passively receives data transfer messages from the receiving processors 310a and 310c via the port modules 322a and 322c. Further, the port module 322a can buffer the data transfer messages received from the receiving processor 310a in a block storage unit 350a dedicated to the port module 322a, and the port module 322c can buffer the data transfer messages received from the receiving processor 310c in a block storage unit 350c dedicated to the port module 322c.

[0079] Subsequently, according to a non-limiting embodiment of the present invention, the scheduling and control module 324 may poll the block storage units 350a and 350c in sequence according to a predefined timing to obtain the data transfer message buffered therein. When the scheduling and control module 324 polls the block storage unit 350a, the scheduling and control module 324 obtains the data transfer message buffered therein and received from the receiving processor 310a, and may process the data transfer message. Specifically, the scheduling and control module 324 may parse the data transfer message to obtain the message type ID 0x12 indicated in its message type ID field and the payload field (in this case, the payload field is empty). As an example, the scheduling and control module 324 may search the predefined message definition and mapping configuration table based on the message type ID 0x12 to determine the entry corresponding to the data transfer message in the predefined message definition and mapping configuration table (i.e., the example 2 entry shown in Table 1). Further, based on the fact that the data transfer message is sent by the processor 310a, that is, corresponding to the destination port 0x05 in Example 1 (which indicates that the recipient is the processor 310a, 310c), the scheduling and control module 324 can thereby determine that the data transfer message indicates a data query request to the scheduling and control module 324. In addition, by searching the predefined message definition and mapping configuration table, the scheduling and control module 324 can also determine the storage space where the data queried by the receiving processor 310a indicated in the corresponding entry is located (in this example, the corresponding entry indicates that the starting address of the allocated storage space is 0x6FFFFF00 and the ending address is 0x6FFFFF7F). Therefore, according to an embodiment of the present invention, based on the message type ID (e.g., 0x12) of the data transfer message, the scheduling and control module 324 can search for an entry corresponding to the message type ID in the predefined message definition and mapping configuration table, and can then determine the starting address 0x6FFFFF00 and the ending address 0x6FFFFF7F of the storage space. In this case, the scheduling and control module 324 may instruct the storage device management module 326 to read the corresponding humidity data from the storage space S2 defined by the starting address 0x6FFFFF00 and the ending address 0x6FFFFF7F. Subsequently, the scheduling and control module 324 may transmit the temperature data read by the storage device management module 326 to the port module 312a of the receiving processor 310a via the corresponding port module 322a. According to a non-limiting embodiment of the present invention, the scheduling and control module 324 may buffer the temperature data read by the storage device management module 326 in the block storage unit 350a dedicated to the port module 322a. Subsequently, the scheduling and control module 324 may poll the block storage unit 350c to obtain the data transfer message buffered therein and received from the receiving processor 310c, and may process the data transfer message.The processing of the data transfer message by the scheduling and control module 324 is similar to the processing of the data transfer message sent by the processor 310a described above.

[0080] Thus, via the coordination device 320, the receiving processors 310a and 310c can actively query the required temperature data from the storage space managed by the coordination device 320 at any time when they need the temperature data. Therefore, by setting an entry with a destination item value indicating multiple receiving processors in the predefined message definition and mapping configuration table, the multiple receiving processors can read the same storage space, that is, realize data transmission from one sending processor to multiple receiving processors.

[0081] According to an embodiment of the present invention, the scheduling and control module 324 can perform permission management for data transmission based on the data transfer message. As an example, by searching the predefined message definition and mapping configuration table, the scheduling and control module 324 can determine the processor with permission to access the corresponding storage space based on the value of the destination port item indicated by the entry in the configuration table that matches the message type ID of the data transfer message. When the receiving processor that sends the data transfer message is not reflected in the destination indicated by the value of the corresponding destination port item in the message definition and mapping configuration table, the receiving processor does not have the access right to the storage space it wants to access, and the scheduling and control module 324 can prevent the receiving processor from accessing the corresponding storage space.

[0082] Figure 4 The allocation of storage space in the storage device 330 is schematically shown. The storage device 330 may be Figure 3 The storage device 330 in.

[0083] like Figure 4 As shown, the storage device 330 has multiple storage spaces S1, S2, ..., SN. These storage spaces may be continuous or discontinuous. Figure 3 As described, the storage device management module 326 manages the allocation of these storage spaces S1, S2...SN based on the instructions of the scheduling and control module 324, that is, writes to and / or reads from the corresponding storage spaces S1, S2...SN.

[0084] In some embodiments, the storage device 330 may be implemented as a double data rate (DDR) storage device. In this case, since the read and write speed of the DDR storage device is relatively high (for example, when the PCIe bus is used to connect the processor 310 and the coordination device 320, the transmission rate of the PCIe bus is much lower than the read and write rate of the DDR storage device), the time difference between the time spent on reading the DDR storage device and the transmission time of the data transfer message between the processor 310a, 310b, 310c and the coordination device 320 can be used to compensate for the processing of the data transfer message by the coordination device 320. Therefore, based on the reading speed of the storage device actually used and the transmission speed of the bus between the processor 310a, 310b, 310c and the coordination device 320, the conflict can be further avoided by appropriately setting the timing of the scheduling and control module 324 obtaining the data transfer message from the port module.

[0085] Specifically, as mentioned above Figure 3 As described, in some embodiments, the scheduling and control module 324 may use static fixed time polling to poll each port module in turn to obtain data transfer messages, and the polling time slice needs to be set to be greater than the storage space setting delay. In addition, when matching the reading rate of the DDR storage device with the reading rate of the PCIe bus, factors such as the size setting of the block storage unit corresponding to the port module, the length of the payload of the message, and the sending frequency must also be considered. In other embodiments, for other specific application scenarios, it is also possible to consider using a dynamic method to check each port module to obtain data transfer messages. This dynamic method is based on the priority of each asynchronous processor in the computing system (for example, preferentially obtaining data transfer messages from a port module with a higher priority) and the order in which the asynchronous processor sends the data transfer message (for example, using a first-come, first-served dynamic management method). When using such a dynamic management method, the setting of the predefined timing usually needs to take into account the rate matching between the PCIe bus transmission and the reading and writing of the storage device, and avoid the exclusive use of resources by a specific PCIe channel.

[0086] According to an embodiment of the present invention, overall, the processor acts as the master and the coordination device acts as the slave, so that the processor can send and / or receive data at any required time. Inside the coordination device, the scheduling and control module acts as the master and the port module and the storage device management module act as the slave, so that the scheduling and control module can perform scheduling based on a predefined timing.

[0087] Therefore, the technical solution proposed by the present invention can realize the real-time transmission of data between processors, effectively avoid conflicts, and do not need to synchronize the processors. In addition, using the technical solution proposed by the present invention, a hardware setting adapted to the actual application needs can be selected, for example, the storage device used can be easily expanded based on a specific application scenario, and programming can be performed based on a specific application scenario, so that the technical solution proposed by the present invention has good scalability and can be adapted to various complex system applications.

[0088] Now turn to Figure 5 , Figure 5 A flow chart of a method 500 for real-time data transmission between multiple asynchronous processors according to an embodiment of the present invention is illustrated.

[0089] The method 500 may include, at block 502 , promptly receiving data transfer messages sent by a plurality of asynchronous processors.

[0090] According to an embodiment of the present invention, multiple asynchronous processors send data transfer messages in an active manner. Specifically, a sender processor among the multiple asynchronous processors can send a data transfer message including data A at any desired time, indicating that the sender processor is to send data A to a receiver processor among the multiple asynchronous processors. Similarly, a receiver processor among the multiple asynchronous processors can also send a data transfer message at any desired time, indicating that the receiver processor is to receive data from the sender processor. Thus, multiple asynchronous processors can send data transfer messages in an active manner at any desired time, and these data transfer messages are received immediately.

[0091] The method 500 may include, at block 504, processing the received data transfer message with a predetermined timing.

[0092] According to an embodiment of the present invention, after the data transfer messages sent by multiple processors are received immediately, these data transfer messages can be buffered in a specific block storage unit to be retrieved and processed according to a predetermined timing.

[0093] According to an embodiment of the present invention, a polling method can be used to sequentially access block storage units associated with multiple processors. For example, the first block storage unit associated with the first processor can be polled first, thereby obtaining the data transfer message buffered in the block storage unit and processing the data transfer message. At this time, if other data transfer messages sent by other processors have been received, these data transfer messages can be buffered in other block storage units associated with these other processors, respectively, to wait for the next round of polling. Thus, through static time scheduling, the scheduling and control module effectively prevents conflicts between multiple processors.

[0094] In addition, according to an embodiment of the present invention, the data transfer message may have a predefined message format, and this message format may be reflected by a predefined message definition and mapping configuration table. Thus, the storage space for the transmitted data can be determined based on the received data transfer message according to the message definition and mapping configuration table.

[0095] As a non-limiting example, a data transfer message may have a message type ID field and a payload field, wherein the value of the message type ID field is used to uniquely identify the type of the data transfer message, and the payload field is used to carry the transmitted data. Thus, processing the data transfer message includes parsing the data transfer message to obtain the message type ID and the payload of the data transfer message.

[0096] Further, according to an embodiment of the present invention, based on the message type ID of the data transfer message, a predefined message definition and mapping configuration table can be searched to determine the entry corresponding to the data transfer message in the predefined message definition and mapping configuration table, and the indication of the allocated storage space in the entry can be read.

[0097] The method 500 may include, at block 506 , accessing the storage space determined at block 504 .

[0098] Take as an example a case where a sending processor periodically reads temperature data measured by a temperature sensor and sends the read temperature data to a receiving processor.

[0099] According to a non-limiting embodiment of the present invention, the sender processor sends a data transfer message including temperature data in an active manner, and the data transfer message is received immediately. Subsequently, the data transfer message can be parsed according to a predefined timing to obtain the message type ID 0x03 indicated in its message type ID field and the temperature data carried by the payload field. According to an embodiment of the present invention, the predefined message definition and mapping configuration table can be searched based on the message type ID 0x03 to determine the entry corresponding to the data transfer message in the predefined message definition and mapping configuration table (i.e., the example 1 entry shown in Table 1). Thus, by searching the predefined message definition and mapping configuration table, it can be determined that the starting address of the storage space allocated for the temperature data indicated in the corresponding entry is 0x6000FF00 and the ending address is 0x6000FF1F. According to an embodiment of the present invention, based on the message type ID (e.g., 0x03) of the data transfer message, an entry corresponding to the message type ID can be found in the predefined message definition and mapping configuration table, and the starting address 0x6000FF00 and the ending address 0x6000FF1F of the storage space allocated for the temperature data carried in the data transfer message can be determined. In this case, the temperature data can be written into the determined storage space S1 defined by the starting address 0x6000FF00 and the destination address 0x6000FF1F.

[0100] Further, according to a non-limiting embodiment of the present invention, when the receiving processor needs temperature data, the receiving processor can actively send a data transfer message, and the data transfer message is received immediately. Subsequently, according to a non-limiting embodiment of the present invention, the data transfer message can be parsed according to a predefined timing, so as to obtain the message type ID 0x03 indicated in its message type ID field and the payload field (in this case, the payload field is empty). According to an embodiment of the present invention, the predefined message definition and mapping configuration table can be searched based on the message type ID 0x03 to determine the entry corresponding to the data transfer message in the predefined message definition and mapping configuration table (i.e., the example 1 entry shown in Table 1). Thus, by searching the predefined message definition and mapping configuration table, it can be determined that the starting address of the storage space where the data queried by the receiving processor is located indicated in the corresponding entry is 0x6000FF00 and the ending address is 0x6000FF1F. In this case, the corresponding temperature data may be read from the storage space S1 defined by the start address 0x6000FF00 and the destination address 0x6000FF1F, and then the read temperature data may be transferred to the receiving processor. According to a non-limiting embodiment of the present invention, the read temperature data may also be buffered in a block storage unit.

[0101] Additionally, the following refers to a case where a transmitting processor periodically reads humidity data measured by a humidity sensor and transmits the read humidity data to a plurality of receiving processors as another example.

[0102] Unlike the case where the sending processor sends temperature data to the receiving processor (i.e., the case where the sending processor and the receiving processor perform one-to-one data transmission), there are multiple receiving processors that need to query humidity data for further processing (i.e., a one-to-many data transmission form between the sending processor and the receiving processor). The message data transmission on the receiving side will be further described below.

[0103] According to a non-limiting embodiment of the present invention, when multiple receiving processors need humidity data, these receiving processors can actively send data transfer messages, and these data transfer messages are received instantly. Further, the received data transfer messages can be buffered in corresponding block storage units.

[0104] Subsequently, according to a non-limiting embodiment of the present invention, the data transfer message may be processed according to a predefined timing. Specifically, each block storage unit may be polled in turn to obtain the data transfer message buffered therein in turn and process it. For example, when polling to a block storage unit, the data transfer message in the block storage unit is taken out and processed, while the other block storage units wait for the next round of polling. According to an embodiment of the present invention, the taken out data transfer message may be parsed to obtain the message type ID 0x12 indicated in its message type ID field and the payload field (in this case, the payload field is empty). As an example, the predefined message definition and mapping configuration table may be searched based on the message type ID 0x12 to determine the entry corresponding to the data transfer message in the predefined message definition and mapping configuration table (i.e., the example 2 entry shown in Table 1). Further, by searching the predefined message definition and mapping configuration table, it may be determined that the starting address of the storage space where the data queried by the receiving processor is located indicated in the corresponding entry is 0x6FFFFF00 and the ending address is 0x6FFFFF7F. In this case, the corresponding humidity data can be read from the storage space S2 defined by the starting address 0x6FFFFF00 and the ending address 0x6FFFFF7F. Subsequently, the read temperature data can be transferred to the corresponding receiving processor. According to a non-limiting embodiment of the present invention, the read temperature data can also be buffered in the corresponding block storage unit. Subsequently, the next block storage unit can be polled to obtain the data transfer message received from another receiving processor buffered therein, and the data transfer message can be processed.

[0105] Thus, multiple receiving processors can actively query the required temperature data any time they need temperature data.

[0106] In addition, according to a further embodiment of the present invention, the method 500 can further implement the authority management of data transmission. As an example, by searching the predefined message definition and mapping configuration table, the processor with the authority to access the corresponding storage space to receive the data stored therein can be determined based on the value of the destination port item indicated by the entry matching the data transfer message in the configuration table. When the destination reflected by the value of the destination port item indicated by the entry matching the data transfer message in the message definition and mapping configuration table is different from the processor that issued the data transfer message, the access to the corresponding storage space can be blocked.

[0107] According to an embodiment of the present invention, in addition to the one-to-one data transmission between the sending processor and the receiving processor described above, the embodiment of the present invention also supports a one-to-many data transmission form between the sending processor and the receiving processor.

[0108] The systems and devices described in the embodiments of the present invention may be implemented in the form of hardware, software or a combination thereof.

[0109] Program code can be applied to input instructions to perform the functions described herein and generate output information. Output information can be applied to one or more output devices in a known manner. For the purpose of this application, control system includes any system with a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC) or a microprocessor. Program code can be implemented with a high-level process programming language or an object-oriented programming language to communicate with the control system.

[0110] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic within a processor, which when read by a machine causes the machine to fabricate logic for performing the techniques described herein.

[0111] The preferred embodiments of the present invention are described in detail above. However, it should be understood that the present invention can be implemented in various ways and variations without departing from its broad spirit and scope. A person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should fall within the scope of protection determined by the claims of the present invention.

Claims

1. A device for real-time data transmission between multiple asynchronous processors, characterized in that: include: A plurality of port modules, respectively connected to the plurality of asynchronous processors, the plurality of port modules being configured to promptly receive data transfer messages sent by the plurality of asynchronous processors, wherein the data transfer messages indicate that a sending processor among the plurality of asynchronous processors is to send data to a receiving processor among the plurality of asynchronous processors; A scheduling and control module connected to the plurality of port modules, the scheduling and control module being configured to: Checking the plurality of port modules according to a predefined timing to obtain the data transfer message; and parsing the data transfer message to determine storage space in a storage device for the data to be sent, wherein the storage device is connected to the device; and A storage device management module is connected to the scheduling and control module, and is configured to write the transmitted data into the determined storage space.

2. The device according to claim 1, characterized in that The data transfer message has a predefined message format, and the predefined message format is reflected by a message definition and mapping configuration table.

3. The device according to claim 2, characterized in that The predefined message format includes a message type identifier field and a payload field, wherein a value of the message type identifier field is used to uniquely identify the type of the data transfer message, and a value of the payload field indicates the transmitted data.

4. The device according to claim 3, characterized in that The scheduling and control module is further configured to: Parsing the data transfer message to obtain a message type identifier of the data transfer message; querying the message definition and mapping configuration table based on the message type identifier to determine an entry in the message definition and mapping configuration table that matches the data transfer message; as well as The storage space is determined according to the entry.

5. The device according to claim 3, characterized in that The storage device is a first storage device, and the message definition and mapping configuration table is a static configuration table that is preset and stored in a second storage device.

6. The device according to claim 1, characterized in that: The apparatus communicates with the plurality of asynchronous processors via a Peripheral Component Interconnect Express (PCIe) bus through the plurality of port modules, and wherein each of the plurality of port modules has a corresponding block storage unit to buffer the data transfer messages.

7. The device according to claim 6, characterized in that The scheduling and control module is further configured to set the predefined timing based on a read transfer rate of the PCIe bus and a read and write rate of the storage device.

8. The device according to claim 1, characterized in that The scheduling and control module is further configured to check the plurality of port modules in a static time-sharing polling manner to obtain the data transfer message.

9. The device according to claim 1, characterized in that The scheduling and control module is further configured to dynamically check the multiple port modules to obtain the data transfer messages based on the priorities of the multiple asynchronous processors and / or based on the order in which the multiple asynchronous processors send the data transfer messages.

10. The device according to any one of claims 1 to 9, characterized in that The data transfer message indicates that the receiving processor is to receive data from the sending processor, wherein The scheduling and control module is further configured to: Checking the plurality of port modules according to a predefined timing to obtain the data transfer message; and parsing the data transfer message to determine storage space for received data; and The storage device management module is further configured to: reading data from the determined storage space; and Returning the read data to the scheduling and control module; The scheduling and control module further transmits the received data to the receiving processor via the corresponding port module.

11. The device according to claim 10, characterized in that The data transfer message includes a port number of a destination to receive data from the sender processor, Wherein, the scheduling and control module is further configured to: The port number is parsed from the data transfer message to determine whether one or more recipient processors have access rights to the determined memory space.

12. The device according to claim 10, characterized in that The device is implemented by a field programmable gate array FPGA.

13. A method for real-time data transmission between multiple asynchronous processors, characterized in that: include: receiving data transfer messages sent by the plurality of asynchronous processors in real time, wherein the data transfer messages indicate that a sending processor among the plurality of asynchronous processors is to send data to a receiving processor among the plurality of asynchronous processors; processing the data transfer message according to a predefined timing to determine storage space in a storage device for the data to be sent; and The transmitted data is written into the determined storage space.

14. The method according to claim 13, characterized in that The data transfer message has a predefined message format, and the predefined message format is reflected by a message definition and mapping configuration table.

15. The method according to claim 14, characterized in that The predefined message format includes a message type identifier field and a payload field, wherein a value of the message type identifier field is used to uniquely identify the type of the data transfer message, and a value of the payload field indicates the transmitted data.

16. The method according to claim 15, characterized in that The method further comprises: parsing the data transfer message according to the predefined timing to obtain a message type identifier of the data transfer message; querying the message definition and mapping configuration table based on the message type identifier to determine an entry in the message definition and mapping configuration table that matches the data transfer message; and The storage space is determined according to the entry.

17. The method according to claim 13, characterized in that The method further includes buffering the data transfer message in a block storage unit associated with a processor of the plurality of asynchronous processors that issued the data transfer message.

18. The method according to any one of claims 13 to 17, characterized in that The data transfer message indicates that the receiving processor is to receive data from the sending processor, wherein the method further comprises: processing the data transfer message according to a predefined timing to determine storage space for received data; reading data from the determined storage space; and The read data is transmitted to the receiving processor.

19. The method according to claim 18, characterized in that The data transfer message includes a port number of a target to receive data from the sender processor, wherein the method further comprises: The port number is parsed from the data transfer message to determine whether one or more recipient processors have access rights to the determined memory space.

20. A computing system, characterized in that: include: Multiple asynchronous processors; The device according to any one of claims 1 to 12, wherein the device is connected to the plurality of asynchronous processors; as well as The storage device.

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