Cross-clock domain queue structure

Abstract

The invention relates to a cross-clock domain queue structure, which is used for carrying out cross-clock domain data transmission, and comprises a cross-clock domain FIFO (First In First Out) which is positioned in a slow clock domain and is used for synchronizing a combined signal of a plurality of signals corresponding to a plurality of data processed in the slow clock domain to a fast clock domain, the slow clock domain is a slower clock period in a read clock period and a write clock period, and the fast clock domain is a faster clock period in the read clock period and the write clock period; the first generation module is located in the fast clock domain and used for generating a first mark signal representing the empty and full state of the cross-clock-domain queue according to a signal corresponding to a piece of data transmitted in the fast clock domain and the combined signal synchronized by the cross-clock-domain FIFO. Therefore, the bandwidth of cross-clock domain data transmission can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of digital circuit design, and in particular to a cross-clock domain queue structure. Background Art

[0002] In digital circuit design, there is a large demand for using a cross-clock domain (Clock Domain Crossing, CDC) queue to transfer data from one clock domain to another asynchronous clock domain. In the related art, a cross-clock domain queue based on Gray code counting is used to realize data transmission across clock domains. However, for the use of the cross-clock domain queue for cross-clock domain data transmission, only one piece of data can be pushed in one write clock cycle, and one piece of data can be popped out in one read clock cycle, so the bandwidth of data transmission is limited by the slow clock cycle in the write clock cycle and the read clock cycle and the bit width of the cross-clock domain queue.

[0003] Therefore, the cross-clock domain queue based on Gray code counting can be used for cross-clock domain data transmission with low bandwidth requirements, but the cross-clock domain queue based on Gray code counting cannot be used for cross-clock domain data transmission with high bandwidth requirements. Therefore, how to realize a cross-clock domain queue that can be applied to high-bandwidth cross-clock domain data transmission is one of the problems to be solved in the prior art. Summary of the invention

[0004] In view of this, the present disclosure proposes a cross-clock domain queue structure, so as to improve the bandwidth of data transmission across clock domains.

[0005] According to one aspect of the present disclosure, a cross-clock domain queue structure is provided for performing cross-clock domain data transmission, comprising: a cross-clock domain FIFO, which is located in a slow clock domain and is used to synchronize a combination signal of multiple signals corresponding to multiple data processed in the slow clock domain to a fast clock domain, wherein the slow clock domain is a slower clock cycle between a read clock cycle and a write clock cycle, and the fast clock domain is a faster clock cycle between the read clock cycle and the write clock cycle; a first generating module, which is located in the fast clock domain and is used to generate a first flag signal indicating the empty or full state of the cross-clock domain queue based on a signal corresponding to a data transmitted in the fast clock domain and a combination signal synchronized from the cross-clock domain FIFO.

[0006] In a possible implementation, it also includes: a first counting module, which is located in the fast clock domain, and is used to count the one signal to obtain a first count value; a synchronization module, which is located in the fast clock domain, and is used to synchronize the first count value to the slow clock domain; a second counting module, which is located in the slow clock domain, and is used to count the multiple signals to obtain a second count value; and a second generating module, which is used to generate a second flag signal indicating the empty or full state of the cross-clock domain queue according to the second count value and the synchronized first count value.

[0007] In a possible implementation, the width of the cross-clock domain FIFO is determined according to the frequency difference between the read clock cycle and the write clock cycle and the bandwidth requirement for cross-clock domain data transmission using the cross-clock domain queue structure.

[0008] In one possible implementation, when the bandwidth requirement is that the bandwidth of data transmission in the read clock cycle is equal to the bandwidth of data transmission in the write clock cycle, the width of the cross-clock domain FIFO is equal to the sum of a multiple of the frequency difference relative to the frequency of the slower clock cycle among the read clock cycle and the write clock cycle and 1.

[0009] In a possible implementation, the width of the cross-clock domain FIFO is equal to 2, 3 or 4.

[0010] In one possible implementation, when the slow clock domain is the read clock cycle and the fast clock domain is the write clock cycle, the cross-clock domain FIFO synchronizes the combination signal of multiple pop-up signals corresponding to multiple data popped out in one read clock cycle to the write clock cycle, and accordingly, the first counting module counts the data pushed in one write clock cycle to obtain a write pointer, and the write pointer is used as the first count value; the first generating module compares the write pointer with the synchronized combination signal to generate a flag signal indicating that the cross-clock domain queue is full.

[0011] In one possible implementation, when the slow clock domain is the read clock cycle and the fast clock domain is the write clock cycle, the synchronization module synchronizes the write pointer to the read clock cycle, the second counting module counts the multiple pop-up signals to obtain a read pointer, and the read pointer is used as the second count value; the second generating module compares the read pointer with the synchronized write pointer to generate a flag signal indicating that the cross-clock domain queue is empty and a flag signal indicating that the cross-clock domain queue is about to be empty.

[0012] In a possible implementation, when the width of the cross-clock domain queue is N, the multiple pop-up signals are N pop-up signals, and the second generating module is configured to: when M pop-up signals among the N pop-up signals are valid at the same time, increment the read pointer by M, wherein N is a positive integer greater than or equal to 2, and M is less than or equal to N.

[0013] In a possible implementation, when the slow clock domain is the write clock cycle and the fast clock domain is the read clock cycle, the cross-clock domain FIFO synchronizes the combination signal of multiple push signals corresponding to multiple data pushed in one write clock cycle to the read clock domain, and accordingly, the first counting module counts the data popped out in one read clock cycle to obtain a read pointer; the first generating module compares the read pointer with the synchronized combination signal to generate a flag signal indicating that the cross-clock domain queue is empty.

[0014] In one possible implementation, when the slow clock domain is the write clock cycle and the fast clock domain is the read clock cycle, the synchronization module synchronizes the read pointer to the read clock cycle, the second counting module counts the multiple advance signals to obtain a write pointer, and the write pointer is used as the second count value; the second generating module compares the write pointer with the synchronized read pointer to generate a flag signal indicating that the cross-clock domain queue is full and a flag signal indicating that the cross-clock domain queue is about to be full.

[0015] In one possible implementation, when the width of the cross-clock domain queue is P, the multiple push signals are P push signals, and the second generating module is configured to: when Q push signals among the P push signals are valid at the same time, increment the write pointer by Q, where P is a positive integer greater than or equal to 2, and Q is less than or equal to P.

[0016] According to the cross-clock domain queue structure disclosed in the present invention, a piece of data can be transmitted in the faster clock cycle of the read clock cycle and the write clock cycle, and multiple pieces of data can be processed in the slower clock cycle of the two. Therefore, using the cross-clock domain queue structure disclosed in the present invention to realize cross-clock domain data transmission can make the bandwidth of data transmission no longer limited by the slow clock cycle during cross-clock domain processing, thereby improving the processing performance of the system and achieving a higher data transmission bandwidth compared with the cross-clock domain queue based on Gray code counting.

[0017] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0019] Figure 1 A pointer-based cross-clock domain queue structure is provided according to an embodiment of the present disclosure.

[0020] Figure 2 is a block diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure.

[0021] Figure 3 is a block diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure.

[0022] Figure 4 is a block diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure.

[0023] Figure 5 is a timing diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure.

[0024] Figure 6 is a block diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure.

[0025] Figure 7 is a block diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure.

[0026] Figure 8 is a block diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0028] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0029] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0030] Figure 1 FIG. 4 shows a cross-clock domain queue structure based on Gray code counting. Figure 1As shown, when a data is written in the write clock domain WCLK, there is a push signal in the write clock domain WCLK, and the push signal is counted in Gray code to generate a Gray code write pointer gwptr, and then the counting result gwptr is synchronized to the read clock domain RCLK through the synchronization of a 2-stage D-type flip-flop (referred to as 2DFF). At the same time, when a data is read out in the read clock domain RCLK, there is a pop signal in the read clock domain RCLK, and the pop signal is counted in Gray code to generate a Gray code read pointer grptr, and then the counting result grptr is synchronized to the write clock domain WCLK through the synchronization of 2DFF. In the write clock domain WCLK, the write pointer gwptr is compared with the synchronized read pointer grptr to generate a full signal indicating that the cross-clock domain queue is full. Correspondingly, in the read clock domain RCLK, the read pointer grptr is compared with the synchronized write pointer gwptr to generate an empty signal indicating that the cross-clock domain queue is empty.

[0031] Therefore, the cross-clock domain queue based on Gray code counting can only meet the requirements of pushing one data in one write clock cycle (1TWCLK) and popping one data in one read clock cycle (1T RCLK). Therefore, the bandwidth of cross-clock domain data transmission using the cross-clock domain queue is limited by the slow clock cycles in the read clock cycle RCLK and the write clock cycle WCLK and the bit width of the cross-clock domain queue, and is therefore not suitable for cross-clock domain data transmission with high bandwidth requirements.

[0032] To this end, this embodiment proposes a cross-clock domain queue structure that can be applied to high-bandwidth cross-clock domain data transmission, so that the bandwidth of data transmission is no longer limited by the slow clock cycle during cross-clock domain processing, thereby improving the processing performance of the system and achieving a higher data transmission bandwidth compared to the cross-clock domain queue based on Gray code counting. Figure 2 to Figure 8 The cross-clock domain queue structure of the present disclosure is described in detail.

[0033] Figure 2 A block diagram of a cross-clock domain queue structure according to an embodiment of the present disclosure is shown. The cross-clock domain queue structure 200 can be used for data transmission across clock domains, such as transmitting data from a fast clock domain to a slow clock domain and transmitting data from a slow clock domain to a fast clock domain. Figure 2As shown, the cross-clock domain queue structure may include a CDC FIFO 210 and a first generating module 220. The CDC FIFO 210 is located in a slow clock domain, and is used to synchronize the combined signals of multiple signals corresponding to multiple data processed in a slow clock domain to a fast clock domain, wherein the slow clock domain is a slower clock cycle in a read clock cycle and a write clock cycle, and the fast clock domain is a faster clock cycle in a read clock cycle and a write clock cycle. The first generating module 220 is located in the fast clock domain, and is used to generate a first flag signal indicating the empty or full state of the cross-clock domain queue according to a signal corresponding to a data transmitted in the fast clock domain and a combined signal synchronized from the CDCFIFO 210.

[0034] In this embodiment, a CDC FIFO 210 is introduced into the cross-clock domain queue structure 200. During the period of transmitting a piece of data in the fast clock domain, the CDC FIFO 210 can be used to synchronize multiple signals corresponding to multiple pieces of data in the slow clock domain to the fast clock domain. In this way, the first generating module 220 is used in the fast clock domain to compare the piece of data with the synchronized multiple signals to generate a flag signal, i.e., a first flag signal, for indicating the full or empty state of the cross-clock domain queue.

[0035] Thus, compared to Figure 1 During the period of transmitting a piece of data in the fast clock domain, a 2-level DFF is used to synchronize a signal corresponding to a piece of data in the slow clock domain to the fast clock domain. This embodiment can transmit a piece of data in the faster clock cycle of the read clock cycle and the write clock cycle, and process multiple pieces of data in the slower clock cycle of the two. Therefore, using the cross-clock domain queue structure of this embodiment to realize cross-clock domain data transmission can make the bandwidth of data transmission no longer limited by the slow clock cycle during cross-clock domain processing, thereby improving the processing performance of the system. Figure 1 Compared with the cross-clock domain queue structure, it can achieve higher data transmission bandwidth.

[0036] Figure 3 A block diagram showing a cross-clock domain queue structure according to an embodiment of the present disclosure is shown. Figure 3 The cross-clock domain queue structure 300 shown is compared to Figure 2 The cross-clock domain queue structure 200 shown in the figure is additionally provided with a first counting module 230, a synchronization module 240, a second counting module 250 and a second generating module 260. Figure 3 Regarding the CDC FIFO 210 and the first generating module 220, please refer to the above description. Figure 2 The description will not be repeated here.

[0037] The first counting module 230 is located in the fast clock domain, and is used to perform Gray code counting on a signal corresponding to a data transmitted in the fast clock domain to generate a Gray code pointer, and the generated Gray code pointer is used as the first count value. Then, the first count value is synchronized to the slow clock domain through the synchronization module 240 located in the fast clock domain, such as 2-level or 3-level DFF synchronization. At the same time, in the slow clock domain, the second counting module 250 counts the multiple signals corresponding to the above-mentioned multiple data to obtain a second count value. In this way, the second generating module 260 can be used to generate a second flag signal indicating the empty or full state of the cross-clock domain queue according to the second count value and the synchronized first count value. That is, the second generating module 260 compares the second count value with the synchronized first count value to generate a flag signal, i.e., a second flag signal, for indicating the full or empty state of the cross-clock domain queue.

[0038] In a possible implementation, the width of the CDC FIFO 210 is determined according to the frequency difference between the read clock cycle and the write clock cycle and the bandwidth requirement for cross-clock domain data transmission using the cross-clock domain queue structure.

[0039] In this embodiment, the width of CDC FIFO 210 can be determined according to the frequency difference between the read clock cycle and the write clock cycle to meet the bandwidth requirement of data transmission. Thus, the number of data processed in the slower clock cycle of the read clock cycle and the write clock cycle can be dynamically adjusted to achieve cross-clock domain data transmission with various high bandwidth requirements.

[0040] In one possible implementation, when the bandwidth requirement is that the bandwidth of data transmission in a read clock cycle is equal to the bandwidth of data transmission in a write clock cycle, the width of the CDC FIFO 210 is equal to the sum of a multiple of the frequency difference between the two relative to the frequency of the slower clock cycle of the read clock cycle and the write clock cycle and 1.

[0041] In this embodiment, the width of the CDC FIFO 210 can be determined according to the frequency difference between the read clock cycle and the write clock cycle, so that the bandwidth of data transmission of the read clock cycle and the write clock cycle is equal. For example, the frequency difference between the read clock cycle and the write clock cycle can be calculated, and then the frequency difference is calculated as a multiple of the frequency of the slower clock cycle of the two, and the multiple + 1 is the width of the CDC FIFO 210. For another example, the ratio of the frequency of the faster clock cycle of the read clock cycle and the write clock cycle to the frequency of the slower clock cycle can be calculated, and then the ratio is used as the width of the CDC FIFO 210.

[0042] Exemplarily, assuming that the bandwidth of data transmission of the read clock cycle and the write clock cycle is equal, if the frequency of the write clock cycle is 200M and the frequency of the read clock cycle is 100M, the width of the CDC FIFO 210 is 200M / 100M=2; if the frequency of the write clock cycle is 150M and the frequency of the read clock cycle is 50M, the width of the CDC FIFO 210 is 150M / 50M=3; if the frequency of the write clock cycle is 200M and the frequency of the read clock cycle is 50M, the width of the CDC FIFO 210 is 200M / 50M=4.

[0043] In the case where the slow clock domain is the read clock cycle and the fast clock domain is the write clock cycle, such as Figure 4 As shown, the cross-clock domain queue structure 400 may include a POP_CDC FIFO 410 , a write counter (Wcounter) 420 , a gwptr 430 , a 2DFFsync 440 , a read counter (Rcounter) 450 , and a module 460 .

[0044] POP_CDC FIFO 410 synchronizes the combination signals of multiple pop-up signals pop 1 and pop 2 corresponding to multiple data popped out in a read clock cycle RCLK to the write clock cycle WCLK, and gwptr 430 counts the push signal of a data pushed in a write clock cycle WCLK to obtain the write pointer gwptr as the first count value. Wcounter 420 compares the push signal with the synchronized combination signal to generate a flag signal full signal indicating that the cross-clock domain queue is full.

[0045] 2DFF sync 440 synchronizes the write pointer gwptr to the read clock cycle RCLK, Rcounter 450 counts multiple pop-up signals pop 1 and pop 2 to obtain a read pointer as a second count value, and module 460 compares the read pointer with the synchronized write pointer gwptr to generate a flag signal empty signal indicating that the cross-clock domain queue is empty and a flag signal nrempty signal indicating that the cross-clock domain queue is about to be empty.

[0046] In this embodiment, when a piece of data is written in the write clock domain WCLK, there is a push signal in the write clock domain WCLK, gwptr 430 performs Gray code counting on the push signal to generate a Gray code write pointer gwptr, and then synchronizes the count result gwptr to the RCLK clock domain through synchronization of 2DFF sync 440. At the same time, when two pieces of data are read out in the read clock domain RCLK, there are pop 1 signal and pop 2 signal in the read clock domain RCLK. In the read clock domain RCLK, Rcounter450 calculates the read pointer grptr based on the pop 1 signal and the pop 2 signal, and compares the read pointer grptr with the synchronized write pointer gwptr to generate an empty signal indicating that the cross-clock domain queue is empty and an nrempty signal indicating that the cross-clock domain queue is about to be empty.

[0047] At the same time, in order to avoid the problem of bit error rate caused by the simultaneous change of multi-bit encoding due to the Gray code counting of the two pop signals, the pop 1 signal and the pop 2 signal of one read clock cycle, this embodiment does not perform Gray code counting on the two signals, but writes the pop 1 signal and the pop 2 signal as data into the POP_CDCFIFO 410, and the POP_CDC FIFO 410 synchronizes the states of the pop 1 signal and the pop 2 signal to the write clock domain WCLK as a record. In the write clock domain WCLK, the Wcounter 420 compares the push signal with the states of the synchronized pop 1 signal and the pop 2 signal to generate a full signal indicating that the cross-clock domain queue is full.

[0048] In a possible implementation, when both the pop 1 signal and the pop 2 signal are valid, the read pointer grptr is incremented by 2, and when only one of the pop 1 signal and the pop 2 signal is valid, the read pointer grptr is incremented by 1. When both the pop 1 signal and the pop 2 signal are invalid, the read pointer grptr is not incremented. It should be understood that for Figure 4 For the cross-clock domain queue structure shown, the nrempty signal indicates that there is and only one valid data in the cross-clock domain queue. The pop 1 signal is allowed to be valid when the cross-clock domain queue is not empty, and the pop 2 signal is allowed to be valid when the cross-clock domain queue is not empty and is not about to be empty.

[0049] By comparison Figure 4 and Figure 1 It can be seen that the cross-clock domain queue structure of this embodiment uses a cross-clock domain FIFO, i.e. Figure 4The POP_CDC FIFO 410 in the read clock domain RCLK is used to synchronize the pop 1 signal and pop 2 signal of the read clock domain RCLK to the write clock domain WCLK. POP_CDC is a traditional asynchronous First-In-First-Out (FIFO). The width and depth of POP_CDC can be configured according to the frequency difference between WCLK and RCLK and the bandwidth requirement. The width setting method is described above and will not be repeated here.

[0050] for Figure 4 In the cross-clock domain queue structure shown, the width of the POP_CDC FIFO 410 is equal to 2, and the depth of the POP_CDCFIFO 410 is equal to the depth of the cross-clock domain queue. The write clock of POP_CDC FIFO 410 is the read clock cycle RCLK of the cross-clock domain queue, the read clock of POP_CDC FIFO 410 is the write clock cycle WCLK of the cross-clock domain queue, the input data of POP_CDCFIFO 410 is a 2-bit signal {pop1, pop 2} composed of the pop 1 signal and the pop 2 signal of the cross-clock domain queue; the push signal of POP_CDC FIFO 410 is the OR logic "pop 1||pop2" of the pop 1 signal and the pop 2 signal; the pop signal of POP_CDC FIFO 410 is a non-empty signal of the cross-clock domain queue, and outputs 2 bits of data at the same time, such as "00", "01", "10" and "11", "00" indicates that both the pop 1 signal and the pop 2 signal are invalid, "01" indicates that the pop 1 signal is invalid but the pop 2 signal is valid, "10" indicates that the pop 1 signal is valid but the pop 2 signal is invalid, and "11" indicates that both the pop 1 signal and the pop2 signal are valid. Therefore, if Figure 5 As shown in the timing diagram, the pop1_w signal and pop2_w signal of the write clock domain WCLK can be obtained. Thus, the problem of bit error rate caused by simultaneous changes of multiple bit codes caused by Gray code counting of two pop signals of a read clock domain can be avoided.

[0051] According to this embodiment, when the frequency of the write clock cycle WCLK is greater than the frequency of the read clock cycle RCLK, the Figure 4 The cross-clock domain queue structure shown in the figure is used to transmit data across clock domains, which can push one data in one WCLK and pop up two data in one RCLK, so that the bandwidth of data transmission is no longer limited by RCLK. Figure 1 The cross-clock domain queue structure shown can achieve higher data transmission bandwidth with fewer resources.

[0052] In the case where the slow clock domain is the write clock cycle and the fast clock domain is the read clock cycle, such as Figure 6 As shown, the cross-clock domain queue structure 600 may include a PUSH_CDC FIFO 630 , a write counter (Wcounter) 620 , a grptr 650 , a 2DFFsync 610 , a read counter (Rcounter) 660 , and a module 640 .

[0053] PUSH_CDC FIFO 630 synchronizes the combination of multiple push signals push 1 and push 2 corresponding to multiple data pushed in a write clock cycle WCLK to the read clock cycle RCLK, and grptr 650 counts the pop signal of a data popped in a read clock cycle RCLK to obtain the read pointer grptr as the first count value. Rcounter 660 compares the pop signal with the synchronized combination signal to generate a flag signal empty signal indicating that the cross-clock domain queue is empty.

[0054] 2DFF sync 650 synchronizes the read pointer grptr to the write clock cycle WCLK, Wcounter 620 counts multiple push signals push 1 and push 2 to obtain a write pointer as a second count value, and module 640 compares the write pointer with the synchronized read pointer grptr to generate a flag signal full signal indicating that the cross-clock domain queue is full and a flag signal nrfull signal indicating that the cross-clock domain queue is about to be full.

[0055] In this embodiment, when a piece of data is read out in the read clock domain RCLK, there is a pop signal in the read clock domain RCLK, grptr 650 performs Gray code counting on the pop signal to generate a Gray code read pointer grptr, and then synchronizes the counting result grptr to the write clock domain WCLK through synchronization of 2DFF sync 610. At the same time, when two pieces of data are written in the write clock domain WCLK, there are push 1 signal and push 2 signal in the write clock domain WCLK. In the write clock domain WCLK, Wcounter 620 calculates the write pointer gwptr based on the push 1 signal and the push 2 signal, and compares the write pointer gwptr with the synchronized read pointer grptr to generate a full signal indicating that the cross-clock domain queue is full and a nrfull signal indicating that the cross-clock domain queue is about to be full.

[0056] At the same time, in order to avoid the problem of bit error rate caused by the simultaneous change of multi-bit encoding due to the Gray code counting of the two push signals, push 1 signal and push 2 signal of one write clock cycle WCLK, the present embodiment does not count the two signals in Gray code, but writes the push 1 signal and push 2 signal as data into PUSH_CDC FIFO 630, and PUSH_CDC FIFO 630 synchronizes the states of the push 1 signal and push 2 signal to the read clock domain RCLK as records. In the read clock domain RCLK, Rcounter 660 compares the pop signal with the states of the synchronized push 1 signal and push 2 signal to generate an empty signal indicating that the cross-clock domain queue is empty.

[0057] In a possible implementation, when both the push 1 signal and the push 2 signal are valid, the write pointer gwptr is incremented by 2, and when only one of the push 1 signal and the push 2 signal is valid, the write pointer gwptr is incremented by 1. When both the push 1 signal and the push 2 signal are invalid, the write pointer gwptr is not incremented. Figure 6 For the cross-clock domain queue structure shown, the nrfull signal indicates that there is and only one valid data in the cross-clock domain queue. The push1 signal is allowed to be valid when the cross-clock domain queue is not empty, and the push 2 signal is allowed to be valid when the cross-clock domain queue is not empty and is not about to be empty.

[0058] By comparison Figure 6 and Figure 1 It can be seen that the cross-clock domain queue structure of this embodiment uses a cross-clock domain FIFO, i.e. Figure 6 The PUSH_CDC FIFO 630 in the write clock domain WCLK is used to synchronize the push 1 signal and the push 2 signal of the read clock domain RCLK.

[0059] for Figure 6In the cross-clock domain queue structure shown, the width of the PUSH_CDC FIFO 630 is equal to 2, and the depth of the PUSH_CDCFIFO 630 is equal to the depth of the cross-clock domain queue. The write clock of PUSH_CDC FIFO 630 is the write clock cycle WCLK of the cross-clock domain queue, the read clock of PUSH_CDC FIFO 630 is the read clock cycle RCLK of the cross-clock domain queue, and the input data of PUSH_CDC FIFO 630 is a 2-bit signal {push 1, push 2} composed of the push 1 signal and the push 2 signal of the cross-clock domain queue; the pop signal of PUSH_CDC FIFO 630 is the OR logic "push 1||push 2" of the push 1 signal and the push 2 signal; the push signal of PUSH_CDC FIFO 630 is a non-full signal of the cross-clock domain queue, and outputs 2 bits of data at the same time, such as "00", "01", "10" and "11", "00" indicates that both the push 1 signal and the push 2 signal are invalid, "01" indicates that the push 1 signal is invalid but the push 2 signal is valid, and "10" indicates that the push 1 signal is valid but the push The push 2 signal is invalid, and "11" indicates that both the push 1 signal and the push 2 signal are valid. Therefore, the push1_r signal and the push2_r signal of the read clock domain RCLK can be obtained. In this way, the problem of bit error rate caused by simultaneous changes in multiple bit codes due to Gray code counting of two push signals in a write clock domain can be avoided.

[0060] According to this embodiment, when the frequency of the read clock cycle RCLK is greater than the frequency of the write clock cycle WCLK, the Figure 6 The cross-clock domain queue structure shown in FIG. 1 is used to transmit data across clock domains, which can realize popping out one piece of data in one RCLK and pushing two pieces of data in one WCLK, so that the bandwidth of data transmission is no longer limited by RCLK. Figure 1 The cross-clock domain queue structure shown can achieve higher data transmission bandwidth with fewer resources.

[0061] Figure 7 A block diagram showing a cross-clock domain queue structure according to an embodiment of the present disclosure is shown. Figure 7 The cross-clock domain queue structure 700 shown is compared to Figure 4 The difference between the cross-clock domain queue structure 400 shown is that the number of pop signals increases from 2 to 3, that is, the width of the POP_CDC FIFO changes from 2 to 3. For a detailed description of the cross-clock domain queue structure 700, please refer to the above description of Figure 4 The description will not be repeated here.

[0062] for Figure 7 In the cross-clock domain queue structure shown, the width of the POP_CDC FIFO 710 is equal to 3, and the depth of the POP_CDCFIFO 710 is equal to the depth of the cross-clock domain queue. The write clock of POP_CDC FIFO 710 is the read clock cycle RCLK of the cross-clock domain queue, the read clock of POP_CDC FIFO 710 is the write clock cycle WCLK of the cross-clock domain queue, and the input data of POP_CDCFIFO 710 is a 3-bit signal {pop 1, pop 2, pop 3} composed of the pop 1 signal, pop 2 signal and pop 3 signal of the cross-clock domain queue; the push signal of POP_CDC FIFO 710 is the OR logic "pop 1||pop 2||pop 3" of the pop 1 signal, pop 2 signal and pop3 signal; the pop signal of POP_CDC FIFO 710 is a non-empty signal of the cross-clock domain queue, and outputs 3 bits of data at the same time, such as "000", "001", "010", "011", "100", "101", "110", "111", "000" represents the pop 1 signal, pop 2 signal and pop "001" means that pop 1 and pop 2 signals are invalid but pop 3 signal is valid, "100" means that pop 1 signal is valid but pop 2 and pop 3 signals are invalid, and "111" means that pop 1, pop 2 and pop 3 signals are all valid.

[0063] According to this embodiment, when the frequency of the write clock cycle WCLK is greater than the frequency of the read clock cycle RCLK, the Figure 7 The cross-clock domain queue structure shown in FIG. 1 is used to transmit data across clock domains, which can push one data in one WCLK and pop up three data in one RCLK, so that the bandwidth of data transmission is no longer limited by RCLK. Figure 1 The cross-clock domain queue structure shown can achieve higher data transmission bandwidth with fewer resources.

[0064] Figure 8 A block diagram showing a cross-clock domain queue structure according to an embodiment of the present disclosure is shown. Figure 8 The cross-clock domain queue structure 800 shown is compared to Figure 4 The difference between the cross-clock domain queue structure 400 shown is that the number of pop signals increases from 2 to 4, that is, the width of the POP_CDC FIFO changes from 2 to 4. For a detailed description of the cross-clock domain queue structure 800, please refer to the above description of Figure 4 The description will not be repeated here.

[0065] for Figure 8 In the cross-clock domain queue structure shown, the width of POP_CDC FIFO 810 is equal to 4, and the depth of POP_CDCFIFO 810 is equal to the depth of the cross-clock domain queue. The write clock of POP_CDC FIFO 810 is the read clock cycle RCLK of the cross-clock domain queue, the read clock of POP_CDC FIFO 810 is the write clock cycle WCLK of the cross-clock domain queue, and the input data of POP_CDCFIFO 810 is a 4-bit signal {pop 1, pop 2, pop 3, pop 4} composed of the pop 1 signal, pop 2 signal, pop 3 signal and pop 4 signal of the cross-clock domain queue; the push signal of POP_CDC FIFO 810 is the OR logic "pop 1||pop 2||pop 3||pop 4" of the pop 1 signal to pop 4 signal; the pop signal of POP_CDC FIFO 810 is a non-empty signal of the cross-clock domain queue, and outputs 4 bits of data at the same time.

[0066] According to this embodiment, when the frequency of the write clock cycle WCLK is greater than the frequency of the read clock cycle RCLK, the Figure 8 The cross-clock domain queue structure shown in FIG. 1 is used to transmit data across clock domains, which can push one data in one WCLK and pop up four data in one RCLK, so that the bandwidth of data transmission is no longer limited by RCLK. Figure 1 The cross-clock domain queue structure shown can achieve higher data transmission bandwidth with fewer resources.

[0067] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A cross-clock domain queue structure for data transmission across clock domains, characterized in that: include: A cross-clock domain FIFO, which is located in a slow clock domain and is used to synchronize a combination signal of multiple signals corresponding to multiple data processed in one of the slow clock domains to a fast clock domain, wherein the slow clock domain is a slower clock cycle of a read clock cycle and a write clock cycle, and the fast clock domain is a faster clock cycle of the read clock cycle and the write clock cycle; The first generating module is located in the fast clock domain and is used to generate a first flag signal indicating the empty or full state of the cross-clock domain queue according to a signal corresponding to a data transmitted in the fast clock domain and a combined signal synchronized from the cross-clock domain FIFO.

2. The cross-clock domain queue structure according to claim 1, characterized in that: Also includes: A first counting module, located in the fast clock domain, for counting the one signal to obtain a first counting value; A synchronization module, located in the fast clock domain, configured to synchronize the first count value to the slow clock domain; A second counting module, located in the slow clock domain, for counting the multiple signals to obtain a second counting value; The second generating module is used to generate a second flag signal indicating the empty or full state of the cross-clock domain queue according to the second count value and the synchronized first count value.

3. The cross-clock domain queue structure according to claim 1, characterized in that: The width of the cross-clock domain FIFO is determined according to the frequency difference between the read clock cycle and the write clock cycle and the bandwidth requirement for cross-clock domain data transmission using the cross-clock domain queue structure.

4. The cross-clock domain queue structure according to claim 3, characterized in that: When the bandwidth requirement is that the bandwidth of data transmission in the read clock cycle is equal to the bandwidth of data transmission in the write clock cycle, the width of the cross-clock domain FIFO is equal to the sum of a multiple of the frequency difference relative to the frequency of the slower clock cycle among the read clock cycle and the write clock cycle and 1.

5. The cross-clock domain queue structure according to claim 3, characterized in that: The width of the cross-clock domain FIFO is equal to 2, 3 or 4.

6. The cross-clock domain queue structure according to claim 2, characterized in that: In the case where the slow clock domain is the read clock cycle and the fast clock domain is the write clock cycle, The cross-clock domain FIFO synchronizes the combined signal of multiple ejection signals corresponding to multiple data ejected in one read clock cycle to the write clock cycle. Accordingly, The first counting module counts a data entry advanced in one write clock cycle to obtain a write pointer, and the write pointer is used as the first count value; The first generating module compares the write pointer with the synchronized combined signal to generate a flag signal indicating that the cross-clock domain queue is full.

7. The cross-clock domain queue structure according to claim 6, characterized in that: In the case where the slow clock domain is the read clock cycle and the fast clock domain is the write clock cycle, The synchronization module synchronizes the write pointer to the read clock cycle, The second counting module counts the plurality of eject signals to obtain a read pointer, and the read pointer is used as the second counting value; The second generating module compares the read pointer with the synchronized write pointer to generate a flag signal indicating that the cross-clock domain queue is empty and a flag signal indicating that the cross-clock domain queue is about to be empty.

8. The cross-clock domain queue structure according to claim 2, characterized in that: In the case where the slow clock domain is the write clock cycle and the fast clock domain is the read clock cycle, The cross-clock domain FIFO synchronizes the combined signal of multiple push signals corresponding to multiple data pushed in one write clock cycle to the read clock domain. Accordingly, The first counting module counts a piece of data popped out in one of the read clock cycles to obtain a read pointer; The first generating module compares the read pointer with the synchronized combined signal to generate a flag signal indicating that the cross-clock domain queue is empty.

9. The cross-clock domain queue structure according to claim 8, characterized in that: In the case where the slow clock domain is the write clock cycle and the fast clock domain is the read clock cycle, The synchronization module synchronizes the read pointer to the read clock cycle, The second counting module counts the plurality of advance signals to obtain a write pointer, and the write pointer is used as the second count value; The second generating module compares the write pointer with the synchronized read pointer to generate a flag signal indicating that the cross-clock domain queue is full and a flag signal indicating that the cross-clock domain queue is about to be full.

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