A wiring optimization method and device for FPGA circuit layout

Abstract

The present invention relates to the technical field of circuit layout optimization, and discloses a wiring optimization method and device for FPGA circuit layout, the method comprising: obtaining initial layout data of the FPGA circuit, generating a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit; using a convolutional neural network model to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain a wiring feasibility prediction value of the FPGA circuit layout; optimizing and adjusting the FPGA circuit layout based on the wiring feasibility prediction value of the FPGA circuit layout to obtain a wiring optimization result of the FPGA circuit layout. The present invention can not only significantly reduce invalid layout and wiring iterations, but also dynamically optimize and adjust the FPGA circuit layout through a feedback mechanism, thereby improving the wiring efficiency and wiring success rate of the FPGA circuit layout.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit layout optimization, and in particular to a wiring optimization method and device for FPGA circuit layout. Background Art

[0002] In the FPGA (Field Programmable Gate Array) design process, the routability of the circuit layout is one of the key factors that determine the success of the design. Routine failure will not only lead to more design iterations, but also extend the time to market.

[0003] However, the routability prediction accuracy of FPGA circuit layout is insufficient, resulting in low routing efficiency and success rate of FPGA circuit layout. Summary of the invention

[0004] In view of this, the present invention provides a wiring optimization method and device for FPGA circuit layout to solve the problems of low wiring efficiency and success rate of FPGA circuit layout.

[0005] In a first aspect, the present invention provides a wiring optimization method for FPGA circuit layout, the method comprising: Acquire initial layout data of the FPGA circuit, and generate a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit; The convolutional neural network model is used to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain the routing feasibility prediction value of the FPGA circuit layout; The FPGA circuit layout is optimized and adjusted based on the routing feasibility prediction value of the FPGA circuit layout to obtain the routing optimization result of the FPGA circuit layout.

[0006] The present embodiment provides a routing optimization method for FPGA circuit layout, which generates a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit; uses a convolutional neural network model to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout; optimizes and adjusts the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain a routing optimization result of the FPGA circuit layout; uses convolutional neural network technology to quickly and accurately predict whether the FPGA circuit layout is routable by analyzing the congestion heat map during the FPGA circuit layout process, which can not only significantly reduce invalid layout and routing iterations, but also dynamically optimize and adjust the FPGA circuit layout through a feedback mechanism, thereby improving the routing efficiency and routing success rate of the FPGA circuit layout and reducing design time and resource consumption.

[0007] In an optional implementation, generating a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit includes: Calculate the path requirements of each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit; Divide the FPGA circuit layout into multiple grid areas, and determine the cumulative path requirements of the signal lines in each grid area based on the path requirements of each signal line; Obtain available wiring resources in each grid area, and calculate the congestion level value of each grid area based on the accumulated path requirements of the signal lines in each grid area and the available wiring resources in each grid area; A congestion heat map of FPGA circuit layout is constructed based on the congestion level of each grid area.

[0008] The present embodiment provides a wiring optimization method for FPGA circuit layout, which divides the FPGA circuit layout into multiple grid areas, calculates the congestion level of each grid area using the accumulated path requirements of signal lines in each grid area and the available wiring resources in each grid area, and then constructs a congestion heat map of the FPGA circuit layout, thereby achieving accurate calculation of resource requirements and resource supply in the FPGA circuit layout, and accurately displays the congestion level in each grid area through the congestion heat map, laying a foundation for accurate prediction of the wiring feasibility of the subsequent FPGA circuit layout and feedback optimization of the FPGA circuit layout.

[0009] In an optional implementation, calculating the path requirements of each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit includes: Determine the starting point, the ending point and the intermediate passing area of ​​each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit; Based on the starting point and the end point, a path allocation algorithm is used to determine the possible routing paths of each signal line; Based on the possible routing paths of each signal line, the number of times each signal line passes through the intermediate passing area is counted to generate the path requirements of each signal line.

[0010] The present embodiment provides a wiring optimization method for FPGA circuit layout, which achieves accurate calculation of path requirements for signal lines in the FPGA circuit layout by decomposing each signal line in the FPGA circuit layout and then performing path allocation, thereby laying a foundation for accurate calculation of resource requirements in subsequent FPGA circuit layout.

[0011] In an optional implementation, the convolutional neural network model includes an input layer, multiple convolutional layers, multiple pooling layers, and a fully connected layer; the convolutional neural network model is used to perform feature analysis on a congestion heat map of an FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout, including: The congestion heat map of the FPGA circuit layout is transmitted to the convolution layer through the input layer; Using multiple convolutional layers to perform convolution operations on the congestion heat map of the FPGA circuit layout, a spatial feature map of the FPGA circuit layout is obtained; Using multiple pooling layers to reduce the size of the spatial feature map of the FPGA circuit layout; Based on the spatial feature map of the reduced-size FPGA circuit layout, the fully connected layer is used for classification to obtain the routing feasibility prediction value of the FPGA circuit layout.

[0012] This embodiment provides a wiring optimization method for FPGA circuit layout. The convolutional neural network model uses multiple convolutional layers and pooling layers to perform convolution and pooling operations on the congestion heat map layer by layer, and then outputs the wiring feasibility prediction value of the FPGA circuit layout through a fully connected layer. A multi-stage convolutional neural network structure is used in combination with the congestion heat map to achieve high-precision routability prediction of the FPGA circuit layout.

[0013] In an optional implementation, before using a convolutional neural network model to perform feature analysis on a congestion heat map of an FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout, the method further includes: A layout congestion heat map and a routing feasibility prediction result are obtained, and a convolutional neural network model is trained using the layout congestion heat map and the routing feasibility prediction result to obtain a trained convolutional neural network model.

[0014] In an optional implementation, optimizing and adjusting the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain a routing optimization result of the FPGA circuit layout includes: Comparing the routing feasibility prediction value of the FPGA circuit layout with a preset threshold; If the routing feasibility prediction value of the FPGA circuit layout is less than a preset threshold, identifying a congested area to be optimized in a congestion heat map of the FPGA circuit layout; Optimize the parameters of the congested area to be optimized, and update the FPGA circuit layout based on the optimized parameters to obtain an updated FPGA circuit layout; the parameters include circuit density, signal line routing path, and routing resources; The updated FPGA circuit layout is verified and optimized, and a wiring optimization result of the FPGA circuit layout is determined based on the verification and optimization result.

[0015] The present embodiment provides a routing optimization method for FPGA circuit layout. The method determines the congested area to be optimized in the congestion heat map of the FPGA circuit layout by comparing the routing feasibility prediction value of the FPGA circuit layout with a preset threshold value, and then optimizes the parameters of the congested area to be optimized, thereby realizing dynamic adjustment of the FPGA circuit layout. The routing optimization result of the FPGA circuit layout is then determined according to the updated verification optimization result of the FPGA circuit layout. Ineffective layout iterations are avoided through real-time routability prediction and feedback adjustment. The routing scheme of the optimized FPGA circuit layout has a higher routing success rate, and the overall layout efficiency is improved. The prediction accuracy and minimum running time of the routability of the FPGA circuit layout are improved, and the routing design efficiency of the FPGA circuit layout is improved.

[0016] In a second aspect, the present invention provides a wiring optimization device for FPGA circuit layout, the device comprising: A generation module, used for acquiring initial layout data of the FPGA circuit, and generating a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit; A prediction module, used to perform feature analysis on a congestion heat map of the FPGA circuit layout using a convolutional neural network model to obtain a routing feasibility prediction value of the FPGA circuit layout; The layout optimization module is used to optimize and adjust the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain the routing optimization result of the FPGA circuit layout.

[0017] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the wiring optimization method for FPGA circuit layout of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0018] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the wiring optimization method for FPGA circuit layout of the above-mentioned first aspect or any corresponding embodiment thereof.

[0019] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the wiring optimization method for FPGA circuit layout of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a flow chart of a wiring optimization method for FPGA circuit layout according to an embodiment of the present invention; Figure 2 is a schematic diagram of a routability prediction process according to an embodiment of the present invention; Figure 3 is a flow chart of another FPGA circuit layout routing optimization method according to an embodiment of the present invention; Figure 4 is a flow chart of another FPGA circuit layout wiring optimization method according to an embodiment of the present invention; Figure 5 is a schematic diagram of the architecture of a convolutional neural network model according to an embodiment of the present invention; Figure 6 is a flow chart of another FPGA circuit layout wiring optimization method according to an embodiment of the present invention; Figure 7 is a structural block diagram of a wiring optimization device for FPGA circuit layout according to an embodiment of the present invention; Figure 8 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0023] In order to accurately predict the routability of FPGA circuit layout early in the design phase, the following method is proposed: (1) Global router method: The global router method uses a global routing tool to estimate the routing rate of the circuit. By simulating the entire routing process, this method can predict possible congestion and routing difficulty. Although this method is relatively reliable in terms of estimation accuracy and can provide relatively accurate prediction results, it takes a long time to run. Especially when dealing with complex FPGA designs, a routing simulation may take hours or even longer, which seriously limits the frequency of use of the global router in the actual layout optimization process, thereby affecting the overall design efficiency. In addition, the global router cannot fully consider the resource conflict problems that may arise during detailed routing, resulting in its insufficient adaptability in complex designs.

[0024] (2) Random model: The random model estimates the circuit connection length through probability distribution and predicts the routing rate based on statistical data. This type of method is simple and easy to implement, but its main disadvantage is that it ignores the geometric details of the circuit connection and the complexity of the internal structure of the FPGA, resulting in low accuracy of the prediction results. Compared with the global router method, although the random model has high computational efficiency, it is much worse in accuracy, so it is limited in practical applications.

[0025] (3) Congestion-based heuristic method: Estimating the routing rate by analyzing the local congestion in the circuit layout can provide more accurate predictions than random models. However, the congestion heuristic method mainly focuses on the local area and fails to fully consider the complex routing resource allocation characteristics in modern FPGA (especially heterogeneous FPGA) architectures. This method relies too much on heuristic rules, resulting in poor adaptability and accuracy of the prediction results when dealing with new FPGA architectures or complex circuit designs.

[0026] (4) Machine learning framework based on linear regression: Machine learning models based on linear regression have been introduced into the prediction of the routing rate. These models can outperform traditional methods in terms of running time and prediction accuracy by learning from historical data. However, due to the limitations of linear regression models in capturing the complex architecture and nonlinear characteristics of FPGAs, their prediction results still have certain errors, especially when dealing with new architectures or complex designs, showing the problem of poor adaptability.

[0027] Although the above methods have improved the routability prediction of FPGA circuit layout to varying degrees, they still face the following major difficulties: (1) Running time is too long: The global router approach suffers from long computation times: a single routing iteration can take hours for complex use cases, which is not sufficient for the real-time feedback required in modern FPGA designs.

[0028] (2) Insufficient prediction accuracy: Both random models and heuristic-based congestion analysis have insufficient accuracy. The above methods fail to fully consider the detailed features of FPGA layout, resulting in poor accuracy of routing rate prediction.

[0029] (3) Poor adaptability: The above methods have limited adaptability to new FPGA architectures or complex circuit designs. Many methods rely too much on specific rules or models, and when faced with new design challenges, they show problems of inaccurate predictions and difficulty in generalization.

[0030] To solve the above technical problems, an embodiment of the present invention provides a wiring optimization method for FPGA circuit layout, which uses a deep learning framework of a convolutional neural network model (CNN) to predict the routability of the circuit in real time during the FPGA layout process. By extracting and analyzing the features of the layout congestion heat map, the routability of the layout can be quickly and accurately predicted, and the strategy of the layout tool can be optimized through a feedback mechanism, thereby reducing unnecessary iterations and improving the overall efficiency and success rate of FPGA design. The method can be applied to different FPGA architectures and layout tools and has broad application prospects.

[0031] The embodiment of the present invention provides a wiring optimization method for FPGA circuit layout. It should be noted that the wiring optimization method for FPGA circuit layout provided by the embodiment of the present invention can be executed by a wiring optimization device for FPGA circuit layout. The wiring optimization device for FPGA circuit layout can be implemented as part or all of an electronic device through software, hardware, or a combination of software and hardware. The electronic device can be a server or a terminal. The server in the embodiment of the present application can be a single server or a server cluster composed of multiple servers. The terminal in the embodiment of the present application can be a smart phone, a personal computer, a tablet computer, a wearable device, and other smart hardware devices such as an intelligent robot. In the following method embodiments, the execution subject is an electronic device as an example for explanation.

[0032] According to an embodiment of the present invention, an embodiment of a wiring optimization method for FPGA circuit layout is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] In this embodiment, a wiring optimization method for FPGA circuit layout is provided, which can be used for the above-mentioned electronic equipment. Figure 1is a flow chart of a wiring optimization method for FPGA circuit layout according to an embodiment of the present invention, such as Figure 1 As shown, the process includes the following steps: Step S101, obtaining initial layout data of the FPGA circuit, and generating a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit.

[0034] Specifically, the initial data generated during the FPGA circuit layout phase is obtained from the FPGA layout tool. The initial layout data of the FPGA circuit includes the circuit netlist, the location information of the logic units, and the distribution of wiring resources, wherein the main data includes the location of each logic unit, the connection relationship of each signal line, and the total amount of wiring resources in each area.

[0035] Furthermore, during the FPGA layout process, the layout tool generates a congestion heat map of the current layout at each stage. The congestion heat map is generated by calculating the routing resource requirements and the regional density of the layout. Each pixel of the heat map represents an area in the FPGA layout, and its value indicates the degree of congestion in the area.

[0036] Step S102, using a convolutional neural network model to perform feature analysis on a congestion heat map of the FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout.

[0037] Specifically, a layout congestion heat map and a routing feasibility prediction result are obtained, and a convolutional neural network model is trained using the layout congestion heat map and the routing feasibility prediction result to obtain a trained convolutional neural network model.

[0038] Furthermore, a large number of layout congestion heat maps were generated through layout tools such as GPlace (Global Placement) as training data for the convolutional neural network model. The training data included tens of thousands of layout samples, covering the congestion conditions at different layout stages (such as global layout and detailed layout).

[0039] Furthermore, if Figure 2As shown in the figure, during the training phase of the model, a large number of layout congestion heat maps are used as input. The convolutional neural network model learns the relationship between the layout congestion heat map and the final wiring success or failure. The training process of the convolutional neural network model adopts the stochastic gradient descent method (SGD for short), and optimizes hyperparameters such as learning rate and batch size to ensure the high accuracy and low misclassification rate of the convolutional neural network model. Data enhancement and regularization techniques are also used in the training process of the convolutional neural network model to avoid overfitting of the model. The final training results of the convolutional neural network model show that on the test set, the convolutional neural network model can predict the routability of the FPGA circuit layout with an accuracy of 97%.

[0040] Furthermore, if Figure 2 As shown, the congestion heat map of the FPGA circuit layout is input into the trained convolutional neural network model for analysis, and the predicted routability result, i.e., the routing rate label, is output.

[0041] Step S103 , optimizing and adjusting the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain a routing optimization result of the FPGA circuit layout.

[0042] Specifically, by reading the output results of the CNN model, the optimization strategy of the layout tool is dynamically adjusted and passed to the layout tool, ultimately improving the routability of the layout; in practical applications, the convolutional neural network model can be integrated into the FPGA layout tool to provide routability prediction results in real time. When it is identified that the current layout of the FPGA circuit may be difficult to route, the feedback mechanism will automatically adjust the optimization parameters of the layout tool, such as increasing the circuit density in specific areas, optimizing the routing path of signal lines, etc.

[0043] The present embodiment provides a routing optimization method for FPGA circuit layout, which generates a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit; uses a convolutional neural network model to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout; optimizes and adjusts the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain a routing optimization result of the FPGA circuit layout; uses convolutional neural network technology to quickly and accurately predict whether the FPGA circuit layout is routable by analyzing the congestion heat map during the FPGA circuit layout process, which can not only significantly reduce invalid layout and routing iterations, but also dynamically optimize and adjust the FPGA circuit layout through a feedback mechanism, thereby improving the routing efficiency and routing success rate of the FPGA circuit layout and reducing design time and resource consumption.

[0044] In this embodiment, a wiring optimization method for FPGA circuit layout is provided, which can be used for the above-mentioned electronic equipment, etc. Figure 3 is a flow chart of a wiring optimization method for FPGA circuit layout according to an embodiment of the present invention, such as Figure 3 As shown, the process includes the following steps: Step S301, obtaining initial layout data of the FPGA circuit, and generating a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit.

[0045] Specifically, the above step S301 includes: Step S3011, calculating the path requirements of each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit.

[0046] In some optional implementations, the above step S3011 includes: Step a1, determining the starting point, the ending point and the intermediate passing area of ​​each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit.

[0047] Specifically, each signal line in the FPGA circuit is decomposed to determine its starting point and end point, as well as the intermediate passing area that needs to be passed through. The intermediate passing area is the wiring area that needs to be passed between the starting point and the end point of the signal line.

[0048] Step a2: Based on the starting point and the end point, a possible routing path of each signal line is determined using a path allocation algorithm.

[0049] Specifically, the path allocation algorithm can use Manhattan distance, Algorithms and other algorithms.

[0050] Step a3, based on the possible routing paths of each signal line, count the number of times each signal line passes through the intermediate passing area, and generate the path requirements of each signal line.

[0051] Specifically, the number of times the signal line passes through each wiring area (ie, the intermediate passing area) is counted, and the number of times the signal line passes through the wiring area is accumulated to obtain the path requirement of each signal line.

[0052] Step S3012, dividing the FPGA circuit layout into a plurality of grid areas, and determining the cumulative path requirements of the signal lines in each grid area based on the path requirements of each signal line.

[0053] Specifically, the FPGA circuit layout is divided into multiple grid areas, each grid area corresponds to a pixel point in the congestion heat map, and the size of each grid area is preset by the tool and can be configured according to the accuracy requirements (for example, each grid area covers 4×4 logic units), and then the cumulative path requirements of the signal lines in each grid area are calculated.

[0054] Step S3013, obtaining available routing resources in each grid area, and calculating the congestion level value of each grid area based on the accumulated path requirements of the signal lines in each grid area and the available routing resources in each grid area.

[0055] Specifically, according to the physical architecture of the FPGA, the available wiring resources in each grid area (such as the number of connection channels between logic units) are obtained; and then the congestion level of each grid area is calculated as follows: congestion level = (available wiring resources / accumulated path requirements of signal lines) × 100%.

[0056] Step S3014, constructing a congestion heat map of the FPGA circuit layout based on the congestion level values ​​of each grid area.

[0057] Specifically, when the cumulative path demand of signal lines in each grid area exceeds the available routing resources in each grid area, the grid area is considered "congested", and the congestion level of each grid area is represented by a numerical value (for example, 0 means no congestion and 100 means full congestion).

[0058] Furthermore, the congestion level of each grid area is mapped to a grayscale value, for example, 0-255, where 0 represents no congestion (black) and 255 represents full congestion (white); the congestion heat map is output in the form of a grayscale image, where each pixel corresponds to a grid area in the FPGA circuit layout.

[0059] Furthermore, the congestion heat map is updated in real time at each stage of the layout process (e.g., global layout, detailed layout), and the FPGA circuit layout strategy is adjusted according to the congestion level, such as reallocating logic cell locations or optimizing signal line paths.

[0060] Step S302: Use a convolutional neural network model to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain a routing feasibility prediction value for the FPGA circuit layout. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0061] Step S303, optimizing and adjusting the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain the routing optimization result of the FPGA circuit layout. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0062] The present embodiment provides a wiring optimization method for FPGA circuit layout, which divides the FPGA circuit layout into multiple grid areas, calculates the congestion level of each grid area using the accumulated path requirements of signal lines in each grid area and the available wiring resources in each grid area, and then constructs a congestion heat map of the FPGA circuit layout, thereby achieving accurate calculation of resource requirements and resource supply in the FPGA circuit layout, and accurately displays the congestion level in each grid area through the congestion heat map, laying a foundation for accurate prediction of the wiring feasibility of the subsequent FPGA circuit layout and feedback optimization of the FPGA circuit layout.

[0063] In this embodiment, a wiring optimization method for FPGA circuit layout is provided, which can be used for the above-mentioned electronic equipment. Figure 4 is a flow chart of a wiring optimization method for FPGA circuit layout according to an embodiment of the present invention, such as Figure 4 As shown, the process includes the following steps: Step S401, obtaining initial layout data of the FPGA circuit, and generating a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit. Figure 3 Step S301 of the illustrated embodiment will not be described in detail here.

[0064] Step S402: Use a convolutional neural network model to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout.

[0065] Specifically, Figure 5 As shown in the figure, the convolutional neural network model includes an input layer, multiple convolutional layers, multiple pooling layers and a fully connected layer; the convolutional neural network model is designed based on a multi-layer convolution and pooling structure, and is used to extract key features from the congestion heat map; specifically, the input layer receives the congestion heat map representing the FPGA layout, and the CNN model includes four convolutional layers, each of which is followed by a pooling layer to reduce the size of the feature map while retaining important information, and finally outputs the prediction result through the fully connected layer; wherein, the signal transmission between each layer follows the standard forward propagation mode, and finally outputs the routing feasibility prediction value of the FPGA circuit layout; wherein, the convolutional layer and the pooling layer can use the ReLU activation function (Rectified LinearUnit, linear rectification function) to quickly extract features, and the Sigmoid activation function (which maps any real number to between 0 and 1 and has been widely used in neural network activation functions) is used in the last layer of the fully connected layer to convert the output of the network into the probability of whether the FPGA circuit layout is easy to route successfully, thereby achieving the classification task.

[0066] The above step S402 includes: Step S4021, transmitting the congestion heat map of the FPGA circuit layout to the convolution layer through the input layer.

[0067] Specifically, the size of the congestion heat map input to the input layer is 64×64×1, which means that the resolution of the congestion heat map is 64×64 and the channel is 1 (single-channel grayscale image).

[0068] Step S4022, using multiple convolutional layers to perform a convolution operation on the congestion heat map of the FPGA circuit layout to obtain a spatial feature map of the FPGA circuit layout.

[0069] Specifically, in each convolutional layer, multiple filters are used to perform convolution operations on the input congestion heatmap to generate feature maps that capture the spatial features in the layout, such as the congestion level of the area and the distribution of signal lines.

[0070] Furthermore, the multiple convolutional layers include the first convolutional layer, the second convolutional layer, the third convolutional layer and the fourth convolutional layer. Each convolution operation can extract different levels of features of the input data: the first layer usually captures basic features (such as edges, lines, etc.); the second and subsequent layers can gradually extract more complex patterns (such as the local structure of congestion hotspots); using 4 convolutional layers enables the model to learn feature representations from simple to complex and adapt to the multi-level information in the congestion heat map.

[0071] Furthermore, the first convolutional layer mainly extracts low-level features of the input congestion heat map, such as basic image patterns such as local edges and lines. Its function is to identify local area characteristics in the heat map through simple filters, such as high-density congestion or low-density blank areas in a certain area. The characteristic is that the output feature map retains more original information, and the spatial distribution of pixel values ​​is still close to the input heat map; the second convolutional layer begins to identify slightly higher-level features, such as local patterns in specific areas (such as the distribution form or shape of high-congestion areas in heat maps). Its function is to combine the low-level features extracted by the first layer to capture slightly larger spatial patterns. The characteristic is that the spatial dimension of the feature map is usually reduced by pooling, but the number of channels increases, and the feature representation is richer; the third convolutional layer The extracted features are more abstract, such as the interaction between multiple high-congestion areas or the distribution trend of local hotspots. Its role is to further capture contextual information in a larger range, including the association between complex congestion patterns and routing resources. The characteristics are that the size of the feature map is further reduced, and the feature channel contains more abstract information, which is highly related to the routing complexity of the FPGA; the fourth convolutional layer convolutionally extracts global features to capture the global pattern of the entire congestion heat map, such as the overall congestion level, the number of hotspot areas and their distribution. Its role is to provide a high-level comprehensive feature input for the fully connected layer, which is used to predict whether the FPGA layout is routable. The characteristics are that the size of the feature map is the smallest, but the channel contains the most important abstract information for routing rate prediction.

[0072] Furthermore, setting four convolutional layers has a layer-by-layer effect: from low level to high level, each convolutional layer gradually extracts the features of the data to form a hierarchical feature representation; the specific effect is that the first layer focuses on local features, and gradually to the fourth layer, focuses on overall characteristics, and then the output of the feature map of the fourth layer is the basis of the final prediction result of the model, which gathers key information from local to global, and is used to classify whether the layout is routable; specifically, the effects of setting four convolutional layers include: (1) Gradually extract features to improve model performance.

[0073] (2) Increase model capacity and improve expressiveness: Deep models (more convolutional layers) have stronger feature learning capabilities than shallow models (fewer convolutional layers) and can more comprehensively understand the nonlinear distribution of data; the congestion characteristics of FPGA layout may be very complex, and multi-layer convolution helps capture complex geometric and spatial characteristics.

[0074] (3) Reduce the risk of overfitting: Compared with models with a single or a small number of convolutional layers, four convolutional layers can reduce the dependence on a single feature by introducing multiple feature learning processes, thereby enhancing the generalization ability of the model.

[0075] (4) Gradually reduce dimension and reduce computational complexity: The pooling operation after each convolutional layer will gradually reduce the size of the feature map (for example, from 64×64 to 32×32, and then to 16×16, etc.), greatly reducing computational complexity; through the combination of multiple layers of convolution and pooling, it is possible to significantly reduce unnecessary calculations while retaining important features.

[0076] (5) Striking a balance between model complexity and computational efficiency: The routability prediction of FPGA layout needs to strike a balance between high precision and high efficiency. Four convolutional layers can better meet the needs of complex feature learning than shallow models, while avoiding the excessive computational burden brought by overly deep models.

[0077] Step S4023, using multiple pooling layers to reduce the size of the spatial feature map of the FPGA circuit layout.

[0078] Specifically, the pooling layer further reduces the size of the feature map through the maximum pooling operation, reducing the computational complexity while retaining important features.

[0079] Furthermore, the input size of the first convolutional layer is 64×64×1, the number of filters is 16, the size is 3×3, the stride is 1, the padding method is "same", and the output size is 64×64×16, that is, the congestion heat map still maintains the original resolution, but the number of channels is increased to 16, and 16 basic features are extracted to identify local edges and simple patterns; the input of the first pooling layer is 64×64×16, the pooling method is maximum pooling, the size is 2×2, the stride is 2, and the output size is 32×32×16, that is, the maximum value is taken in each 2×2 area, which reduces the size and retains important information , which is used to reduce the dimension while retaining the local significant features; the input of the second convolutional layer is 32×32×16, that is, the number of filters is 32, the size is 3×3, the stride is 1, the padding method is "same", and the output size is 32×32×32. The resolution is 32×32, and the feature channels are increased to 32, which extracts more complex regional features, and is used to extract local feature patterns and hot spot distribution; the input of the second pooling layer is 32×32×32, the pooling method is maximum pooling, the size is 2×2, the stride is 2, and the output size is 16×16×32. Each 2×2 area is further reduced in dimension , which is used to preserve the feature context and reduce the computational complexity; the input of the third convolutional layer is 16×16×32, that is, the number of filters is 64, the size is 3×3, the stride is 1, the padding method is "same", and the output size is 16×16×64, that is, the resolution remains at 16×16, and the number of channels is increased to 64, extracting more abstract features, which is used to identify complex patterns, such as local connections of hotspots; the input of the third pooling layer is 16×16×64, the pooling method is maximum pooling, the size is 2×2, the stride is 2, and the output size is 8×8×64, which is reduced again, and the function is The feature size is further reduced to retain important information; the input of the fourth convolutional layer is 8×8×64, that is, the number of filters is 128, the size is 3×3, the stride is 1, the padding method is "same", and the output size is 8×8×128, that is, the number of channels is increased to 128, and global features are extracted to form high-level abstract features for classification; the input of the fourth pooling layer is 8×8×128, the pooling method is maximum pooling, the size is 2×2, the stride is 2, and the output size is 4×4×128, which is finally reduced to a 4×4 feature map, and each feature map channel retains important global features.

[0080] Step S4024, based on the spatial feature graph of the FPGA circuit layout after size reduction, classification is performed using a fully connected layer to obtain a routing feasibility prediction value of the FPGA circuit layout.

[0081] Specifically, the input of the fully connected layer is 4×4×128, and the size after flattening is 2048. All feature channels are flattened into one dimension, which serves as the input of the final classification layer to predict whether it is routable.

[0082] Furthermore, after multiple convolution and pooling operations, the feature map is flattened and classified through a fully connected layer to output a prediction result of whether the current layout is routable, that is, a routing feasibility prediction value of the FPGA circuit layout, wherein the routing feasibility prediction value of the FPGA circuit layout can be a probability value indicating whether the FPGA circuit layout is easy to route successfully.

[0083] Step S403, optimizing and adjusting the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain the routing optimization result of the FPGA circuit layout. Figure 3 Step S303 of the illustrated embodiment will not be described in detail here.

[0084] This embodiment provides a wiring optimization method for FPGA circuit layout. The convolutional neural network model uses multiple convolutional layers and pooling layers to perform convolution and pooling operations on the congestion heat map layer by layer, and then outputs the wiring feasibility prediction value of the FPGA circuit layout through a fully connected layer. A multi-stage convolutional neural network structure is used in combination with the congestion heat map to achieve high-precision routability prediction of the FPGA circuit layout.

[0085] In this embodiment, a wiring optimization method for FPGA circuit layout is provided, which can be used for the above-mentioned electronic equipment. Figure 6 is a flow chart of a wiring optimization method for FPGA circuit layout according to an embodiment of the present invention, such as Figure 6 As shown, the process includes the following steps: Step S601, obtaining initial layout data of the FPGA circuit, and generating a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit. Figure 4 Step S401 of the illustrated embodiment will not be described in detail here.

[0086] Step S602: Use a convolutional neural network model to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout. Figure 4 Step S402 of the illustrated embodiment will not be described in detail here.

[0087] Step S603 , optimizing and adjusting the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain a routing optimization result of the FPGA circuit layout.

[0088] Specifically, the above step S603 includes: Step S6031, comparing the routing feasibility prediction value of the FPGA circuit layout with a preset threshold.

[0089] Step S6032: If the routing feasibility prediction value of the FPGA circuit layout is less than a preset threshold, a congested area to be optimized in the congestion heat map of the FPGA circuit layout is identified.

[0090] Specifically, assuming that the preset threshold is 50%, if the routing feasibility prediction value of the FPGA circuit layout is lower than 50%, the optimization mechanism is triggered; if the routing feasibility prediction value of the FPGA circuit layout is higher than 50%, no optimization is required and the FPGA circuit layout process continues.

[0091] Furthermore, based on the high congestion areas in the congestion heat map, the specific grid areas that need to be adjusted (for example, grid areas with a congestion level greater than 80%) are determined, namely, the congestion areas to be optimized; among them, for high congestion areas, it is necessary to reduce path requirements or increase resource allocation, and for low congestion areas, some resources can be appropriately freed up.

[0092] Step S6033, performing parameter optimization on the congested area to be optimized, and updating the FPGA circuit layout based on the optimized parameters to obtain an updated FPGA circuit layout; the parameters include circuit density, signal line routing path, and routing resources.

[0093] Specifically, circuit density optimization: increase the grid size in high-congestion areas and reduce the density of logic cells; signal line routing path optimization: optimize the routing paths of signal lines to avoid multiple paths passing through certain hot spots; resource allocation optimization: dynamically increase routing resources in hot spots (such as allocating more channels).

[0094] Furthermore, after receiving the feedback, the layout tool automatically adjusts relevant parameters, such as adjusting the priority of circuit unit distribution or signal line weight.

[0095] Step S6034, verify and optimize the updated FPGA circuit layout, and determine the routing optimization result of the FPGA circuit layout based on the verification and optimization result.

[0096] Specifically, the updated optimization parameters are applied to regenerate the layout and output a new congestion heat map. The CNN model is used to re-predict the feasibility of the updated layout to verify whether the optimization is effective. If the optimization effect does not meet the set goal, adjustments are continued until the layout feasibility prediction value reaches the threshold.

[0097] Furthermore, the optimization strategy can be dynamically adjusted at each stage of FPGA circuit layout. For example, in the global layout stage, the layout process can be terminated in advance based on the predicted routing feasibility value of the FPGA circuit layout to avoid invalid optimization iterations; in the detailed layout stage, local optimization can be performed on areas that are difficult to route (such as reducing the length of signal lines in critical paths) to improve the success rate of the final layout.

[0098] The present embodiment provides a routing optimization method for FPGA circuit layout. The method determines the congested area to be optimized in the congestion heat map of the FPGA circuit layout by comparing the routing feasibility prediction value of the FPGA circuit layout with a preset threshold value, and then optimizes the parameters of the congested area to be optimized, thereby realizing dynamic adjustment of the FPGA circuit layout. The routing optimization result of the FPGA circuit layout is then determined according to the updated verification optimization result of the FPGA circuit layout. Ineffective layout iterations are avoided through real-time routability prediction and feedback adjustment. The routing scheme of the optimized FPGA circuit layout has a higher routing success rate, and the overall layout efficiency is improved. The prediction accuracy and minimum running time of the routability of the FPGA circuit layout are improved, and the routing design efficiency of the FPGA circuit layout is improved.

[0099] In this embodiment, a wiring optimization device for FPGA circuit layout is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0100] This embodiment provides a wiring optimization device for FPGA circuit layout, such as Figure 7 As shown, including: The generating module 701 is used to obtain the initial layout data of the FPGA circuit, and generate a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit.

[0101] The prediction module 702 is used to perform feature analysis on the congestion heat map of the FPGA circuit layout using a convolutional neural network model to obtain a routing feasibility prediction value of the FPGA circuit layout.

[0102] The layout optimization module 703 is used to optimize and adjust the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain the routing optimization result of the FPGA circuit layout.

[0103] In some optional implementations, the generating module 701 includes: The first calculation unit is used to calculate the path requirements of each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit.

[0104] The partitioning unit is used to divide the FPGA circuit layout into a plurality of grid areas, and determine the cumulative path requirements of the signal lines in each grid area based on the path requirements of each signal line.

[0105] The second calculation unit is used to obtain available wiring resources in each grid area, and calculate the congestion level value of each grid area based on the accumulated path requirements of the signal lines in each grid area and the available wiring resources in each grid area.

[0106] The construction unit is used to construct a congestion heat map of the FPGA circuit layout based on the congestion degree values ​​of each grid area.

[0107] In some optional implementations, the first computing unit includes: The first determination subunit is used to determine the starting point, the ending point and the intermediate passing area of ​​each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit.

[0108] The second determining subunit is used to determine the possible routing paths of each signal line based on the starting point and the ending point by using a path allocation algorithm.

[0109] The generation subunit is used to count the number of times each signal line passes through the intermediate passing area based on the possible routing paths of each signal line, and generate the path requirements of each signal line.

[0110] In some optional implementations, the prediction module 702 includes: The transmission unit is used to transmit the congestion heat map of the FPGA circuit layout to the convolution layer through the input layer.

[0111] The convolution unit is used to perform a convolution operation on the congestion heat map of the FPGA circuit layout using multiple convolution layers to obtain a spatial feature map of the FPGA circuit layout.

[0112] A pooling unit is used to reduce the size of the spatial feature map of the FPGA circuit layout using multiple pooling layers.

[0113] The classification unit is used to perform classification based on the spatial feature map of the FPGA circuit layout after the size reduction by using a fully connected layer to obtain a routing feasibility prediction value of the FPGA circuit layout.

[0114] In some optional embodiments, it also includes: The training module is used to obtain a layout congestion heat map and a routing feasibility prediction result, and train a convolutional neural network model using the layout congestion heat map and the routing feasibility prediction result to obtain a trained convolutional neural network model.

[0115] In some optional implementations, the layout optimization module 703 includes: The comparison unit is used to compare the routing feasibility prediction value of the FPGA circuit layout with a preset threshold.

[0116] The identification unit is used to identify a congested area to be optimized in a congestion heat map of the FPGA circuit layout if the routing feasibility prediction value of the FPGA circuit layout is less than a preset threshold.

[0117] The updating unit is used to optimize the parameters of the congested area to be optimized, and update the FPGA circuit layout based on the optimized parameters to obtain an updated FPGA circuit layout. The parameters include circuit density, signal line routing path and routing resources.

[0118] The verification unit is used to verify and optimize the updated FPGA circuit layout, and determine the wiring optimization result of the FPGA circuit layout based on the verification optimization result.

[0119] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0120] In this embodiment, a wiring optimization device for FPGA circuit layout is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0121] The embodiment of the present invention also provides a computer device having the above Figure 7 A wiring optimization device for FPGA circuit layout is shown.

[0122] See also Figure 8 , Figure 8 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 8 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0123] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0124] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0125] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0126] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0127] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 8 The example of connecting through bus is taken in the following.

[0128] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device may be a touch screen.

[0129] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0130] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0131] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A wiring optimization method for FPGA circuit layout, characterized in that: The method comprises: Acquire initial layout data of the FPGA circuit, and generate a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit; Using a convolutional neural network model to perform feature analysis on the congestion heat map of the FPGA circuit layout, and obtain a routing feasibility prediction value of the FPGA circuit layout; The FPGA circuit layout is optimized and adjusted based on the routing feasibility prediction value of the FPGA circuit layout to obtain a routing optimization result of the FPGA circuit layout.

2. The method according to claim 1, characterized in that The generating of a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit comprises: Calculating the path requirements of each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit; Dividing the FPGA circuit layout into a plurality of grid areas, and determining the cumulative path requirements of the signal lines in each grid area based on the path requirements of each signal line; Obtaining available wiring resources in each grid area, and calculating a congestion level value of each grid area based on the accumulated path requirements of the signal lines in each grid area and the available wiring resources in each grid area; A congestion heat map of the FPGA circuit layout is constructed based on the congestion level values ​​of the grid areas.

3. The method according to claim 2, characterized in that The calculating the path requirements of each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit includes: Determine the starting point, the ending point and the intermediate passing area of ​​each signal line in the FPGA circuit based on the initial layout data of the FPGA circuit; Based on the starting point and the ending point, determining a possible routing path for each signal line using a path allocation algorithm; Based on the possible wiring paths of the signal lines, the number of times each signal line passes through the intermediate passing area is counted to generate the path requirements of each signal line.

4. The method according to claim 1, characterized in that: The convolutional neural network model includes an input layer, multiple convolutional layers, multiple pooling layers and a fully connected layer; the convolutional neural network model is used to perform feature analysis on the congestion heat map of the FPGA circuit layout to obtain a routing feasibility prediction value of the FPGA circuit layout, including: Transmitting the congestion heat map of the FPGA circuit layout to the convolution layer through the input layer; Using a plurality of the convolutional layers to perform a convolution operation on the congestion heat map of the FPGA circuit layout to obtain a spatial feature map of the FPGA circuit layout; Using a plurality of the pooling layers to reduce the size of the spatial feature map of the FPGA circuit layout; Based on the spatial feature map of the reduced-size FPGA circuit layout, a fully connected layer is used for classification to obtain a routing feasibility prediction value of the FPGA circuit layout.

5. The method according to claim 1, characterized in that Before performing feature analysis on the congestion heat map of the FPGA circuit layout using the convolutional neural network model to obtain a routing feasibility prediction value of the FPGA circuit layout, the method further includes: Obtain a layout congestion heat map and a routing feasibility prediction result, and use the layout congestion heat map and the routing feasibility prediction result to train the convolutional neural network model to obtain a trained convolutional neural network model.

6. The method according to claim 1, characterized in that The step of optimizing and adjusting the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain a routing optimization result of the FPGA circuit layout includes: Comparing the routing feasibility prediction value of the FPGA circuit layout with a preset threshold; If the routing feasibility prediction value of the FPGA circuit layout is less than the preset threshold, identifying a congested area to be optimized in a congestion heat map of the FPGA circuit layout; Optimizing parameters of the congested area to be optimized, and updating the FPGA circuit layout based on the optimized parameters to obtain an updated FPGA circuit layout; the parameters include circuit density, signal line routing path, and routing resources; The updated FPGA circuit layout is verified and optimized, and a wiring optimization result of the FPGA circuit layout is determined based on the verification and optimization result.

7. A wiring optimization device for FPGA circuit layout, characterized in that: The device comprises: A generation module, used to obtain initial layout data of the FPGA circuit, and generate a congestion heat map of the FPGA circuit layout based on the initial layout data of the FPGA circuit; A prediction module, used for performing feature analysis on the congestion heat map of the FPGA circuit layout using a convolutional neural network model to obtain a routing feasibility prediction value of the FPGA circuit layout; The layout optimization module is used to optimize and adjust the FPGA circuit layout based on the routing feasibility prediction value of the FPGA circuit layout to obtain the routing optimization result of the FPGA circuit layout.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the wiring optimization method for FPGA circuit layout according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the wiring optimization method for FPGA circuit layout according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the wiring optimization method for FPGA circuit layout according to any one of claims 1 to 6.

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