GPU synchronization device and image processing system

Abstract

The invention provides a GPU synchronization device and an image processing system. The synchronization device comprises a first processing unit used for receiving a preset effective clock signal and outputting the effective clock signal to at least one GPU; the second processing unit is used for receiving the first frame synchronization signal of the at least one GPU and outputting a second frame synchronization signal to the at least one GPU; wherein the second frame synchronization signal is an effective synchronization signal under the condition that the first frame synchronization signal indicates that the GPU is in a frame synchronization state; the effective synchronization signal is used for indicating that the at least one GPU is in a frame synchronization state; and based on the effective clock signal, the GPU outputs frame data to be displayed in a state that the second frame synchronization signal is the effective synchronization signal.

Description

Technical Field

[0001] The present disclosure relates to the field of image processing, and in particular to a synchronization device of a GPU (Graphics Processing Unit) and an image processing system. Background Art

[0002] Video wall is an image, graphic and text display system, which is a large-screen video display wall composed of multiple display units. Video wall has a wide range of applications in many fields, including but not limited to monitoring centers, command centers, video conference rooms, exhibition halls and other places, and is used to display real-time video monitoring, multimedia information, data analysis results and other content. Video wall usually consists of splicing unit, multi-screen processor, signal switching and distribution, control system and other parts. Among them, multi-screen processor is often the core of splicing video wall, which is used to divide a complete image signal and distribute it to each video display unit.

[0003] However, video walls often require dedicated displays and the cooperation of the transmitter, or a dedicated signal control system to achieve signal synchronization among the displays. This has low versatility, high cost and complex deployment. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a GPU synchronization device and an image processing system to solve at least one problem existing in the prior art.

[0005] To achieve the above-mentioned purpose, the technical solution of the embodiment of the present disclosure is implemented as follows: On the one hand, the embodiment of the present disclosure provides a synchronization device of a GPU, including: A first processing unit, configured to receive a preset valid clock signal and output the valid clock signal to at least one GPU; A second processing unit is configured to receive a first frame synchronization signal of the at least one GPU, and output a second frame synchronization signal to the at least one GPU; wherein the second frame synchronization signal is a valid synchronization signal when the first frame synchronization signals all indicate that the GPU is in a frame synchronization state; and the valid synchronization signal is used to indicate that the at least one GPU is in a frame synchronization state; The GPU outputs frame data to be displayed based on the valid clock signal in a state where the second frame synchronization signal is the valid synchronization signal.

[0006] In some embodiments, the first processing unit includes: An OR operation unit, comprising a plurality of input terminals, and configured to perform an OR operation on signals received by the plurality of input terminals; At least part of the multiple input terminals of the OR operation unit are respectively used to connect to the GPU; Wherein, any of the GPUs inputs the valid clock signal to the OR operation unit, or a preset external input inputs the valid clock signal to the OR operation unit through the input terminal; The output end of the OR operation unit is connected to the at least one GPU, and is used to provide the effective clock signal to the at least one GPU.

[0007] In some embodiments, a plurality of input terminals of the OR operation unit are respectively connected to pull-down resistors; the pull-down resistors are used to set the input signals of the input terminals to logic 0 when the valid clock signal is not received.

[0008] In some embodiments, the first processing unit includes: A signal selection unit, comprising a plurality of input terminals, for selecting a valid clock signal from the signals received by the plurality of input terminals as an output signal; At least part of the plurality of input terminals of the signal selection unit are respectively used to connect to the GPU; Wherein, any of the GPUs inputs the valid clock signal to the signal selection unit, or a preset external input inputs the valid clock signal to the signal selection unit through the input terminal; The output end of the signal selection unit is connected to the at least one GPU, and is used to provide the effective clock signal to the at least one GPU.

[0009] In some embodiments, the second processing unit includes: AND unit; The AND operation unit includes a plurality of input terminals; at least part of the plurality of input terminals of the AND operation unit are respectively used to connect to the GPU and receive the first frame synchronization signal provided by the GPU; Among them, the first frame synchronization signal of high level is the valid synchronization signal.

[0010] In some embodiments, a plurality of input terminals of the AND operation unit are respectively connected to pull-up resistors; the pull-up resistors are used to set the input terminals not connected to the GPU to logic 1.

[0011] In some embodiments, the second processing unit includes: Counting unit; The counting unit comprises a plurality of input terminals; at least part of the plurality of input terminals of the counting unit are respectively used to connect to the GPU and receive the first frame synchronization signal provided by the GPU; The counting unit is used for counting valid synchronization signals in the received first frame synchronization signal, and outputting the second frame synchronization signal to the at least one GPU when the count value is consistent with the number of the received first frame synchronization signals.

[0012] In some embodiments, the synchronization device includes N GPU interfaces; the GPU interfaces include at least N first connection ends connected to the first processing unit and N second connection ends connected to the second processing unit; wherein N is an integer greater than or equal to 2; The synchronization device is connected to the M GPUs through the GPU interface, and is used to provide the effective clock signal to the M GPUs through the first processing unit, and provide the second frame synchronization signal to the M GPUs through the second processing unit; Wherein, M is a positive integer less than or equal to N.

[0013] In some embodiments, the synchronization device further comprises: A cascade input terminal and a cascade output terminal; The cascade input terminal is connected to the cascade output terminal of another synchronization device in the cascade; The cascade output terminal and the cascade input terminal are used to transmit the valid clock signal and / or the valid synchronization signal between the plurality of cascaded synchronization devices.

[0014] In some embodiments, the cascade input terminal includes: a clock cascade input terminal; the cascade output terminal includes: a clock cascade output terminal; The clock cascade input terminal is connected to the input terminal of the first processing unit and is used to connect to the clock cascade output terminal of another synchronization device in the cascade; The clock cascade output terminal is connected to the output terminal of the first processing unit.

[0015] In some embodiments, when the clock cascade input terminal is not connected to the clock cascade output terminal of the other synchronization device, the clock cascade input terminal is floating; and / or When the clock cascade output terminal is floating and is not connected to the clock cascade input terminal of another synchronization device, the clock cascade output terminal is floating.

[0016] In some embodiments, the cascade input terminal includes: a first synchronization input terminal; the cascade output terminal includes: a first synchronization output terminal; The first synchronization input terminal is connected to the input terminal of the second processing unit and is used to connect to the first synchronization output terminal of another cascaded synchronization device; The first synchronous output terminal is connected to the output terminal of the second processing unit.

[0017] In some embodiments, the cascade input terminal further includes: a second synchronization input terminal, and the cascade output terminal further includes: a second synchronization output terminal; The second synchronization input terminal and the second synchronization output terminal are both connected to the at least one GPU for transmitting the valid synchronization signal, and the second synchronization input terminal is used to connect to the second synchronization output terminal of another cascaded synchronization device, or to connect to the first synchronization output terminal of the synchronization device.

[0018] In some embodiments, when no other synchronization device is cascaded on the first side of the synchronization device, and another synchronization device is cascaded on the second side: The first synchronization input terminal and the second synchronization output terminal are both floating; The first synchronization output terminal is connected to the first synchronization input terminal of the other synchronization device; The second synchronization input terminal is connected to the second synchronization output terminal of the other synchronization device.

[0019] In some embodiments, when a first synchronization device is cascaded to a first side of the synchronization device, and a second synchronization device is cascaded to a second side of the synchronization device: The first synchronization input terminal is connected to the first synchronization output terminal of the first synchronization device; The second synchronization output terminal is connected to the second synchronization input terminal of the first synchronization device; The first synchronization output terminal is connected to the first synchronization input terminal of the second synchronization device; The second synchronization input terminal is connected to the second synchronization output terminal of the second synchronization device; The first synchronization device and the second synchronization device are the same as the synchronization device.

[0020] In some embodiments, when another synchronization device is cascaded to the first side of the synchronization device, and no other synchronization device is cascaded to the second side: The first synchronization input terminal is connected to the first synchronization output terminal of the other synchronization device; The second synchronization output terminal is connected to the second synchronization input terminal of the other synchronization device; The first synchronization output terminal is connected to the second synchronization input terminal.

[0021] In some embodiments, when the synchronization device is not cascaded with other synchronization devices: The first synchronization input terminal and the second synchronization output terminal are both floating; The first synchronization output terminal is connected to the second synchronization input terminal.

[0022] In some embodiments, the synchronization device further comprises: One or more synchronization indicating units; the synchronization indicating unit is used to receive a clock synchronization state signal sent by the GPU based on the valid clock signal, indicating that the GPU is in a clock synchronization state.

[0023] On the other hand, an embodiment of the present disclosure provides an image processing system, including: One or more cascaded synchronization devices of any of the above; There are multiple GPUs, and each of the synchronization devices is connected to one or more of the GPUs.

[0024] In some embodiments, the image processing system further comprises: A display module connected to the multiple GPUs; The GPU outputs frame data to be displayed to the display module based on the valid clock signal and the valid synchronization signal output by the synchronization device; The display module displays a spliced ​​picture based on the frame data output by the multiple GPUs.

[0025] In the technical solution provided in the present disclosure, a synchronization device for a GPU is provided. The device processes the received valid clock signal through a simple first processing unit and a second processing unit and provides it to at least one GPU so that at least one GPU receives the same valid clock signal as a reference clock for outputting image data; and when one or more connected GPUs send a valid synchronization signal indicating a frame synchronization state, a second frame synchronization signal is provided to each GPU to inform each GPU of the current synchronization state, thereby realizing display synchronization of each GPU. In this way, the synchronization device can be used to conveniently realize signal synchronization of multiple GPUs without the need for a dedicated display system or data processing system. It is low-cost and easy to expand, and can be applied to various video walls, scenes requiring multi-display display, and scenes requiring multi-GPU image processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a GPU synchronization device provided in an embodiment of the present disclosure Figure 1 ; Figure 2 A schematic diagram of a GPU synchronization device provided in an embodiment of the present disclosure Figure 2 Figure 3 A schematic diagram of a GPU synchronization device provided in an embodiment of the present disclosure Figure 3 ; Figure 4 A schematic diagram of a GPU synchronization device provided in an embodiment of the present disclosure Figure 4 ; Figure 5 A schematic diagram of a cascade connection method for implementing a synchronization device provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of a connection mode of a synchronization device provided in an embodiment of the present disclosure without cascading; Figure 7 A wiring diagram of a synchronization device provided by an embodiment of the present disclosure applied in a system architecture; Figure 8 A flowchart of a synchronization device and a configuration method for multiple GPUs provided in an embodiment of the present disclosure; Fig. 9 A schematic diagram of the structure of a synchronization device provided by an embodiment of the present disclosure applied to a display system; Fig.10 A structural block diagram of an image processing system provided by an embodiment of the present disclosure; Fig.11 A structural block diagram of a GPU provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0028] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] In order to achieve synchronous display of multi-screen video walls, an independent video wall system (hardware or software implementation) can be used to realize video acquisition, cutting and multi-display display. The display end is required to support the frame synchronization signal sent by the video wall system to achieve multi-display synchronization. This method requires an additional dedicated system or adds a dedicated synchronization signal for the display. It is not universal and increases the cost of use and the difficulty of deployment. Alternatively, a synchronization signal may be added at the display end to ensure that the received images can be displayed synchronously. However, this method requires a dedicated display, and in actual use, the transmitter also needs to cooperate to avoid excessive synchronization delays of each display.

[0031] like Figure 1 As shown, the embodiment of the present disclosure provides a GPU synchronization device 100, comprising: The first processing unit 110 is configured to receive a preset valid clock signal clk and output the valid clock signal clk to at least one GPU; The second processing unit 120 is configured to receive a first frame synchronization signal fsync1 of the at least one GPU, and output a second frame synchronization signal fsync2 to the at least one GPU; wherein the second frame synchronization signal fsync2 is a valid synchronization signal when the first frame synchronization signal fsync1 indicates that the GPU is in a frame synchronization state; and the valid synchronization signal is used to indicate that the at least one GPU is in a frame synchronization state; Based on the effective clock signal clk, the GPU outputs frame data to be displayed in a state where the second frame synchronization signal fsync2 is the effective synchronization signal.

[0032] The first processing unit 110 may have multiple clock receiving signal channels, and receive one or more clock signals through these signal channels, and select a valid clock signal clk as the output of the first processing unit 110 to be provided to each GPU connected to the synchronization device 100 .

[0033] The valid clock signal may come from any GPU connected to the synchronization device 100. For example, a processor or other device connected to each GPU may preset one of the GPUs as a master GPU for outputting a valid clock signal, while other GPUs do not output clock signals or output invalid signals.

[0034] The effective clock signal may also come from other signal sources connected to the synchronization device 100, for example, a fixed clock signal output by a preset clock signal generator is directly input into the synchronization device 100 as the effective clock signal; for example, a clock signal provided by a processor externally connected to the synchronization device is used as the effective clock signal.

[0035] The effective clock signal may also come from other synchronization devices cascaded with the synchronization device 100, that is, multiple synchronization devices cascaded may use the same effective clock signal. For specific cascade methods, please refer to the detailed description in the relevant embodiments below.

[0036] It should be noted that, for each GPU, a fixed effective clock signal can be used in the entire process of operation after power-on, that is, the effective clock signal is synchronized once after each power-on or initialization operation, and the synchronous use of the effective clock signal can be maintained regardless of whether the picture frame is transmitted. For the transmission of pictures, each GPU is required to synchronize each frame separately. When the GPU completes the processing of a frame of the picture, such as decoding, rendering and other processing, and can send the processed data to the display module for display, the GPU can output a corresponding frame synchronization signal to indicate that the current GPU of the relevant device has completed the processing of the current frame. Therefore, in the embodiment of the present disclosure, the synchronization device 100 can use the frame synchronization signal sent by the GPU to determine whether multiple GPUs have completed the processing of the current frame, and after multiple GPUs have completed the current processing, indicate that each GPU can output the data of the current frame for display by the display device.

[0037] The second processing unit 120 is used to determine whether each GPU connected to the synchronization device 100 is in a synchronization state. The second processing unit 120 receives the first frame synchronization signal fsync1 output by each connected GPU, which is used to indicate whether the corresponding GPU has completed the processing of the current frame. The second processing unit 120 can be connected to one or more GPUs and receive the first frame synchronization signal fsync1 output by each GPU connected to it, and output a second frame synchronization signal to each GPU. It can be understood that in order to achieve the synchronization of each GPU outputting the same frame of the picture, the first frame synchronization signal fsync1 output by each GPU is to indicate that the GPU is in a frame synchronization state (or understood as a state where the processing has been completed and data can be sent), and the output second frame synchronization signal is a valid synchronization signal. For example, if the first frame synchronization signal is at a high level, it indicates that the GPU is in a frame synchronization state. When the first frame synchronization signals output by each connected GPU are all at a high level, the second processing unit 120 outputs a valid synchronization signal (i.e., a valid second frame synchronization signal, such as a high level). Correspondingly, if the first frame synchronization signal output by any at least one connected GPU is at a low level, indicating that the GPU has not completed the processing and is temporarily unable to send data, the second processing unit 120 outputs a second frame synchronization state indicating an invalid (i.e., unsynchronized) state. The above-mentioned "high level" or "low level" is only an exemplary embodiment. In practical applications, the expression form of the above-mentioned signal is not limited to this form, and different signal waveforms, signal duty cycles, signal frequencies, and signal on-offs can also be used to indicate whether the GPU is in a valid state of completing a frame of data processing and waiting to send data. The output signal of the second processing unit 120 can also adopt any of the above-mentioned signal expression forms, which will not be repeated here.

[0038] In some embodiments, the synchronization device 100 includes N GPU interfaces; the GPU interface includes at least N first connection terminals 111 connected to the first processing unit 110 and N second connection terminals 121 connected to the second processing unit 120; wherein N is an integer greater than or equal to 2; The synchronization device is connected to the M GPUs through the GPU interface, and is used to provide the effective clock signal to the M GPUs through the first processing unit, and provide the second frame synchronization signal to the M GPUs through the second processing unit; Wherein, M is a positive integer less than or equal to N.

[0039] In the disclosed embodiment, the number of GPU interfaces of the synchronization device 100 can be designed according to actual application requirements. For example, if a conventional GPU synchronization device for household or small devices is provided, such as a device used in 1 to 4 GPUs, a synchronization device with 4 GPU interfaces can be designed. For application scenarios such as large TV walls or AI (Artificial Intelligence) model training devices (or device clusters) that require high computing power, for example, when 32 or 64 GPUs are required to simultaneously process an image processing task, the synchronization device can be designed with 32 or 64 GPU interfaces, or a relatively small number of GPU interfaces, such as 8, which can be cascaded according to needs during use to expand the number of connectable GPUs and achieve flexible multi-GPU synchronization configuration.

[0040] Of course, in some scenarios, the number of GPUs required may be less than the number of GPU interfaces of the synchronization device. For example, a synchronization device with 4 GPU interfaces can be connected to only 1 GPU, or it can be connected to 2 to 4 GPUs and synchronize these 2 to 4 GPUs.

[0041] In some embodiments, Figure 2 As shown, the first processing unit 110 includes: an OR operation unit 110a; the OR operation unit 110a is used to perform OR operation processing on signals received from multiple input terminals, and at least part of the multiple input terminals of the OR operation unit 110a are respectively used to connect to GPUs. Exemplarily, the multiple input terminals of the OR operation unit 110a are respectively connected to multiple GPUs (such as Figure 2 The reference clock output terminal of GPU0 to GPU3) shown in the figure; the output terminal of the OR operation unit 110a is connected to the reference clock input terminal of each GPU; wherein at most one of the multiple reference clock output terminals is used to provide a reference clock output signal o_refclk; and the reference clock input terminal is used to provide a valid clock signal i_refclk to the GPU.

[0042] In some embodiments, the multiple input terminals of the above-mentioned OR operation unit 110a can be connected to pull-down resistors respectively. The pull-down resistor is used to set the input signal of the connected input terminal to logic "0" when a valid clock signal is not received. In this way, even if the input terminal is not connected to the GPU, or the connected GPU does not output any signal, the OR operation unit 110a can operate normally. It can be understood that if the OR operation unit 110a is composed of one or more OR gates, then each input terminal of the OR gate needs to provide an input signal and cannot be floated, otherwise the accuracy of the output result may be affected by interference with the floating input terminal. Therefore, in the embodiment of the present disclosure, each input terminal is set to logic "0" through a pull-down resistor, that is, when there is no signal input, the input terminal defaults to input logic "0". When a valid signal logic "1" or logic "0" is input, it will be input through the input terminal, and the pull-down resistor will be short-circuited.

[0043] Furthermore, in some embodiments, Figure 2 As shown, the second processing unit 120 includes: an AND operation unit 120a. The AND operation unit 120a also includes a plurality of input terminals, wherein at least some of the input terminals are respectively used to connect to the GPU and receive the first frame synchronization signal provided by the GPU. Exemplarily, the plurality of input terminals of the AND operation unit 120a are respectively connected to the synchronization signal output terminals of the plurality of GPUs; the output terminal of the AND operation unit 120a is connected to the synchronization signal input terminal of each GPU; wherein the synchronization signal output terminal is used to output the frame synchronization output signal o_fsync of the GPU; the synchronization signal input terminal is used to provide a valid synchronization signal i_fsync to the GPU; The GPU outputs frame data to be displayed based on the valid clock signal i_refclk and the valid synchronization signal i_fsync.

[0044] In some embodiments, the plurality of input terminals of the AND operation unit 120a can be connected to a pull-up resistor respectively; the pull-up resistor is used to set the input terminal that is not connected to the GPU to logic "1". In this way, even if the input terminal is not connected to the GPU, or the connected GPU does not output any signal, the AND operation unit 120a can operate normally. It can be understood that if the AND operation unit 120a is composed of one or more AND gates, then similar to the above-mentioned OR gate, each input terminal of the AND gate needs to provide an input signal and cannot be floated, otherwise the floating input terminal may be disturbed and affect the accuracy of the output result. Therefore, in the embodiment of the present disclosure, each input terminal is set to logic "1" through a pull-up resistor, that is, when there is no signal input, the input terminal defaults to input logic "1". When there is a logic "1" or logic "0" input by the GPU, it will be input to the AND operation unit 120a through the input terminal, and the pull-up resistor will be short-circuited.

[0045] Regarding the above Figure 2 In the case shown, the OR operation unit performs an OR logic operation on the input signals received by the multiple input terminals and provides an output signal. If at least one of the input signals of the multiple input terminals is a logic "1", that is, a high level, then the output is a logic "1", that is, a high level; if the input signals of the multiple input terminals are all logic "0", that is, a low level, then the output is a logic "0", that is, a low level.

[0046] It should be noted that, in the disclosed embodiment, the reference clock input of the GPU is used to receive a valid clock signal i_refclk, which is the reference clock signal used by the GPU. When the GPU performs image processing, it can output image data according to the clock transition edge with the valid clock signal i_refclk, and provide it to the corresponding display device. Therefore, in order to synchronize the clocks of multiple GPUs, it is necessary to provide a synchronized valid clock signal i_refclk to the reference clock inputs of the multiple GPUs. Each GPU itself can output the internal clock signal, so a GPU can be selected as the main card to provide the reference clock signal.

[0047] In the embodiment of the present disclosure, the multiple input terminals of the OR operation unit 110a are used to receive the reference clock signals provided by the reference clock output terminals of the multiple GPUs. In order to synchronize the clocks of the multiple GPUs, one of the GPUs is selected as the main card, and its output reference clock output signal is provided to the OR operation unit 110a as one of the input signals, and the other GPUs are used as slave cards, and the reference clock output terminals of the slave cards can output low-level signals, that is, logic "0" or no signal.

[0048] In this way, the output end of the OR operation unit 110a can output the reference clock output signal o_refclk output by the reference clock output end of the main card as a reference clock signal, and connect the reference clock input ends of multiple GPUs to the output end of the OR operation unit 110a to synchronously receive the reference clock signal, that is, the above-mentioned effective clock signal i_refclk. In this way, the clock synchronization of multiple GPUs can be achieved through a simple OR operation unit.

[0049] It is understandable that in order for the OR operation unit 110a to output the reference clock signal normally, only one of its multiple inputs is a clock signal, otherwise it will cause abnormal output. In some embodiments, the multiple input terminals of the OR operation unit 110a may include a reference clock input terminal connected to an external input in addition to the multiple input terminals connected to the reference clock output terminals of the above-mentioned multiple GPUs. If there is a main card in the above-mentioned multiple GPUs for providing the above-mentioned reference clock output signal o_refclk, the reference clock input terminal of the external input can be disconnected from the card, without any input signal, or can be grounded or connected to a low-level input signal. If there is no main card for providing the reference clock output signal o_refclk in the above-mentioned multiple GPUs, the reference clock output signal o_refclk can be provided through the reference clock input terminal of the external input.

[0050] It can be understood that the reference clock input terminal can be used to connect to the reference clock output terminal of other GPUs, and can also be used to connect to a clock signal generator dedicated to outputting clock signals, and can also be used to connect to the output terminal of the OR operation unit 110a of other synchronization devices to achieve the expansion of the synchronization device.

[0051] The AND operation unit 120a is a module that performs an AND logic operation on the input signals received from multiple input terminals and provides an output signal. If at least one of the input signals from the multiple input terminals is a logic "0" or a low level, then the output is a logic "0" or a low level. Only when all the input signals are a logic "1" or a high level, then the output is a logic "1" or a high level.

[0052] Since the GPU needs a certain amount of preparation time to process the data of each frame, when the data of a frame is ready and stored in the cache, it means that the signal can be output to the display end for display. The above-mentioned synchronization signal output end of the GPU is used to output the frame synchronization output signal o_fsync. Therefore, after each frame is processed and cached, the synchronization signal output end can be set to "1", that is, a high-level frame synchronization output signal o_fsync is output, indicating that the GPU has completed the data preparation of the current frame.

[0053] When the frame synchronization output signals o_fsync received by the multiple input terminals of the AND operation unit 120a of the synchronization device 100 are all high-level logic "1", it means that all GPUs have completed the data preparation of the current frame. At this time, if the synchronization of the above-mentioned effective clock signal i_refclk has been completed, each GPU can be instructed to output frame data to complete the display of the current frame.

[0054] Since the output end of the AND operation unit 120a is respectively connected to the synchronization signal input ends of multiple GPUs, the AND operation result can be provided to each GPU as a frame synchronization indication signal. When the GPU receives the valid synchronization signal i_fsync of the high level, i.e., logic "1", it means that the multiple GPUs have completed the preparation of frame data, and thus can output the frame data for display by the display end.

[0055] It should be noted that the above clock synchronization can be implemented when the device is powered on or in the initialization process of preparing to start video display. When multiple GPUs complete the synchronization of the reference clock (that is, the reference clock input end of each GPU receives a valid clock signal i_refclk), the multiple GPUs complete the clock synchronization. After that, the clock synchronization can be maintained unchanged to ensure the clock synchronization of the subsequent frames. The synchronization of the above frame data is implemented after each GPU completes the data preparation of each frame, that is, frame synchronization is required for each frame displayed. After receiving the valid synchronization signal i_fsync input from the synchronization signal input end, the GPU outputs the current frame data, and then the output signal of the synchronization signal output end can be cleared, that is, the frame synchronization output signal o_fsync is set to "0", until the data of the next frame is prepared, the frame synchronization output signal o_fsync is set to "1" again. In this way, under the premise of clock synchronization, the frame synchronization of each frame can be completed in sequence, and each frame can be output in sequence to complete the display of the spliced ​​picture.

[0056] In this way, by using the above-mentioned synchronization device 100, the clock synchronization and frame synchronization operations of multiple GPUs can be realized by simply connecting multiple GPUs. In addition, there is no need for communication between each GPU, so there is no need to set up an additional synchronization signal channel, nor is there a need to configure a dedicated display device. The display end can be a plurality of different display units, and each display unit can be connected to a plurality of GPUs and controlled separately. There is no need to consider the synchronization separately for each GPU and the display unit. The synchronization device 100 has completed the clock synchronization and frame synchronization of multiple GPUs, and the display end can display according to the received data and clock signal. Therefore, the above-mentioned synchronization device is more versatile and can be widely used in various scenarios such as various video walls, multi-screen displays, screen segmentation, etc. It is low-cost and easy to expand.

[0057] In other embodiments, the first processing unit 110 and the second processing unit 120 may also be other types of logic operation units capable of implementing similar functions. For example, the first processing unit 110 may also be a signal selection unit, for example, the signal selection unit may be composed of one or more signal selectors. At least part of the multiple input ends of the signal selection unit are respectively used to connect to the GPU. The signal selection unit selects a valid clock signal from the received multiple signals as an output signal.

[0058] Exemplarily, the signal selection unit may further include a signal selection terminal, which may be used to receive a preset selection signal, and the selection signal is used to indicate which input signal the signal selection unit selects as the output signal. For example, when the first input terminal is configured to receive a valid clock signal, the selection signal may be configured as a signal corresponding to the first input terminal, so that the signal selection unit may output the signal of the first input terminal. When the second input terminal is modified to receive a valid clock signal, the selection signal may be configured as a signal corresponding to the second input terminal, thereby switching the output signal to the input signal of the second input terminal.

[0059] For another example, the second processing unit 120 can also be a counting unit, which can be composed of one or more counters. The counting unit can count the valid synchronization signals in the received input signal. When the count value is consistent with the number of the received first frame synchronization signals, it indicates that the received first frame synchronization signals are all valid synchronization signals, so that the second frame synchronization signal can be output to indicate that each GPU is in a frame synchronization state. For example, the synchronization device 100 is connected to 3 GPUs, and each GPU outputs a first frame synchronization signal to the counting unit respectively. When the first frame synchronization signal is invalid, it is a low level, and when it is valid, it is a high level. Therefore, the counting unit can count the received high level. When the count value is 3, the second frame synchronization signal is output. For another example, the synchronization device 100 has a total of 4 GPU interfaces, 3 of which are respectively connected to a GPU, and the input end of the counting unit that is not connected to the GPU is set to logic "1" (such as inputting a high level through a pull-up resistor). In this way, the counting unit counts the high level received at each input end, and when the count value is consistent with the total number of GPU interfaces (the count value is 4), the second synchronization signal is output.

[0060] In some embodiments, the synchronization device 100 also includes: a cascade input terminal and a cascade output terminal; the cascade input terminal is connected to the cascade output terminal of another cascaded synchronization device; the cascade output terminal and the cascade input terminal are used to transmit the valid clock signal and / or the valid synchronization signal between the cascaded multiple synchronization devices.

[0061] It is understandable that the synchronization device 100 is implemented by the first processing unit 110 to achieve clock synchronization, and the second processing unit 120 to achieve frame synchronization. Both of these logic units can be implemented by one or more logic gates. Therefore, input ends with different data amounts can be implemented by setting logic gates, and the cascading of multiple synchronization devices can be achieved by cascading the input and output ends of the logic units. In this way, multiple expansion can be achieved through cascading, which is convenient for flexibly setting the number of GPUs.

[0062] In some embodiments, Figure 3 As shown, the cascade input terminal includes: a clock cascade input terminal 210; the cascade output terminal includes: a clock cascade output terminal 220; The clock cascade input terminal 210 is connected to the input terminal of the first processing unit 110 and is used to connect to the clock cascade output terminal 220 of another cascade synchronization device 100; The clock cascade output terminal 220 is connected to the output terminal of the first processing unit 110 .

[0063] In the embodiment of the present disclosure, each synchronization device 100 can be connected to N (N>1, for example, N=4 or N=6, etc.) GPUs. That is, the input ends of the first processing unit 110 and the operation unit 120 in each synchronization device 100 include at least N. In the embodiment of the present disclosure, each synchronization device 100 can also be used to cascade other synchronization devices 100. Specifically, the input ends of the above-mentioned first processing unit 110 can be N+1, wherein the N input ends are respectively used to connect different GPUs, and another input end can be used as the above-mentioned clock cascade input end 210, cascaded with other synchronization devices 100, that is, connected to the output end of the first processing unit 110 of another synchronization device 100. The output end of the first processing unit 110 is divided into multiple N+1 branches, wherein the N branches are respectively connected to the reference clock input ends of multiple GPUs, and another branch is used as the above-mentioned clock cascade output end 220 to be connected to the clock cascade input end 210 of another synchronization device 100. In this way, the synchronization of the reference clocks of multiple synchronization devices 100 can be achieved.

[0064] In some embodiments, when the clock cascade input terminal 210 is not connected to the clock cascade output terminal 220 of the other synchronization device 100, the clock cascade input terminal 210 is floating; and / or When the clock cascade output terminal 220 is floating and is not connected to the clock cascade input terminal 210 of the other synchronization device 100 , the clock cascade output terminal 220 is floating.

[0065] In addition, in some other embodiments, since the above-mentioned clock cascade input terminal 210 is the input terminal of the first processing unit 110, when no other synchronization devices are cascaded, the clock cascade input terminal 210 can be grounded or connected to a low level to provide a logic "0", so that the output signal of the first processing unit 110 is not affected by this terminal.

[0066] In some embodiments, Figure 4 As shown, the cascade input terminal includes: a first synchronous input terminal 310; the cascade output terminal includes: a first synchronous output terminal 320; The first synchronization input terminal 310 is connected to the input terminal of the second processing unit 120 and is used to connect to the first synchronization output terminal 320 of another cascaded synchronization device 100; The first synchronous output terminal 320 is connected to an output terminal of the second processing unit 120 .

[0067] In some embodiments, the cascade input terminal further includes: a second synchronization input terminal 330, and the cascade output terminal further includes: a second synchronization output terminal 340; The second synchronization input terminal 330 and the second synchronization output terminal 340 are both connected to the synchronization signal input terminals of the multiple GPUs, and the second synchronization input terminal 330 is used to connect to the second synchronization output terminal 340 of another cascaded synchronization device 100, or to connect to the first synchronization output terminal 320 of the synchronization device 100.

[0068] In the embodiment of the present disclosure, synchronization of the frame synchronization output signals o_fsync of a plurality of cascaded synchronization devices 100 is achieved through two groups of input and output terminals.

[0069] As mentioned above Figure 4 As shown, in the case of cascading multiple synchronization devices, each synchronization device needs to be connected to the frame signal synchronization of all GPUs. Therefore, in the logical operation, the frame synchronization output signal o_fsync of all GPUs needs to be ANDed. The connection relationship between the second processing units 120 of two adjacent synchronization devices 100 is: the output end of the second processing unit 120 of the upper level is connected to the input end of the second processing unit 120 of the next level, so as to realize the cascading of multiple second processing units 120. In this way, the output signal of the second processing unit 120 of the last level synchronization device 100 is the final frame synchronization signal, and is used to provide to the synchronization signal input end of all GPUs.

[0070] Therefore, for a synchronization device 100, the synchronization signal input terminals of multiple GPUs are connected together, and the second synchronization input terminal 330 and the second synchronization output terminal 340 are connected respectively. In addition to the synchronization signal output terminals of multiple GPUs of the same level, the multiple input terminals of the AND operation unit also have an additional input terminal as the first synchronization input terminal 310; the output terminal of the second processing unit 120 is used as the first synchronization output terminal 320. When other synchronization devices 100 are cascaded, the first synchronization output terminal 320 of the upper synchronization device 100 is connected to the first synchronization input terminal 310 of the lower synchronization device 100. When there is no cascaded synchronization device 100 of the next level, the first synchronization output terminal 320 is connected to the second synchronization input terminal 330 of the current level, that is, the output terminal of the second processing unit 120 is connected to the synchronization signal input terminals of each GPU. The second synchronization output terminal 340 of the synchronization device 100 of the current level is used to connect to the second synchronization input terminal 330 of the synchronization device 100 of the previous level. In this way, the second processing units 120 of multiple cascaded synchronization devices can be cascaded so that the frame synchronization output signals o_fsync of all GPUs participate in the AND operation, and the final AND operation result is provided to each GPU as a valid synchronization signal i_fsync to indicate frame synchronization.

[0071] For the specific connection method of the above-mentioned cascaded multiple synchronization devices 100, please refer to Figure 5 , Figure 5 The cascade connection of three synchronization devices 100 is shown, and the specific description is as follows: In some embodiments, Figure 5 Taking the first synchronization device 100 (1) in the example, when no other synchronization device is cascaded on the first side of the synchronization device 100 and another synchronization device is cascaded on the second side: The first synchronization input terminal 310 and the second synchronization output terminal 340 are both floating; The first synchronization output terminal 320 is connected to the first synchronization input terminal 310 of the other synchronization device 100 (2); The second synchronization input terminal 330 is connected to the second synchronization output terminal 340 of the further synchronization device 100 ( 2 ).

[0072] In some embodiments, Figure 5 For example, the second synchronization device 100 (2) in FIG. 1 is connected in cascade with a first synchronization device (such as Figure 5 The synchronization device 100 (1) shown in FIG. 1 ) is cascaded with a second synchronization device (such as Figure 5 In the case of the synchronization device 100 (3) shown: The first synchronization input terminal 310 is connected to the first synchronization output terminal 320 of the first synchronization device 100 (1); The second synchronization output terminal 340 is connected to the second synchronization input terminal 330 of the first synchronization device 100 (1); The first synchronization output terminal 320 is connected to the first synchronization input terminal 310 of the second synchronization device 100 (3); The second synchronization input terminal 330 is connected to the second synchronization output terminal 340 of the second synchronization device 100 ( 3 ).

[0073] The first synchronization device 100 ( 1 ) and the second synchronization device 100 ( 3 ) may be the same synchronization device 100 as the synchronization device 100 ( 2 ).

[0074] In some embodiments, Figure 5 For example, the synchronization device 100 (3) in FIG. 1 is connected in cascade to another synchronization device (such as Figure 5 In the case of the synchronization device 100 (2) shown in the figure), and no other synchronization devices are cascaded on the second side: The first synchronization input terminal 310 is connected to the first synchronization output terminal 320 of the other synchronization device 100 (2); The second synchronization output terminal 340 is connected to the second synchronization input terminal 330 of the other synchronization device 100 (2); The first synchronization output terminal 320 is connected to the second synchronization input terminal 330 .

[0075] also, Figure 5 It is also shown in FIG. 1 that the clock cascade input terminal 210 of each synchronization device 100 is sequentially connected to the clock cascade output terminal 220 of the adjacent stage, thereby realizing the cascade of the effective clock signal i_refclk.

[0076] In summary, when multiple synchronization devices 100 are cascaded, the first synchronization input terminal 310 of the first-stage synchronization device 100 (1) does not have other cascaded terminals, so it can be floated or set to "1" (providing a high level); the first synchronization output terminal 320 is connected to the first synchronization input terminal 310 of the next-stage synchronization device 100 (2); and the second synchronization input terminal 330 is connected to the second synchronization output terminal 340 of the next-stage synchronization device 100 (2).

[0077] As the intermediate-level synchronization device 100 (2), its first synchronization input terminal 310 is connected to the first synchronization output terminal 320 of the previous-level synchronization device 100 (1), its first synchronization output terminal 320 is connected to the first synchronization input terminal 310 of the next-level synchronization device 100 (3), its second synchronization input terminal 330 is connected to the second synchronization output terminal 340 of the next-level synchronization device 100 (3), and its second synchronization output terminal 340 is connected to the second synchronization input terminal 330 of the previous-level synchronization device 100 (1). It can be understood that if there are more levels of synchronization devices 100 connected to each other, the synchronization devices 100 at the intermediate levels are connected in the same manner as the above-mentioned synchronization device 100 (2).

[0078] The last-stage synchronization device 100 (3) connects its own first synchronization output terminal 320 and second synchronization input terminal 330 together, thereby providing the output signal of the AND operation unit 120 to the synchronization signal input terminal of each GPU, and further transmits it to the synchronization signal input terminal of each GPU of the other cascaded synchronization devices 100 through the second synchronization output terminal 340. Therefore, the input signal of the synchronization signal input terminals of all synchronized GPUs is the above-mentioned effective synchronization signal i_fsync.

[0079] In some embodiments, Figure 6 As shown, when the synchronization device 100 is not cascaded with other synchronization devices: The first synchronization input terminal 310 and the second synchronization output terminal 340 are both floating; The first synchronization output terminal 320 is connected to the second synchronization input terminal 330 .

[0080] In this way, the output end of the second processing unit 120 of the synchronization device 100 is connected to the synchronization signal input ends of the multiple GPUs, so that the frame synchronization output signals o_fsync of the multiple GPUs are provided to each GPU as a valid synchronization signal i_fsync after AND operation. The first synchronization input end 310 and the second synchronization output end 340 do not require additional signals and can be floated. In another embodiment, since the first synchronization input end 310 is the input end of the second processing unit 120, it can also be set to "1", for example, connected to the power supply end to provide a high level as an input signal.

[0081] It is understandable that, in the case where other synchronization devices are not cascaded, the input and output of the first processing unit 110 are also limited to the synchronization device itself, so the clock cascade input terminal 210 and the clock cascade output terminal 220 can be floating. In another embodiment, since the clock cascade input terminal 210 is an input terminal of the first processing unit 110, in the case where it is not cascaded, the input terminal can also be set to logic "0" by grounding or connecting to a low-level power supply terminal.

[0082] In some embodiments, as described above Figure 4 As shown, the synchronization device 100 further includes: One or more synchronization indicating units 350; the synchronization indicating unit 350 is connected to the synchronization state output terminal of the GPU; the synchronization state output terminal is used for the GPU to indicate that the GPU is in a clock synchronization state based on the received valid clock signal i_refclk.

[0083] When the GPU receives a valid clock signal i_refclk, or receives a valid clock signal i_refclk and processes it through internal logic to determine that the GPU has completed clock synchronization, it can output a clock synchronization state signal o_sync_st through the above-mentioned synchronization state output terminal. This signal can be provided to the above-mentioned synchronization indication unit 350, thereby indicating that the GPU has achieved clock synchronization and can work normally to process frame data of subsequent images.

[0084] Exemplarily, the synchronization indication unit 350 may be an indicator light, so that the user can monitor the synchronization status of the GPU during testing or use. In addition, the synchronization indication unit 350 may also be a status signal output terminal, which is used to output the clock synchronization status signal o_sync_st of each GPU to other devices, such as test equipment, display equipment or other control equipment, so as to notify the other party that the GPU has completed clock synchronization and can perform subsequent frame data processing.

[0085] The present disclosure also provides the following examples: Figure 7 The logical architecture of splicing image processing using the synchronization device provided by the embodiment of the present disclosure and four graphics cards (GPUs) is shown. Here, a complete image is cut into four equal strip areas (Strip1 to Strip4). For example, the picture is divided into four horizontally extending strip areas along the vertical direction of the image. Each Strip is further divided into four block areas of the same size (Block1-1 to Block4-4). For example, the size of each Block is up to 16K, and the entire picture has a total of 16 Blocks. These 16 Blocks can be provided to 16 display units for multi-screen display, and the 16 display units can be spliced ​​together to display the complete picture. If each GPU supports 4-way display, 4 graphics cards are required to output 16 Blocks. In order to ensure that it can be spliced ​​into a complete picture on the real end, it is necessary to synchronize the outputs of multiple graphics cards without requiring additional configuration of the display end to ensure the synchronous display of multiple display units.

[0086] like Figure 7As shown, four graphics cards (GPU0 to GPU3) are connected to a synchronization device 100. Each graphics card communicates with the synchronization device 100 through five signals. The five signals include: o_refclk: synchronization reference output clock, the output of the master card in each group of graphics cards is used for clock synchronization of each display port of the board; i_refclk: synchronization reference input clock, each graphics card in the system uses this clock as a reference clock for synchronous output; o_fsync: frame synchronization output signal, used for synchronization of the frame buffer (FrameBuff) of each graphics card in the multi-card system, ensuring that the frame buffer data of the display engines of all graphics cards are ready; i_fsync: valid synchronization signal, used to notify that the frame buffer of all display engines in the multi-card system is ready and can be output for display; o_sync_st: synchronization status output signal, when the reference clock on the graphics card is synchronized, the signal is set high, thereby controlling the indicator light connected to the synchronization device to light up, to indicate that the corresponding graphics card is in a clock synchronization state.

[0087] The logic of the synchronization device 100 is relatively simple, and is composed of input and output signals and signal processing digital logic. The definition of the signal connected to the graphics card synchronization interface is the same. In addition, two sets of input and output signals are provided to realize the cascading of the synchronization device 100, thereby realizing more expansion. Among them, o_ext_i_fsync: the input frame synchronization signal of the external output (that is, the signal output by the second synchronization output terminal involved in the above embodiment) is connected to the i_ext_i_fsync of the previous level (that is, the second synchronization input terminal involved in the above embodiment); i_ext_o_fsync: the input frame synchronization signal of the external input (that is, the input signal of the first synchronization input terminal involved in the above embodiment) is connected to the o_ext_o_fsync of the previous level (that is, the first synchronization output terminal involved in the above embodiment); i_ext_o_refclk: the output synchronization reference of the external input The clock (i.e., the input clock signal of the clock cascade input terminal in the above embodiment) is connected to the o_ext_o_refclk (i.e., the clock cascade output terminal in the above embodiment) of the synchronization device at the previous level; i_ext_i_fsync: the input synchronization frame signal of the external input (i.e., the input signal of the second synchronization input terminal in the above embodiment); o_ext_o_fsync: the frame synchronization signal of the external output (i.e., the input signal of the first synchronization output terminal in the above embodiment); o_ext_o_refclk: the output synchronization reference clock of the external output (i.e., the output signal of the clock cascade output terminal in the above embodiment). There are two signal digital processing logics. Logic01 is an OR operation unit, which realizes that any graphics card is used as the main card, and provides o_refclk output to each secondary card and the i_refclk port of the main card itself. Logic02 is an AND operation unit, which outputs a valid signal only when each input signal is valid (high level, logic "1").

[0088] The configuration logic of the synchronization device 100 provided in the embodiment of the present disclosure for connecting each GPU can be referred to Figure 8 . Specifically, Figure 8 This is the process of configuring multi-card synchronization. In a system, there is only one graphics card as the main card, and the other graphics cards are slave cards. The slave cards receive the reference clock signal sent by the main card to achieve clock synchronization. The specific steps are as follows: 1. Configure the secondary card Step S701, initializing the display system; Step S702, configuring the currently configured graphics card to secondary card mode; Step S703, select external i_refclk as the reference clock; Step S704: After the clock is stably synchronized, an o_sync_st signal may be output to light up the indicator light of the synchronization device (ie, the synchronization indicating unit involved in the above embodiment); Step S705: If there is an image to be output, after the frame buffer is ready, an o_fsync signal is output to inform other graphics cards that the data is ready; Step S706, detect the i_fsync signal. If the data of all graphics cards are ready, the signal is valid. The display engine of the current graphics card fetches data from the frame buffer and sends it to the display end, then clears the o_fsync signal to synchronously prepare the data of the next frame.

[0089] Thereafter, the above steps S705 and S706 are looped to realize synchronous display of the video or multiple pictures.

[0090] 2. Configure the primary card Step S711, initializing the display system; Step S712, configuring the current graphics card to be in master card mode; Step S713, outputting a synchronous reference clock to the o_refclk pin; Step S714, select the external i_refclk as the reference clock; at this time, the synchronous reference input clock i_refclk signal actually comes from the synchronous reference output clock o_refclk signal output by the graphics card itself; Step S715: After the clock is stabilized and synchronized, an o_sync_st signal may be output to light up the indicator light of the synchronization device; Step S716: If there is a picture to be output, after the frame buffer is ready, an o_fsync signal is output to inform other secondary cards that the data is ready; Step S717, detect the i_fsync signal. If the data of all graphics cards are ready, the signal is valid, the display engine frame buffer of the main card fetches data and sends it to the display end, and then clears the o_fsync signal to synchronously prepare the data of the next frame.

[0091] Then, the above steps S716 and S717 are looped to realize synchronous display of video or multiple pictures.

[0092] It should be noted that in the above configuration process, the secondary cards may be configured first, and the above steps S701 to S703 may be executed for each secondary card to realize initialization, and then the main card may be configured, and the above steps 711 to S713 may be executed for the main card to complete initialization.

[0093] Afterwards, each graphics card can execute the subsequent steps simultaneously and synchronously enter the subsequent step loop of steps S705 / S706 and steps S716 / S717.

[0094] Fig. 9 A schematic diagram of the structure of the synchronization device provided in the embodiment of the present disclosure applied to the display system. Here, a single synchronization device supports 4-way connection (4-way signals of a single card are automatically synchronized internally), and each channel supports 4-way output as an example. The image to be displayed is cut into 16 sub-images of the same size, and displayed on 16 display units (each display unit can be an independent display screen or an area on a display screen), the display interface (DE0 to DE3) of the graphics card (GPU0 to GPU3) is connected to the display, and the synchronization interface (SYNC) is connected to the synchronization device 100. According to the specific implementation, the synchronization device 100 supports direct power supply from the motherboard PCIE (Peripheral Component Interconnect Express) or provides a separate interface for power access.

[0095] The synchronization device provided in the embodiment of the present disclosure is simple to implement, does not occupy too many logic units of the graphics card, does not increase too much tape-out cost, is simple to deploy, does not require additional dedicated equipment, can reduce costs, and can enrich the characteristics of the graphics card and enhance product competitiveness.

[0096] Based on the same inventive concept, the present disclosure also provides an image processing system. Fig.10 As shown, the image processing system 900 includes: One or more synchronization devices 100 of any of the above; There are multiple GPUs, and each of the synchronization devices 100 is connected to one or more of the GPUs (such as GPU0 to GPU3 as shown in the figure).

[0097] In some embodiments, the image processing system 900 further includes: A display module 910 connected to the multiple GPUs; The GPU outputs frame data to be displayed to the display module based on the valid clock signal and the valid synchronization signal output by the synchronization device 100; The display module 910 displays a spliced ​​picture based on the frame data output by the multiple GPUs.

[0098] It should be pointed out here that the description of each embodiment above tends to emphasize the differences between the embodiments, and the same or similar aspects can be referenced to each other. The description of the embodiment of the above image processing system is similar to the description of each embodiment corresponding to the above synchronization device, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the image processing system embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0099] The GPU involved in the embodiments of the present disclosure may be an architecture independent of other processors such as a CPU, and may also be referred to as a "graphics card". Fig.11 FIG. 1 is a schematic diagram of the composition structure of a GPU involved in the embodiments of the present disclosure. Fig.11 As shown, the hardware entity of the GUP 800 includes: a GPU chip 801, a video memory 802, and an interface unit 803; The GPU chip 801 is a core component of the GPU 800, and is used to perform graphics rendering tasks, including vertex processing, rasterization, and pixel shading, for example; The video memory 802 is a GPU-specific storage medium, which can be a memory used to store graphic data, such as texture information, vertex information, etc. The types of video memory can include double data rate video memory (Graphics Double Data Rate, GDDR) series and high bandwidth memory (High Bandwidth Memory, HBM), etc. The interface unit 803 is used to connect the display of the electronic device or the interface of other display devices, such as High Definition Multimedia Interface (HDMI), DisplayPort, Digital Visual Interface (DVI), Video Graphics Array (VGA), etc.

[0100] In addition, in some embodiments, the GPU may also include a heat dissipation system, a power interface, and a bus and interface with other systems in the electronic device (such as a CPU and a storage system, etc.). In addition, in some embodiments, the GPU may also include specific hardware accelerators, such as a tensor core for artificial intelligence and deep learning, or a ray tracing core (RT) for real-time ray tracing.

[0101] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution. The execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0102] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0103] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0104] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0105] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0106] The above description is only an implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A synchronization device for a graphics processing unit GPU, characterized in that: The synchronization device comprises: A first processing unit, configured to receive a preset valid clock signal and output the valid clock signal to at least one GPU; A second processing unit is configured to receive a first frame synchronization signal of the at least one GPU, and output a second frame synchronization signal to the at least one GPU; wherein the second frame synchronization signal is a valid synchronization signal when the first frame synchronization signals all indicate that the GPU is in a frame synchronization state; and the valid synchronization signal is used to indicate that the at least one GPU is in a frame synchronization state; The GPU outputs frame data to be displayed based on the valid clock signal in a state where the second frame synchronization signal is the valid synchronization signal.

2. The synchronization device according to claim 1, characterized in that: The first processing unit comprises: An OR operation unit, comprising a plurality of input terminals, and configured to perform an OR operation on signals received by the plurality of input terminals; At least part of the multiple input terminals of the OR operation unit are respectively used to connect to the GPU; Wherein, any of the GPUs inputs the valid clock signal to the OR operation unit, or a preset external input inputs the valid clock signal to the OR operation unit through the input terminal; The output end of the OR operation unit is connected to the at least one GPU, and is used to provide the effective clock signal to the at least one GPU.

3. The synchronization device according to claim 2, characterized in that: The multiple input terminals of the OR operation unit are respectively connected to pull-down resistors; the pull-down resistors are used to set the input signals of the input terminals to logic 0 when the valid clock signal is not received.

4. The synchronization device according to claim 1, characterized in that: The first processing unit comprises: A signal selection unit, comprising a plurality of input terminals, for selecting a valid clock signal from the signals received by the plurality of input terminals as an output signal; At least part of the plurality of input terminals of the signal selection unit are respectively used to connect to the GPU; Wherein, any of the GPUs inputs the valid clock signal to the signal selection unit, or a preset external input inputs the valid clock signal to the signal selection unit through the input terminal; The output end of the signal selection unit is connected to the at least one GPU, and is used to provide the effective clock signal to the at least one GPU.

5. The synchronization device according to claim 1, characterized in that: The second processing unit comprises: AND unit; The AND operation unit includes a plurality of input terminals; at least part of the plurality of input terminals of the AND operation unit are respectively used to connect to the GPU and receive the first frame synchronization signal provided by the GPU; Among them, the first frame synchronization signal of high level is the valid synchronization signal.

6. The synchronization device according to claim 5, characterized in that: The plurality of input terminals of the AND operation unit are respectively connected to pull-up resistors; the pull-up resistors are used to set the input terminals not connected to the GPU to logic 1.

7. The synchronization device according to claim 1, characterized in that: The second processing unit comprises: Counting unit; The counting unit comprises a plurality of input terminals; at least part of the plurality of input terminals of the counting unit are respectively used to connect to the GPU and receive the first frame synchronization signal provided by the GPU; The counting unit is used for counting valid synchronization signals in the received first frame synchronization signal, and outputting the second frame synchronization signal to the at least one GPU when the count value is consistent with the number of the received first frame synchronization signals.

8. The synchronization device according to any one of claims 1 to 7, characterized in that: The synchronization device includes N GPU interfaces; the GPU interfaces include at least N first connection ends connected to the first processing unit and N second connection ends connected to the second processing unit; wherein N is an integer greater than or equal to 2; The synchronization device is connected to the M GPUs through the GPU interface, and is used to provide the effective clock signal to the M GPUs through the first processing unit, and provide the second frame synchronization signal to the M GPUs through the second processing unit; Wherein, M is a positive integer less than or equal to N.

9. The synchronization device according to any one of claims 1 to 7, characterized in that: The synchronization device also includes: A cascade input terminal and a cascade output terminal; The cascade input terminal is connected to the cascade output terminal of another synchronization device in the cascade; The cascade output terminal and the cascade input terminal are used to transmit the valid clock signal and / or the valid synchronization signal between the plurality of cascaded synchronization devices.

10. The synchronization device according to claim 9, characterized in that: The cascade input terminal includes: a clock cascade input terminal; the cascade output terminal includes: a clock cascade output terminal; The clock cascade input terminal is connected to the input terminal of the first processing unit and is used to connect to the clock cascade output terminal of another synchronization device in the cascade; The clock cascade output terminal is connected to the output terminal of the first processing unit.

11. The synchronization device according to claim 10, characterized in that: When the clock cascade input terminal is not connected to the clock cascade output terminal of the other synchronization device, the clock cascade input terminal is floating; and / or When the clock cascade output terminal is floating and is not connected to the clock cascade input terminal of another synchronization device, the clock cascade output terminal is floating.

12. The synchronization device according to claim 9, characterized in that: The cascade input terminal includes: a first synchronization input terminal; the cascade output terminal includes: a first synchronization output terminal; The first synchronization input terminal is connected to the input terminal of the second processing unit and is used to connect to the first synchronization output terminal of another cascaded synchronization device; The first synchronous output terminal is connected to the output terminal of the second processing unit.

13. The synchronization device according to claim 12, characterized in that: The cascade input terminal further includes: a second synchronization input terminal, and the cascade output terminal further includes: a second synchronization output terminal; The second synchronization input terminal and the second synchronization output terminal are both connected to the at least one GPU for transmitting the valid synchronization signal, and the second synchronization input terminal is used to connect to the second synchronization output terminal of another cascaded synchronization device, or to connect to the first synchronization output terminal of the synchronization device.

14. The synchronization device according to claim 13, characterized in that: In the case where no other synchronization device is cascaded to the first side of the synchronization device, and another synchronization device is cascaded to the second side: The first synchronization input terminal and the second synchronization output terminal are both floating; The first synchronization output terminal is connected to the first synchronization input terminal of the other synchronization device; The second synchronization input terminal is connected to the second synchronization output terminal of the other synchronization device.

15. The synchronization device according to claim 13, characterized in that: In the case where a first synchronization device is cascaded with a first synchronization device on the first side and a second synchronization device is cascaded with a second synchronization device on the second side: The first synchronization input terminal is connected to the first synchronization output terminal of the first synchronization device; The second synchronization output terminal is connected to the second synchronization input terminal of the first synchronization device; The first synchronization output terminal is connected to the first synchronization input terminal of the second synchronization device; The second synchronization input terminal is connected to the second synchronization output terminal of the second synchronization device; The first synchronization device and the second synchronization device are the same as the synchronization device.

16. The synchronization device according to claim 13, characterized in that: In the case where another synchronization device is cascaded to the first side of the synchronization device, and no other synchronization device is cascaded to the second side: The first synchronization input terminal is connected to the first synchronization output terminal of the other synchronization device; The second synchronization output terminal is connected to the second synchronization input terminal of the other synchronization device; The first synchronization output terminal is connected to the second synchronization input terminal.

17. The synchronization device according to claim 13, characterized in that: In the case where the synchronization device is not cascaded with other synchronization devices: The first synchronization input terminal and the second synchronization output terminal are both floating; The first synchronization output terminal is connected to the second synchronization input terminal.

18. The synchronization device according to any one of claims 1 to 17, characterized in that: The synchronization device also includes: One or more synchronization indicating units; the synchronization indicating unit is used to receive a clock synchronization state signal sent by the GPU based on the valid clock signal, indicating that the GPU is in a clock synchronization state.

19. An image processing system, characterized in that: include: One or more cascaded synchronization devices as claimed in any one of claims 1 to 18; There are multiple GPUs, and each of the synchronization devices is connected to one or more of the GPUs.

20. The image processing system according to claim 19, characterized in that: Also includes: A display module connected to the multiple GPUs; The GPU outputs frame data to be displayed to the display module based on the valid clock signal and the valid synchronization signal output by the synchronization device; The display module displays a spliced ​​picture based on the frame data output by the multiple GPUs.

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