Level conversion circuit and electronic equipment

Abstract

The invention provides a level switching circuit and electronic equipment, and relates to the technical field of level switching. The level conversion circuit comprises an input port, a capacitor, a first level conversion module, a second level conversion module and an output port, the two ends of the capacitor are electrically connected with the input port and the output port respectively, and the input end of the first level conversion module is connected with the input port. The output end of the first level conversion module is electrically connected with the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected with the output port; when the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path. The first level conversion module is used for converting a first signal input by the input end into an opposite second signal, and the second level conversion module is used for converting the second signal into an opposite third signal. The circuit has the advantages of being small in signal delay and duty ratio loss.

Description

Technical Field

[0001] The present application relates to the technical field of level switching, and in particular to a level conversion circuit and an electronic device. Background Art

[0002] In the fifth generation DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) protocol memory interface chip, with the continuous increase in speed and the improvement of chip power consumption efficiency, the chip output power supply voltage has dropped to 1.1V. In order to pursue higher energy efficiency, a multi-voltage domain solution is usually adopted in the design of TX (Transmitter), that is, the output stage uses a 1.1V voltage domain, and the previous stage uses a lower voltage domain to reduce power consumption.

[0003] In the multi-voltage domain solution, the level switching between multiple voltage domains is completed by the level converter. As a bridge connecting different voltage domains, the level converter not only determines the quality of high-speed signal conversion, but also determines the final performance of the entire output end.

[0004] The integrity of the signal in the double data rate (DDR) high-speed link is crucial to the performance of the entire system. Therefore, the high-speed signal needs to ensure good signal quality after level conversion, that is, the signal conversion needs to be fast enough; the delay of the conversion process needs to be small enough; and the duty cycle loss of the signal during the conversion process also needs to be small enough. However, since the high-speed data signal has different voltage domains before and after the level converter after conversion, it is easy to cause the duty cycle of the signal to be lost during the level conversion process. In addition, the current level converter circuit generally stacks NMOS protection tubes and high-voltage PMOS tubes, which will cause a large delay in the entire level converter.

[0005] In summary, in the prior art, there are problems in which the level converter has a large delay and duty cycle loss during the level conversion process. Summary of the invention

[0006] The purpose of the present application is to provide a level conversion circuit and an electronic device to solve the problem of large delay and duty cycle loss of the level converter in the level conversion process in the prior art.

[0007] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: On the one hand, an embodiment of the present application provides a level conversion circuit, the level conversion circuit comprising an input port, a capacitor, a first level conversion module, a second level conversion module and an output port, the two ends of the capacitor are electrically connected to the input port and the output port respectively, the input end of the first level conversion module is connected to the input port, the output end of the first level conversion module is electrically connected to the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected to the output port; wherein, When the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path; and the first level conversion module is used to convert a first signal inputted from the input end into an opposite second signal, and the second level conversion module is used to convert the second signal into an opposite third signal; The first signal and the third signal have the same swing amplitude, the first signal is a signal located in a first voltage domain, the third signal is a signal located in a second voltage domain, and the power supply voltage and ground voltage of the second voltage domain are respectively greater than the power supply voltage and ground voltage of the first voltage domain.

[0008] Optionally, the first level conversion module includes a signal pull-down unit, a signal pull-up unit and a feedback loop unit, the signal pull-up unit and the signal pull-down unit are both connected to the input port, the signal pull-up unit and the feedback loop unit are both connected to a first node, the signal pull-down unit is also connected to a ground of the first voltage domain, and the signal pull-down unit, the feedback loop unit and the input end of the second level conversion module are all connected to a second node; wherein, When the first signal is a high level signal, the signal pull-down unit is turned on, and the signal pull-up unit is turned off; When the first signal is a low level signal, the signal pull-up unit is turned on, and the signal pull-down unit is turned off.

[0009] Optionally, the signal pull-down unit includes a first transistor and a second transistor, the feedback loop unit includes a third transistor and a fourth transistor, and the signal pull-up unit includes a fifth transistor; The gate of the first transistor is connected to the input port, the source of the first transistor is connected to the ground of the first voltage domain, the drain of the first transistor is electrically connected to the source of the second transistor, the gate of the second transistor is connected to the power supply of the first voltage domain, and the drain of the second transistor is connected to the second node; The gate of the third transistor and the drain of the fourth transistor are both connected to the first node, the drain of the third transistor and the gate of the fourth transistor are connected to the second node, and the source of the third transistor and the source of the fourth transistor are both connected to the power supply of the second voltage domain; A gate of the fifth transistor is connected to a power source of the first voltage domain, a source of the fifth transistor is connected to the input port, and a drain of the fifth transistor is connected to the first node.

[0010] Optionally, the first transistor, the second transistor and the fifth transistor are low-voltage NMOS transistors, and the third transistor and the fourth transistor are high-voltage PMOS transistors; wherein, The lowest withstand voltage of the high-voltage PMOS tube is greater than the highest withstand voltage of the low-voltage NMOS tube.

[0011] Optionally, a width-to-length ratio of the fifth transistor is greater than or equal to twice a width-to-length ratio of the fourth transistor; The width-to-length ratios of the first transistor and the second transistor are both greater than or equal to the width-to-length ratio of the third transistor.

[0012] Optionally, the level conversion circuit further includes a pull-up jump acceleration module, and the pull-up jump acceleration module is electrically connected to the output end of the capacitor and the input end of the second level conversion module respectively; wherein, The pull-up transition acceleration module is used to accelerate the transition speed of the high level when the first level conversion module outputs a high level.

[0013] Optionally, the pull-up jump acceleration module includes a sixth transistor and a seventh transistor, the drain of the sixth transistor is connected to the input end of the second level conversion module, the gate of the sixth transistor is connected to the ground of the second voltage domain, the source of the sixth transistor is electrically connected to the drain of the seventh transistor, the source of the seventh transistor is connected to the power supply of the second voltage domain, and the gate of the seventh transistor is connected to the output end of the capacitor.

[0014] Optionally, the sixth transistor and the seventh transistor are both low-voltage PMOS transistors.

[0015] Optionally, the second level conversion module includes an eighth transistor and a ninth transistor, the gate of the eighth transistor and the gate of the ninth transistor are both connected to the output end of the first level conversion module, the drain of the eighth transistor and the drain of the ninth transistor are both connected to the output port, the source of the eighth transistor is connected to the power supply of the second voltage domain, and the source of the ninth transistor is connected to the ground of the second voltage domain; wherein, When the second signal is a high level signal, the eighth transistor is turned off, the ninth transistor is turned on, and the third signal is a low level signal; When the second signal is a low level signal, the eighth transistor is turned on, the ninth transistor is turned off, and the third signal is a high level signal.

[0016] On the other hand, an embodiment of the present application further provides an electronic device, which includes the above-mentioned level conversion circuit.

[0017] Compared with the prior art, this application has the following beneficial effects: The present application provides a level conversion circuit and an electronic device, the level conversion circuit comprising an input port, a capacitor, a first level conversion module, a second level conversion module and an output port, the two ends of the capacitor are electrically connected to the input port and the output port respectively, the input end of the first level conversion module is connected to the input port, the output end of the first level conversion module is electrically connected to the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected to the output port; wherein, when the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path; and the first level conversion module is used to convert a first signal inputted at the input end into an opposite second signal, and the second level conversion module is used to convert the second signal into an opposite third signal; the first signal and the third signal have equal swing amplitudes, the first signal is a signal located in a first voltage domain, the third signal is a signal located in a second voltage domain, and the power supply voltage and the ground voltage of the second voltage domain are respectively greater than the power supply voltage and the ground voltage of the first voltage domain. Since the AC path formed by the capacitor is added to the level conversion circuit provided by the present application, when the signal frequency is not zero, the signal of the input port can be transmitted through the AC path and the DC path, and due to the inherent characteristics of the capacitive coupling, the level conversion of the signal can be greatly accelerated, and the delay of the entire level conversion circuit is reduced to the picosecond level, which greatly reduces the signal delay of the entire level conversion circuit. In addition, the DC path ensures the stability of the signal, thereby greatly reducing the signal delay while the entire level conversion circuit meets the stability requirements. In addition, since the capacitive coupling can synchronize the jump of the input signal, the duty cycle loss of the output signal is small, which can make the quality of the output signal higher.

[0018] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 The figure is a circuit diagram of a level converter in the prior art.

[0021] Figure 2 The diagram is a circuit diagram of another level converter in the prior art.

[0022] Figure 3 A circuit diagram of a level conversion circuit provided in an embodiment of the present application.

[0023] Figure 4 Another circuit diagram of the level conversion circuit provided in an embodiment of the present application.

[0024] In the figure: 110-input port; 120-capacitor; 130-first level conversion module; 131-signal pull-down unit; 132-signal pull-up unit; 133-feedback loop unit; 140-second level conversion module; 150-output port; 160-pull-up jump acceleration module; M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0027] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0028] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0029] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0030] As described in the background art, the level converter in the prior art has the problems of high signal delay and large duty cycle loss.

[0031] For example, see Figure 1 , Figure 1 A circuit diagram of a level converter in the prior art is shown. In the figure, there are two voltage domains in the whole circuit, and both voltage domains include VSS (Voltage Source Source, ground voltage) and VDD (Voltage Drain Drain, power supply voltage). Therefore, in the figure, one voltage domain is VSS1~VDD1, and the other voltage domain is VSS2~VDD2, and VSS2 is greater than VSS1, and VDD2 is greater than VDD1. For example, VSS1~VDD1 can be 0V~0.8V, and VSS2~VDD2 can be 0.3V~1.1V. Among them, M1, M2, M3, and M4 are differential input negative polarity metal oxide semiconductors (NMOS), and the signal input swing of M1 and M2 is VSS1~VDD1, and the signal output swing of the circuit is VSS2~VDD2.

[0032] It should be noted that the swing described in this application refers to the amplitude of the signal can be any value within the swing range. For example, if the input swing is VSS1~VDD1, then for the input signal, its minimum amplitude is VSS1 and its maximum is VDD1. Of course, the input signal can also be an amplitude between VSS1 and VDD1.

[0033] In order to increase the speed of signal processing by the level converter, M1 and M2 usually use low-voltage NMOS tubes, which have a low conduction threshold, so the delay of their signal processing will be lower than that of high-voltage tubes. Compared with high-voltage tubes, their conduction speed is faster and the delay can be smaller. However, the withstand voltage of low-voltage NMOS tubes is limited. Therefore, in order to protect the low-voltage tubes from overvoltage, M3 and M4 are used as protection tubes so that the drain voltage of M1 does not exceed the VDD1 voltage value. In addition, the gates of M3 and M4 are both connected to the power supply VDD1 of the first voltage domain, so that when M1 is turned on, M3 is also turned on synchronously; when M2 is turned on, M4 is also turned on synchronously.

[0034] M5 and M6 are high-voltage positive metal oxide semiconductors (PMOS). Since the drain of M6 is used as the output, its output voltage swing is VSS1~VDD2, so a high-voltage PMOS is required to ensure that the device does not overvoltage. INV1 (Inverter) is an inverter composed of low-voltage tubes, and INV2 and INV3 are inverters composed of high-voltage tubes.

[0035] The working principle of the entire level converter is: when the input signal is VSS1 voltage value, M1 is turned off, M2 is turned on, and the voltage value of the drain terminal of M6 begins to decrease; at the same time, M5 begins to gradually turn on, and the voltage value of its drain terminal gradually increases to VDD2. Due to the positive feedback, the voltage value of the drain of M5 will also accelerate the decrease of the voltage value of the drain terminal of M6 (the voltage of the drain terminal of M5 increases to a high level, and M6 is turned off, so that the voltage of the drain terminal of M6 drops rapidly), and finally the output voltage of the drain terminal of M6 is VSS1. After passing through the inverter INV2, the output voltage is converted to VDD2, and after passing through the inverter INV3, its output voltage value is VSS2, thus completing the voltage conversion from VSS1 to VSS2.

[0036] Similarly, when the input signal jumps from VSS1 to VDD1, M1 is turned on, M2 is turned off, and M6 is gradually turned on. Under the action of positive feedback, the drain terminal voltage of M5 is pulled down, and the drain voltage of M6 gradually increases to VDD2; after the action of inverter INV2 and inverter INV3, the voltage conversion from VDD1 to VDD2 is completed.

[0037] The input tube of this structure uses a low-voltage NMOS tube with a lower conduction threshold and faster conduction speed. However, due to the stacking of a first-level NMOS protection tube (M3 and M4) and a high-voltage PMOS tube (M5 and M6), the speed of the overall circuit is limited, resulting in a large delay, which makes it difficult to meet the delay requirements of the link. At the same time, due to the existence of a positive feedback loop in this circuit (the loop composed of M5 and M6), the pull-down capability of the input pair tube NMOS needs to be stronger than the pull-up capability of the PMOS in order to correctly distinguish the input signal. In this way, the duty cycle of the circuit output signal is naturally small, causing a large duty cycle loss.

[0038] See also Figure 2 , is a circuit diagram of another level converter in the prior art, Figure 2 In the example, VSS1~VDD1 and VSS2~VDD2 are different voltage domains, and VSS2>VSS1, VDD2>VDD1. Figure 1 Similarly, M1, M2, M3, and M4 are low-voltage NMOS devices, M1 and M2 are used as input pairs, and M3 and M4 are used as protection transistors; M5 and M6 are high-voltage PMOS transistors, of which M5 is connected in a diode manner. Inverter INV1 is an inverter composed of low-voltage devices, and inverters INV2 and INV3 are inverters composed of high-voltage devices.

[0039] Figure 2 The working principle of the circuit is as follows: when the input signal is VDD1 voltage, M1 is turned on, M2 is turned off, and M5 self-biases to generate a bias voltage so that M5 and M6 are both turned on. At this time, under the pull-up action of M6, the output voltage at its drain end is pulled up to VDD2, thereby completing the voltage conversion from VDD1 to VDD2. However, since M1, M3, and M5 are all in the on state, a current path is formed, that is, VDD2 flows to the ground VSS1 after passing through M5, M3, and M1, so that the circuit on the left always has static power consumption when the input is VDD1. Similarly, when the input signal switches from VDD1 to VSS1, M1 is turned off, M2 is turned on, and M5 and M6 are both turned off. At this time, the voltage at the drain end of M6 is pulled down to VSS1 by M2 and M4; the signal then passes through inverter INV2 and inverter INV3 to obtain VSS2, completing the voltage conversion from VSS1 to VSS2.

[0040] Due to the self-bias of M5, the duty cycle of the output mainly depends on the ratio of PMOS to NMOS. By selecting the appropriate size ratio of the device, the output signal can get a good duty cycle. However, the delay of this structure is still large, the high-frequency response is not fast enough, and the static power consumption when the input signal is VDD1 affects the energy efficiency of the DDR interface.

[0041] In view of this, in order to improve the above technical problems, the present application provides a level conversion circuit, which reduces signal delay and duty cycle loss by adding an AC path.

[0042] The level converter provided in this application is described below by way of example: As an alternative implementation, see Figure 3 and Figure 4 The level conversion circuit includes an input port 110, a capacitor 120, a first level conversion module 130, a second level conversion module 140 and an output port 150, wherein two ends of the capacitor 120 are electrically connected to the input port 110 and the output port 150 respectively, an input end of the first level conversion module 130 is connected to the input port 110, an output end of the first level conversion module 130 is electrically connected to an input end of the second level conversion module 140, and an output end of the second level conversion module 140 is electrically connected to the output port 150; wherein, when the signal frequency is not zero, the capacitor 120 forms an AC path, and the first level conversion module 130 and the second level conversion module 140 form a DC path; and the first level conversion module 130 is used to convert a first signal inputted at the input end into an opposite second signal, and the second level conversion module 140 is used to convert the second signal into an opposite third signal; the swing amplitudes of the first signal and the third signal are equal, the first signal is a signal located in the first voltage domain, the third signal is a signal located in the second voltage domain, and the power supply voltage and the ground voltage of the second voltage domain are respectively greater than the power supply voltage and the ground voltage of the first voltage domain.

[0043] It can be understood that, since the AC path constructed by capacitor 120 is added to the level conversion circuit provided by the present application, when the input signal is a signal with a non-zero frequency, the signal can be transmitted through the AC path and the DC path at the same time. In addition, due to the inherent characteristics of the coupling of capacitor 120, the level conversion of high-speed signals can be greatly accelerated, and the delay of the entire level conversion circuit can be reduced to the picosecond level, which greatly reduces the signal delay of the entire level conversion circuit. At the same time, the DC path ensures the stability of the signal, thereby greatly reducing the signal delay of the entire level conversion circuit while meeting the stability requirements.

[0044] That is, when the signal transmission frequency is not zero, the AC path constructed by the capacitor 120 can quickly couple the signal of the input port 110 to the output port 150, so as to achieve signal transmission with lower delay. At the same time, the signal of the input port 110 will also be transmitted to the output port 150 through the DC path constructed by the first level conversion module 130 and the second level conversion module 140. It should be noted that the signal transmission speed of the DC path will be slower than the signal transmission speed of the AC path, so the signal of the AC path will be transmitted to the output port 150 first, and the signal of the DC path will lag behind the signal of the AC path. In addition, the stability of the DC path is stronger, so for the entire level conversion circuit, it can significantly shorten the signal delay while meeting the stability requirements.

[0045] In addition, since the capacitor 120 coupling can synchronize the jump of the input signal, the duty cycle loss of the output signal is small, thereby making the quality of the output signal better.

[0046] As an implementation, see Figure 3 The first level conversion module 130 includes a signal pull-down unit 131, a signal pull-up unit 132 and a feedback loop unit 133. The signal pull-up unit 132 and the signal pull-down unit 131 are both connected to the input port 110. The signal pull-up unit 132 and the feedback loop unit 133 are also connected to the first node. The signal pull-down unit 131 is also connected to the ground of the first voltage domain. The signal pull-down unit 131, the feedback loop unit 133 and the input end of the second level conversion module 140 are all connected to the second node; wherein, when the first signal is a high-level signal, the signal pull-down unit 131 is turned on, and the signal pull-up unit 132 is turned off; when the first signal is a low-level signal, the signal pull-up unit 132 is turned on, and the signal pull-down unit 131 is turned off.

[0047] It can be understood that the first signal described in the present application is the input signal at the input port 110, the second signal is the signal at the second node position, and the third signal is the output signal at the output port 150. And, Figure 3 In the figure, ground 1 to power supply 1 represents the first voltage domain, ground 2 to power supply 2 represents the second voltage domain, and ground 1 < ground 2, power supply 1 < power supply 2. On this basis, the swing of the first signal is ground 1 to power supply 1, the swing of the second signal is ground 1 to power supply 2, and the swing of the third signal is ground 2 to power supply 2.

[0048] It should be noted that the signal pull-up unit 132 and the signal pull-down unit 131 described in the present application are both for the signal at the output end of the first level conversion module 130, that is, for the signal of the second node. When the signal pull-up unit 132 is turned on, the signal of the second node is pulled up to a high level; when the signal pull-down unit 131 is turned on, the signal of the second node is pulled down to ground.

[0049] It can be understood that in the present application, the first level conversion module 130 realizes the function of an inverter. When the input port 110 inputs a high-level signal of the first voltage domain, the second node outputs a low-level signal of the first voltage domain; and when the input port 110 inputs a low-level signal of the first voltage domain, the second node outputs a high-level signal of the second voltage domain.

[0050] Among them, the signal pull-down unit 131 includes a first transistor M1 and a second transistor M2, the feedback loop unit 133 includes a third transistor M3 and a fourth transistor M4, and the signal pull-up unit 132 includes a fifth transistor M5; the gate of the first transistor M1 is connected to the input port 110, the source of the first transistor M1 is connected to the ground of the first voltage domain, the drain of the first transistor M1 is electrically connected to the source of the second transistor M2, the gate of the second transistor M2 is connected to the power supply of the first voltage domain, and the drain of the second transistor M2 is connected to the second node; the gate of the third transistor M3 and the drain of the fourth transistor M4 are both connected to the first node, the drain of the third transistor M3 and the gate of the fourth transistor M4 are connected to the second node, and the source of the third transistor M3 and the source of the fourth transistor M4 are both connected to the power supply of the second voltage domain; the gate of the fifth transistor M5 is connected to the power supply of the first voltage domain, the source of the fifth transistor M5 is connected to the input port 110, and the drain of the fifth transistor M5 is connected to the first node.

[0051] In the present application, in order to minimize the delay of the signal in the DC path, low-voltage tubes are used as much as possible in the entire level conversion circuit. Therefore, in the first level conversion module 130, the first transistor M1, the second transistor M2 and the fifth transistor M5 use low-voltage NMOS tubes, and the third transistor M3 and the fourth transistor M4 use high-voltage PMOS tubes; wherein the lowest withstand voltage of the high-voltage PMOS tube is greater than the highest withstand voltage of the low-voltage NMOS tube. For example, the withstand voltage of the low-voltage NMOS tube is generally less than 1.05V, while the lowest withstand voltage of the high-voltage PMOS tube is generally greater than or equal to 1.1V.

[0052] Furthermore, in the circuit implementation, if the initial voltage of the second node is regarded as 0V, the fourth transistor M4 can be regarded as a conducting state. Therefore, when the fifth transistor M5 is turned on, it is necessary to satisfy that the pull-down capability of the fifth transistor M5 is greater than the pull-up capability of the fourth transistor M4, thereby ensuring that the voltage of the first node is gradually pulled down to drive the third transistor M3 to be turned on. On this basis, the present application sets the width-to-length ratio of the fifth transistor M5 to be greater than or equal to twice the width-to-length ratio of the fourth transistor M4, so as to ensure that when the fifth transistor M5 is turned on, the voltage of the first node can be quickly pulled down.

[0053] Similarly, for the first transistor M1 and the second transistor M2, their pull-down capabilities also need to be greater than the pull-up capabilities of the third transistor M3. It should be noted that the second transistor M2, as a protection transistor for the first transistor M1, generally needs to set the parameters of the first transistor M1 and the second transistor M2 to be the same. Therefore, the present application sets the width-to-length ratio of the first transistor M1 and the second transistor M2 to be greater than or equal to the width-to-length ratio of the third transistor M3.

[0054] Based on the circuit structure of the first level conversion module 130, further analysis shows that when the input port 110 inputs a high-level signal, the first transistor M1 is turned on. Since the first transistor M1 adopts a low-voltage tube, the second node voltage can be quickly pulled down to the ground 1. When the input port 110 inputs a low-level signal, the fifth transistor M5 is turned on, driving the third transistor M3 to turn on, and then the second node voltage is pulled up to the power supply 2. At this time, since the third transistor M3 adopts a high-voltage tube, its conduction rate is slow, resulting in a large difference in the actual signal delay in the process of pulling the second node voltage up to the power supply 2 and pulling it down to the ground 1. That is, in the process of pulling up the second node, the pull-up jump delay is high, which is not conducive to the stability of the operation of the entire circuit. Especially after the parameters of each transistor are determined, if the pull-up jump delay of the second node is large, it may cause the performance of the entire circuit to deteriorate. For example, after the AC path has transmitted the signal of the first cycle to the output port 150, if the signal delay difference between the DC path and the AC path is large, the DC path may still be in the process of signal transmission while the AC path transmits the signal of the second cycle to the output port 150. In this case, the signal of the second cycle of the AC path and the signal of the first cycle of the DC path will cancel each other out, resulting in poor performance of the entire circuit.

[0055] In view of this, in order to increase the rate at which the signal jumps to a high level, the level conversion circuit provided in the present application also includes a pull-up jump acceleration module 160, which is electrically connected to the output end of the capacitor 120 and the input end of the second level conversion module 140, respectively; wherein the pull-up jump acceleration module 160 is used to accelerate the jump speed of the high level when the first level conversion module 130 outputs a high level.

[0056] In one implementation, the pull-up jump acceleration module 160 includes a sixth transistor M6 and a seventh transistor M7, the drain of the sixth transistor M6 is connected to the input end of the second level conversion module 140, the gate of the sixth transistor M6 is connected to the ground of the second voltage domain, the source of the sixth transistor M6 is electrically connected to the drain of the seventh transistor M7, the source of the seventh transistor M7 is connected to the power supply of the second voltage domain, and the gate of the seventh transistor M7 is connected to the output end of the capacitor 120. The sixth transistor M6 and the seventh transistor M7 are both low-voltage PMOS tubes.

[0057] It can be understood that the sixth transistor M6 serves as a protection transistor for the seventh transistor M7. At the same time, since both the sixth transistor M6 and the seventh transistor M7 are low-voltage transistors, the conduction rate of the pull-up transition acceleration module 160 can be faster.

[0058] Furthermore, by setting up the pull-up transition acceleration module 160, when VSS1 is input to the input port 110, the AC path constructed by the capacitor 120 can quickly couple the signal to the output port 150, so that the voltage at the output end of the capacitor 120 (the right side of the capacitor 120 in the figure) is quickly pulled down, driving the seventh transistor M7 to turn on, and then quickly pulling up the voltage of the second node to the power supply 2, thereby realizing a rapid flip jump of the high-level signal of the second node.

[0059] It can be seen that by setting the pull-up jump acceleration module 160, it can be ensured that in the circuit as a whole, the AC path is always faster than the DC path, but the signal delay between the AC path and the DC path will not be too different, thereby ensuring the stable operation of the entire circuit.

[0060] In the present application, the second level conversion module 140 also performs the function of an inverter. As an implementation method, the second level conversion module 140 adopts a push-pull structure, that is, the second level conversion module 140 includes an eighth transistor M8 and a ninth transistor M9, the gate of the eighth transistor M8 and the gate of the ninth transistor M9 are both connected to the output end of the first level conversion module 130, the drain of the eighth transistor M8 and the drain of the ninth transistor M9 are both connected to the output port 150, the source of the eighth transistor M8 is connected to the power supply of the second voltage domain, and the source of the ninth transistor M9 is connected to the ground of the second voltage domain; wherein, when the second signal is a high level signal, the eighth transistor M8 is turned off, the ninth transistor M9 is turned on, and the third signal is a low level signal; when the second signal is a low level signal, the eighth transistor M8 is turned on, the ninth transistor M9 is turned off, and the third signal is a high level signal.

[0061] It should be noted that the eighth transistor M8 may be a high-voltage PMOS transistor, and the ninth transistor M9 may be a low-voltage NMOS transistor.

[0062] Combine the following Figure 4 , the working principle of the level conversion circuit provided in this application is described in detail: like Figure 4As shown, the level conversion circuit provided in the embodiment of the present application has two signal paths, an AC path is constructed through the capacitor 120, and a DC path is constructed through the first level conversion module 130 and the second level conversion module 140. And the AC path and the DC path can process different frequency components of the signal respectively. When the signal frequency is 0, it means that the input DC voltage is input. At this time, the AC path is equivalent to an open circuit (the capacitor 120 has a DC isolation characteristic), so the signal can only be transmitted through the DC path. When the signal frequency is not zero, the signal can be transmitted through the AC path and the DC path together, and the signal transmission speed of the DC path will lag behind the transmission speed of the AC path.

[0063] For example, for the high-frequency part of the signal, such as the rising edge and falling edge of the high-speed signal during the switching process, the high-frequency path formed by the capacitor 120 is transmitted, and the signal of the input port 110 can be quickly coupled to the output port 150 through the capacitor 120. Since the high-frequency signal needs to be coupled through the capacitor 120, in order to ensure the integrity of the high-frequency signal, the swing of the input signal and the output signal needs to be consistent, power supply 1-ground 1 = power supply 2-ground 2, so ground 2 = power supply 2-(power supply 1-ground 1), where power supply 1-ground 1 and power supply 2-ground 2 both represent the swing values ​​of the first voltage domain and the second voltage domain. For example, if the first voltage domain is 0V~0.8V, the swing value of the first voltage domain is 0.8V; if the swing value of the second voltage domain is 0.3V~0.8V, the swing value of the second voltage domain is also 0.8V. Among them, the voltage values ​​of the first voltage domain and the second voltage domain can be generated by an on-chip low drop linear regulator (Low Drop Linear Regulator, LDO) or other circuit methods.

[0064] If each power supply is powered on successfully, the initial state of the input signal is the voltage value VDD1 of power supply 1. After the signal passes through the DC path, the output voltage is the voltage value VDD2 of power supply 2. Therefore, the voltages of the two plates of the feedback capacitor 120 are determined. At this time, the charge stored in the capacitor 120 is: Q0=U*C=(VDD2-VDD1)*C; Here, U represents the voltage across the capacitor 120 , and C represents the capacitor 120 .

[0065] At the next data cycle, when the input signal drops from the voltage value VDD1 to the voltage value VSS1 of ground 1, the output voltage is Vout1, and the charge stored in the capacitor 120 when the high-frequency signal reaches the steady state is: Q1=U*C=(Vout1-VSS1)*C; Since the signal switching process is a high-frequency signal, the high-frequency signal can quickly pass through the AC path formed by the capacitor 120; and the DC path can be equivalent to two sets of inverters, and the time for the high-frequency signal to pass through the DC path is longer than that of the AC path. Therefore, for the high-frequency signal, when it reaches the output port 150 through the AC path, the signal of its DC path has not yet arrived. At this time, the amount of charge stored in the capacitor 120 before and after is conserved, that is, Q0 is equal to Q1, and it can be obtained: Vout1=VDD2-VDD1+VSS1= VDD2-(VDD1-VSS1); That is, Vout1=VSS2 at this time.

[0066] Therefore, the output signal jump can be greatly accelerated by coupling through capacitor 120, and the delay of the AC path constructed by capacitor 120 can be within a few picoseconds. Similarly, when the input signal jumps from VSS1 to VDD1 voltage value, the steady-state voltage of the AC path signal reaching the output port 150 is Vout2, and the charge stored in capacitor 120 is: Q2=(Vout2-VDD1)*C; According to the conservation of charges before and after, Q2 is equal to Q1, that is, Vout2 = VDD1 + VSS2 - VSS1 = VDD2; thus, high-speed conversion of the voltage domain can be completed.

[0067] At the same time, since the rising edge and the falling edge of the signal are directly coupled to the output port 150 through the capacitor 120, the rising and falling speeds of the output signal are synchronized with the input signal, so the duty cycle loss of the output signal is very small, and the duty cycle loss is less than 0.1%, ensuring good duty cycle performance during high-speed signal level conversion.

[0068] At the same time, the present invention also uses a feedback structure to effectively ensure the low static leakage current of the circuit. The first transistor M1 and the second transistor M2 are used as paths for transmitting input high levels, and the fifth transistor M5, the third transistor M3 and the capacitor 120, the seventh transistor M7, and the sixth transistor M6 are used as paths for transmitting input low-level signals. When the input is at a low level, the fifth transistor M5 is turned on, the first transistor M1 is turned off, and the first node is pulled to a low level under the action of the fifth transistor M5 with a stronger drive; at this time, the third transistor M3 is turned on, the second node is pulled to a high level, and the voltage of the second node is fed back to the fourth transistor M4, so that the fourth transistor M4 is turned off; finally, the first node reaches a steady-state low level, and the second node reaches the level value of the steady-state power supply 2. Similarly, when the input is at a high level, the first transistor M1 and the second transistor M2 are turned on, the fifth transistor M5 is turned off, and the second node is gradually pulled down under the strong driving of the first transistor M1 and the second transistor M2; the voltage of the second node is fed back to the fourth transistor M4, forcing the fourth transistor M4 to be turned on, thereby pulling up the first node, and finally the third transistor M3 is turned off, the second node reaches the steady-state ground 1 level, and the first node reaches the voltage value of the power supply 2, thereby ensuring that there is no static current in the steady state. At the same time, since the swing of the second node signal is ground 1 ~ power supply 2, the ground 2 voltage is higher than the ground 1 voltage, so there is no static leakage current in the eighth transistor M8 and the ninth transistor M9, and the static power consumption of the entire circuit is relatively small.

[0069] It can be seen that compared with the traditional level converter, the level conversion circuit provided in this application has at least the following advantages: 1. The level converter adopts a capacitive coupling structure. The feedback capacitor 120 can greatly speed up the level conversion of high-speed signals. The delay can be achieved at the picosecond level and ensure a good duty cycle of the signal.

[0070] 2. The level converter has two signal paths, and the AC path can speed up signal transitions. Moreover, the DC path can directly reset the voltage of the upper and lower plates of the capacitor 120 after the power supply is powered on, without the need for an additional reset circuit.

[0071] 3. The level conversion circuit uses a feedback structure to achieve low static leakage current of the level converter. In addition, the entire circuit has the advantages of relatively simple structure, small circuit area and low static power consumption.

[0072] Based on the above implementation, an embodiment of the present application further provides an electronic device, which includes the above level conversion circuit.

[0073] In summary, the present application provides a level conversion circuit and an electronic device, the level conversion circuit comprising an input port, a capacitor, a first level conversion module, a second level conversion module and an output port, the two ends of the capacitor are electrically connected to the input port and the output port respectively, the input end of the first level conversion module is connected to the input port, the output end of the first level conversion module is electrically connected to the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected to the output port; wherein, when the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path; and the first level conversion module is used to convert a first signal input at the input end into an opposite second signal, and the second level conversion module is used to convert the second signal into an opposite third signal; the swing amplitudes of the first signal and the third signal are equal, the first signal is a signal located in the first voltage domain, the third signal is a signal located in the second voltage domain, and the power supply voltage and the ground voltage of the second voltage domain are respectively greater than the power supply voltage and the ground voltage of the first voltage domain. Since the AC path formed by the capacitor is added to the level conversion circuit provided by the present application, when the signal frequency is not zero, the signal of the input port can be transmitted through the AC path and the DC path, and due to the inherent characteristics of the capacitive coupling, the level conversion of the signal can be greatly accelerated, and the delay of the entire level conversion circuit is reduced to the picosecond level, which greatly reduces the signal delay of the entire level conversion circuit. In addition, the DC path ensures the stability of the signal, thereby greatly reducing the signal delay while the entire level conversion circuit meets the stability requirements. In addition, since the capacitive coupling can synchronize the jump of the input signal, the duty cycle loss of the output signal is small, which can make the quality of the output signal higher.

[0074] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0075] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit includes an input port, a capacitor, a first level conversion module, a second level conversion module and an output port, the two ends of the capacitor are electrically connected to the input port and the output port respectively, the input end of the first level conversion module is connected to the input port, the output end of the first level conversion module is electrically connected to the input end of the second level conversion module, and the output end of the second level conversion module is electrically connected to the output port; wherein, When the signal frequency is not zero, the capacitor forms an AC path, and the first level conversion module and the second level conversion module form a DC path; and the first level conversion module is used to convert a first signal inputted from the input end into an opposite second signal, and the second level conversion module is used to convert the second signal into an opposite third signal; The first signal and the third signal have the same swing amplitude, the first signal is a signal located in a first voltage domain, the third signal is a signal located in a second voltage domain, and the power supply voltage and ground voltage of the second voltage domain are respectively greater than the power supply voltage and ground voltage of the first voltage domain.

2. The level conversion circuit according to claim 1, characterized in that: The first level conversion module includes a signal pull-down unit, a signal pull-up unit and a feedback loop unit, the signal pull-up unit and the signal pull-down unit are both connected to the input port, the signal pull-up unit and the feedback loop unit are both connected to a first node, the signal pull-down unit is also connected to the ground of the first voltage domain, and the signal pull-down unit, the feedback loop unit and the input end of the second level conversion module are all connected to a second node; wherein, When the first signal is a high level signal, the signal pull-down unit is turned on, and the signal pull-up unit is turned off; When the first signal is a low level signal, the signal pull-up unit is turned on, and the signal pull-down unit is turned off.

3. The level conversion circuit according to claim 2, characterized in that: The signal pull-down unit includes a first transistor and a second transistor, the feedback loop unit includes a third transistor and a fourth transistor, and the signal pull-up unit includes a fifth transistor; The gate of the first transistor is connected to the input port, the source of the first transistor is connected to the ground of the first voltage domain, the drain of the first transistor is electrically connected to the source of the second transistor, the gate of the second transistor is connected to the power supply of the first voltage domain, and the drain of the second transistor is connected to the second node; The gate of the third transistor and the drain of the fourth transistor are both connected to the first node, the drain of the third transistor and the gate of the fourth transistor are connected to the second node, and the source of the third transistor and the source of the fourth transistor are both connected to the power supply of the second voltage domain; A gate of the fifth transistor is connected to a power source of the first voltage domain, a source of the fifth transistor is connected to the input port, and a drain of the fifth transistor is connected to the first node.

4. The level conversion circuit according to claim 3, characterized in that: The first transistor, the second transistor and the fifth transistor are low-voltage NMOS transistors, and the third transistor and the fourth transistor are high-voltage PMOS transistors; wherein, The lowest withstand voltage of the high-voltage PMOS tube is greater than the highest withstand voltage of the low-voltage NMOS tube.

5. The level conversion circuit according to claim 3, characterized in that: The width-to-length ratio of the fifth transistor is greater than or equal to twice the width-to-length ratio of the fourth transistor; The width-to-length ratios of the first transistor and the second transistor are both greater than or equal to the width-to-length ratio of the third transistor.

6. The level conversion circuit according to claim 1, characterized in that: The level conversion circuit further includes a pull-up jump acceleration module, and the pull-up jump acceleration module is electrically connected to the output end of the capacitor and the input end of the second level conversion module respectively; wherein, The pull-up transition acceleration module is used to accelerate the transition speed of the high level when the first level conversion module outputs a high level.

7. The level conversion circuit according to claim 6, characterized in that: The pull-up jump acceleration module includes a sixth transistor and a seventh transistor, the drain of the sixth transistor is connected to the input end of the second level conversion module, the gate of the sixth transistor is connected to the ground of the second voltage domain, the source of the sixth transistor is electrically connected to the drain of the seventh transistor, the source of the seventh transistor is connected to the power supply of the second voltage domain, and the gate of the seventh transistor is connected to the output end of the capacitor.

8. The level conversion circuit according to claim 7, characterized in that: The sixth transistor and the seventh transistor are both low-voltage PMOS transistors.

9. The level conversion circuit according to claim 1, characterized in that: The second level conversion module includes an eighth transistor and a ninth transistor, the gate of the eighth transistor and the gate of the ninth transistor are both connected to the output end of the first level conversion module, the drain of the eighth transistor and the drain of the ninth transistor are both connected to the output port, the source of the eighth transistor is connected to the power supply of the second voltage domain, and the source of the ninth transistor is connected to the ground of the second voltage domain; wherein, When the second signal is a high level signal, the eighth transistor is turned off, the ninth transistor is turned on, and the third signal is a low level signal; When the second signal is a low level signal, the eighth transistor is turned on, the ninth transistor is turned off, and the third signal is a high level signal.

10. An electronic device, characterized in that: The electronic device comprises the level conversion circuit according to any one of claims 1 to 9.

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